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pinctrl: renesas: Add R8A779H0 V4M PFC tables
[thirdparty/u-boot.git] / drivers / pinctrl / renesas / sh_pfc.h
CommitLineData
a2a14854
MV		 1/* SPDX-License-Identifier: GPL-2.0
2 *
910df4d0
MV		 3 * SuperH Pin Function Controller Support
4 *
5 * Copyright (c) 2008 Magnus Damm
910df4d0
MV		 6 */
7
8#ifndef __SH_PFC_H
9#define __SH_PFC_H
10
11#include <linux/stringify.h>
12
13enum {
14 PINMUX_TYPE_NONE,
15 PINMUX_TYPE_FUNCTION,
16 PINMUX_TYPE_GPIO,
17 PINMUX_TYPE_OUTPUT,
18 PINMUX_TYPE_INPUT,
19};
20
a2a14854
MV		 21#define SH_PFC_PIN_NONE U16_MAX
22
910df4d0
MV		 23#define SH_PFC_PIN_CFG_INPUT (1 << 0)
24#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
25#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
26#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
a2a14854
MV		 27#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
28 SH_PFC_PIN_CFG_PULL_DOWN)
f3a163dc
MV		 29
30#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
31#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4)
32#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4)
33#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4)
34
35#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)
a2a14854 36
910df4d0
MV		 37#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
38
39struct sh_pfc_pin {
910df4d0
MV		 40 const char *name;
41 unsigned int configs;
a2a14854
MV		 42 u16 pin;
43 u16 enum_id;
910df4d0
MV		 44};
45
3e812421
MV		 46#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \
47 .name = #alias, \
48 .pins = _name##_pins, \
49 .mux = _name##_mux, \
50 .nr_pins = ARRAY_SIZE(_name##_pins) + \
51 BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \
52}
53#define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name)
54
55/*
56 * Define a pin group referring to a subset of an array of pins.
57 */
58#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \
59 .name = #_name, \
60 .pins = data##_pins + first, \
61 .mux = data##_mux + first, \
62 .nr_pins = n + \
63 BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \
64 BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \
65}
66
67/*
68 * Define a pin group for the data pins of a resizable bus.
69 * An optional 'suffix' argument is accepted, to be used when the same group
70 * can appear on a different set of pins.
71 */
72#define BUS_DATA_PIN_GROUP(base, n, ...) \
73 SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n)
910df4d0
MV		 74
75struct sh_pfc_pin_group {
76 const char *name;
77 const unsigned int *pins;
78 const unsigned int *mux;
79 unsigned int nr_pins;
80};
81
3e812421
MV		 82#define SH_PFC_FUNCTION(n) { \
83 .name = #n, \
84 .groups = n##_groups, \
85 .nr_groups = ARRAY_SIZE(n##_groups), \
86}
910df4d0
MV		 87
88struct sh_pfc_function {
89 const char *name;
90 const char * const *groups;
91 unsigned int nr_groups;
92};
93
94struct pinmux_func {
95 u16 enum_id;
96 const char *name;
97};
98
99struct pinmux_cfg_reg {
100 u32 reg;
101 u8 reg_width, field_width;
7f2e60f1
ER		 102#ifdef DEBUG
103 u16 nr_enum_ids; /* for variable width regs only */
104#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
105#else
106#define SET_NR_ENUM_IDS(n)
107#endif
910df4d0 108 const u16 *enum_ids;
3e812421 109 const s8 *var_field_width;
910df4d0
MV		 110};
111
7f2e60f1
ER		 112#define GROUP(...) __VA_ARGS__
113
910df4d0
MV		 114/*
115 * Describe a config register consisting of several fields of the same width
116 * - name: Register name (unused, for documentation purposes only)
117 * - r: Physical register address
118 * - r_width: Width of the register (in bits)
119 * - f_width: Width of the fixed-width register fields (in bits)
7f2e60f1
ER		 120 * - ids: For each register field (from left to right, i.e. MSB to LSB),
121 * 2^f_width enum IDs must be specified, one for each possible
122 * combination of the register field bit values, all wrapped using
123 * the GROUP() macro.
910df4d0 124 */
7f2e60f1
ER		 125#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
126 .reg = r, .reg_width = r_width, \
127 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
128 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
3e812421
MV		 129 (r_width / f_width) << f_width), \
130 .enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids }
910df4d0
MV		 131
132/*
133 * Describe a config register consisting of several fields of different widths
134 * - name: Register name (unused, for documentation purposes only)
135 * - r: Physical register address
136 * - r_width: Width of the register (in bits)
7f2e60f1
ER		 137 * - f_widths: List of widths of the register fields (in bits), from left
138 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
3e812421
MV		 139 * Reserved fields are indicated by negating the field width.
140 * - ids: For each non-reserved register field (from left to right, i.e. MSB
141 * to LSB), 2^f_widths[i] enum IDs must be specified, one for each
142 * possible combination of the register field bit values, all wrapped
143 * using the GROUP() macro.
910df4d0 144 */
7f2e60f1
ER		 145#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
146 .reg = r, .reg_width = r_width, \
3e812421 147 .var_field_width = (const s8 []) { f_widths, 0 }, \
7f2e60f1
ER		 148 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
149 .enum_ids = (const u16 []) { ids }
910df4d0
MV		 150
151struct pinmux_drive_reg_field {
152 u16 pin;
153 u8 offset;
154 u8 size;
155};
156
157struct pinmux_drive_reg {
158 u32 reg;
3e812421 159 const struct pinmux_drive_reg_field fields[10];
910df4d0
MV		 160};
161
162#define PINMUX_DRIVE_REG(name, r) \
163 .reg = r, \
164 .fields =
165
3e812421 166struct pinmux_bias_reg { /* At least one of puen/pud must exist */
bf8d2dab 167 u32 puen; /* Pull-enable or pull-up control register */
3e812421 168 u32 pud; /* Pull-up/down or pull-down control register */
bf8d2dab
MV		 169 const u16 pins[32];
170};
171
172#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
173 .puen = r1, \
174 .pud = r2, \
175 .pins =
176
177struct pinmux_ioctrl_reg {
178 u32 reg;
179};
180
910df4d0
MV		 181struct pinmux_data_reg {
182 u32 reg;
183 u8 reg_width;
184 const u16 *enum_ids;
185};
186
187/*
188 * Describe a data register
189 * - name: Register name (unused, for documentation purposes only)
190 * - r: Physical register address
191 * - r_width: Width of the register (in bits)
7f2e60f1
ER		 192 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
193 * enum ID must be specified, all wrapped using the GROUP() macro.
910df4d0 194 */
7f2e60f1
ER		 195#define PINMUX_DATA_REG(name, r, r_width, ids) \
196 .reg = r, .reg_width = r_width + \
197 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
198 r_width), \
199 .enum_ids = (const u16 [r_width]) { ids }
910df4d0
MV		 200
201struct pinmux_irq {
202 const short *gpios;
203};
204
205/*
206 * Describe the mapping from GPIOs to a single IRQ
207 * - ids...: List of GPIOs that are mapped to the same IRQ
208 */
3e812421
MV		 209#define PINMUX_IRQ(ids...) { \
210 .gpios = (const short []) { ids, -1 } \
211}
910df4d0
MV		 212
213struct pinmux_range {
214 u16 begin;
215 u16 end;
216 u16 force;
217};
218
bf8d2dab
MV		 219struct sh_pfc_window {
220 phys_addr_t phys;
221 void __iomem *virt;
222 unsigned long size;
910df4d0
MV		 223};
224
225struct sh_pfc_pin_range;
226
227struct sh_pfc {
228 struct device *dev;
229 const struct sh_pfc_soc_info *info;
230
231 void *regs;
232
233 struct sh_pfc_pin_range *ranges;
234 unsigned int nr_ranges;
235
236 unsigned int nr_gpio_pins;
237
238 struct sh_pfc_chip *gpio;
239};
240
241struct sh_pfc_soc_operations {
242 int (*init)(struct sh_pfc *pfc);
243 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
244 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
245 unsigned int bias);
3e812421
MV		 246 int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl);
247 int (*pin_to_portcr)(unsigned int pin);
910df4d0
MV		 248};
249
250struct sh_pfc_soc_info {
251 const char *name;
252 const struct sh_pfc_soc_operations *ops;
253
254 struct pinmux_range input;
255 struct pinmux_range output;
256 struct pinmux_range function;
257
258 const struct sh_pfc_pin *pins;
259 unsigned int nr_pins;
260 const struct sh_pfc_pin_group *groups;
261 unsigned int nr_groups;
262 const struct sh_pfc_function *functions;
263 unsigned int nr_functions;
264
265 const struct pinmux_cfg_reg *cfg_regs;
266 const struct pinmux_drive_reg *drive_regs;
bf8d2dab
MV		 267 const struct pinmux_bias_reg *bias_regs;
268 const struct pinmux_ioctrl_reg *ioctrl_regs;
910df4d0
MV		 269 const struct pinmux_data_reg *data_regs;
270
271 const u16 *pinmux_data;
272 unsigned int pinmux_data_size;
273
6fc323c1 274 u32 unlock_reg; /* can be literal address or mask */
910df4d0
MV		 275};
276
bf8d2dab
MV		 277u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
278void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
910df4d0 279
3e812421
MV		 280extern const struct sh_pfc_soc_info emev2_pinmux_info;
281extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
282extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
283extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
284extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
285extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
286extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
287extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
43ef8032 288extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
c5f37625 289extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
220f308a 290extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
975154bc 291extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
3e812421
MV		 292extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
293extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
7547ad4c 294extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
427c75df 295extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
ab2d09b4 296extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
427c75df 297extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
34e93605 298extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
3e812421
MV		 299extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
300extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
301extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
c6435c31 302extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
c106bb53 303extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
f497ec36 304extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
cb13e46a 305extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
a59e6976 306extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
df8adad5 307extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
1b1834c0 308extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
de4c777e 309extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
995a857a 310extern const struct sh_pfc_soc_info r8a779h0_pinmux_info;
8719ca81 311
910df4d0
MV		 312/* -----------------------------------------------------------------------------
313 * Helper macros to create pin and port lists
314 */
315
316/*
317 * sh_pfc_soc_info pinmux_data array macros
318 */
319
320/*
321 * Describe generic pinmux data
322 * - data_or_mark: *_DATA or *_MARK enum ID
323 * - ids...: List of enum IDs to associate with data_or_mark
324 */
325#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
326
327/*
328 * Describe a pinmux configuration without GPIO function that needs
329 * configuration in a Peripheral Function Select Register (IPSR)
330 * - ipsr: IPSR field (unused, for documentation purposes only)
331 * - fn: Function name, referring to a field in the IPSR
332 */
333#define PINMUX_IPSR_NOGP(ipsr, fn) \
334 PINMUX_DATA(fn##_MARK, FN_##fn)
335
336/*
337 * Describe a pinmux configuration with GPIO function that needs configuration
338 * in both a Peripheral Function Select Register (IPSR) and in a
339 * GPIO/Peripheral Function Select Register (GPSR)
340 * - ipsr: IPSR field
341 * - fn: Function name, also referring to the IPSR field
342 */
343#define PINMUX_IPSR_GPSR(ipsr, fn) \
344 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
345
346/*
347 * Describe a pinmux configuration without GPIO function that needs
348 * configuration in a Peripheral Function Select Register (IPSR), and where the
349 * pinmux function has a representation in a Module Select Register (MOD_SEL).
350 * - ipsr: IPSR field (unused, for documentation purposes only)
351 * - fn: Function name, also referring to the IPSR field
352 * - msel: Module selector
353 */
354#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
355 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
356
357/*
358 * Describe a pinmux configuration with GPIO function where the pinmux function
359 * has no representation in a Peripheral Function Select Register (IPSR), but
360 * instead solely depends on a group selection.
361 * - gpsr: GPSR field
362 * - fn: Function name, also referring to the GPSR field
363 * - gsel: Group selector
364 */
365#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
366 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
367
368/*
369 * Describe a pinmux configuration with GPIO function that needs configuration
370 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
371 * Function Select Register (GPSR), and where the pinmux function has a
372 * representation in a Module Select Register (MOD_SEL).
373 * - ipsr: IPSR field
374 * - fn: Function name, also referring to the IPSR field
375 * - msel: Module selector
376 */
377#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
378 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
379
8719ca81
MV		 380/*
381 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
382 * an additional select register that controls physical multiplexing
383 * with another pin.
384 * - ipsr: IPSR field
385 * - fn: Function name, also referring to the IPSR field
386 * - psel: Physical multiplexing selector
387 * - msel: Module selector
388 */
389#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
390 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
391
392/*
393 * Describe a pinmux configuration in which a pin is physically multiplexed
394 * with other pins.
a2a14854 395 * - ipsr: IPSR field
7f2e60f1 396 * - fn: Function name
8719ca81
MV		 397 * - psel: Physical multiplexing selector
398 */
399#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
a2a14854 400 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
8719ca81 401
910df4d0
MV		 402/*
403 * Describe a pinmux configuration for a single-function pin with GPIO
404 * capability.
405 * - fn: Function name
406 */
407#define PINMUX_SINGLE(fn) \
408 PINMUX_DATA(fn##_MARK, FN_##fn)
409
410/*
411 * GP port style (32 ports banks)
412 */
413
414#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
415 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
416#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
417
a2a14854 418#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
910df4d0 419 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
a2a14854
MV		 420 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
421#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
422
423#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
424 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
910df4d0
MV		 425 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
426 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
427#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
428
c106bb53
MV		 429#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
430 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
bf8d2dab
MV		 431 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
432 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
c106bb53
MV		 433#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
434
3e812421 435#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \
bf8d2dab 436 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
3e812421
MV		 437 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg)
438#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0)
439
440#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
441 PORT_GP_CFG_7(bank, fn, sfx, cfg), \
910df4d0
MV		 442 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
443#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
444
445#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
446 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
447 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
448#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
449
450#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
451 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
452 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
453#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
454
634f9f0d 455#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
910df4d0 456 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
8719ca81 457 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
634f9f0d
TK		 458#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
459
460#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
8719ca81 461 PORT_GP_CFG_11(bank, fn, sfx, cfg), \
910df4d0
MV		 462 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
463#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
464
3e812421 465#define PORT_GP_CFG_13(bank, fn, sfx, cfg) \
910df4d0 466 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
3e812421
MV		 467 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)
468#define PORT_GP_13(bank, fn, sfx) PORT_GP_CFG_13(bank, fn, sfx, 0)
469
470#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
471 PORT_GP_CFG_13(bank, fn, sfx, cfg), \
910df4d0
MV		 472 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
473#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
474
475#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
476 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
477 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
478#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
479
480#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
481 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
482 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
483#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
484
485#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
486 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
487 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
488#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
489
490#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
491 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
492 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
493#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
494
3e812421 495#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \
910df4d0 496 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
3e812421
MV		 497 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)
498#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0)
499
500#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
501 PORT_GP_CFG_19(bank, fn, sfx, cfg), \
910df4d0
MV		 502 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
503#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
504
505#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
506 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
507 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
508#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
509
c106bb53 510#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
bf8d2dab
MV		 511 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
512 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
c106bb53
MV		 513#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
514
910df4d0 515#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
bf8d2dab 516 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
910df4d0
MV		 517 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
518#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
519
520#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
521 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
522 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
523#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
524
bf8d2dab 525#define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
910df4d0 526 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
bf8d2dab
MV		 527 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
528#define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
529
530#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
531 PORT_GP_CFG_25(bank, fn, sfx, cfg), \
910df4d0
MV		 532 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
533#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
534
a2a14854 535#define PORT_GP_CFG_27(bank, fn, sfx, cfg) \
910df4d0 536 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
a2a14854
MV		 537 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
538#define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0)
539
540#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
541 PORT_GP_CFG_27(bank, fn, sfx, cfg), \
910df4d0
MV		 542 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
543#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
544
545#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
546 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
547 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
548#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
549
550#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
551 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
552 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
553#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
554
a2a14854 555#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
910df4d0 556 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
a2a14854
MV		 557 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
558#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
559
560#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
561 PORT_GP_CFG_31(bank, fn, sfx, cfg), \
910df4d0
MV		 562 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
563#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
564
565#define PORT_GP_32_REV(bank, fn, sfx) \
566 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
567 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
568 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
569 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
570 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
571 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
572 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
573 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
574 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
575 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
576 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
577 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
578 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
579 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
580 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
581 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
582
583/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
584#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
a2a14854 585#define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str)
910df4d0
MV		 586
587/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
3e812421
MV		 588#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \
589 .pin = (bank * 32) + _pin, \
590 .name = __stringify(_name), \
591 .enum_id = _name##_DATA, \
592 .configs = cfg, \
593}
a2a14854 594#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
910df4d0
MV		 595
596/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
597#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
a2a14854
MV		 598#define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused)
599
600/*
601 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
602 *
603 * The largest GP pin index is obtained by taking the size of a union,
604 * containing one array per GP pin, sized by the corresponding pin index.
605 * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
606 * while the members of a union must be terminated by semicolons, the commas
607 * are absorbed by wrapping them inside dummy attributes.
608 */
609#define _GP_ENTRY(bank, pin, name, sfx, cfg) \
610 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
611#define GP_ASSIGN_LAST() \
612 GP_LAST = sizeof(union { \
613 char dummy[0] __attribute__((deprecated, \
614 CPU_ALL_GP(_GP_ENTRY, unused), \
615 deprecated)); \
616 })
910df4d0
MV		 617
618/*
619 * PORT style (linear pin space)
620 */
621
622#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
623
624#define PORT_10(pn, fn, pfx, sfx) \
625 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
626 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
627 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
628 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
629 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
630
631#define PORT_90(pn, fn, pfx, sfx) \
632 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
633 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
634 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
635 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
636 PORT_10(pn+90, fn, pfx##9, sfx)
637
638/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
639#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
640#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
641
642/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
643#define PINMUX_GPIO(_pin) \
644 [GPIO_##_pin] = { \
645 .pin = (u16)-1, \
646 .name = __stringify(GPIO_##_pin), \
647 .enum_id = _pin##_DATA, \
648 }
649
650/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
3e812421
MV		 651#define SH_PFC_PIN_CFG(_pin, cfgs) { \
652 .pin = _pin, \
653 .name = __stringify(PORT##_pin), \
654 .enum_id = PORT##_pin##_DATA, \
655 .configs = cfgs, \
656}
910df4d0 657
910df4d0
MV		 658/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
659 * PORT_name_OUT, PORT_name_IN marks
660 */
661#define _PORT_DATA(pn, pfx, sfx) \
662 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
663 PORT##pfx##_OUT, PORT##pfx##_IN)
664#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
665
a2a14854
MV		 666/*
667 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
668 *
669 * The largest PORT pin index is obtained by taking the size of a union,
670 * containing one array per PORT pin, sized by the corresponding pin index.
671 * As the fields in the CPU_ALL_PORT() macro definition are separated by
672 * commas, while the members of a union must be terminated by semicolons, the
673 * commas are absorbed by wrapping them inside dummy attributes.
674 */
675#define _PORT_ENTRY(pn, pfx, sfx) \
676 deprecated)); char pfx[pn] __attribute__((deprecated
677#define PORT_ASSIGN_LAST() \
678 PORT_LAST = sizeof(union { \
679 char dummy[0] __attribute__((deprecated, \
680 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \
681 deprecated)); \
682 })
683
910df4d0
MV		 684/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
685#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
686 [gpio - (base)] = { \
687 .name = __stringify(gpio), \
688 .enum_id = data_or_mark, \
689 }
690#define GPIO_FN(str) \
691 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
692
a2a14854
MV		 693/*
694 * Pins not associated with a GPIO port
695 */
696
697#define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg)
698#define PIN_NOGP(pin, name, fn) fn(pin, name, 0)
699
700/* NOGP_ALL - Expand to a list of PIN_id */
701#define _NOGP_ALL(pin, name, cfg) PIN_##pin
702#define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL)
703
704/* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
3e812421
MV		 705#define _NOGP_PINMUX(_pin, _name, cfg) { \
706 .pin = PIN_##_pin, \
707 .name = "PIN_" _name, \
708 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \
709}
a2a14854
MV		 710#define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX)
711
910df4d0
MV		 712/*
713 * PORTnCR helper macro for SH-Mobile/R-Mobile
714 */
3e812421
MV		 715#define PORTCR(nr, reg) { \
716 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \
717 GROUP( \
718 /* PULMD[1:0], handled by .set_bias() */ \
719 /* IE and OE */ \
720 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
721 /* SEC, not supported */ \
722 /* PTMD[2:0] */ \
723 PORT##nr##_FN0, PORT##nr##_FN1, \
724 PORT##nr##_FN2, PORT##nr##_FN3, \
725 PORT##nr##_FN4, PORT##nr##_FN5, \
726 PORT##nr##_FN6, PORT##nr##_FN7 \
727 )) \
728}
910df4d0
MV		 729
730/*
731 * GPIO number helper macro for R-Car
732 */
733#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
734
3e812421
MV		 735/*
736 * Bias helpers
737 */
738const struct pinmux_bias_reg *
739rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
740 unsigned int *bit);
741unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
742void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
743 unsigned int bias);
744
910df4d0 745#endif /* __SH_PFC_H */
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