[people/ms/u-boot.git] / drivers / pinctrl / rockchip / pinctrl_rk3399.c

/*
 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/clock.h>
#include <dm/pinctrl.h>

DECLARE_GLOBAL_DATA_PTR;

struct rk3399_pinctrl_priv {
	struct rk3399_grf_regs *grf;
	struct rk3399_pmugrf_regs *pmugrf;
};

static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
		struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
{
	switch (pwm_id) {
	case PERIPH_ID_PWM0:
		rk_clrsetreg(&grf->gpio4c_iomux,
			     GRF_GPIO4C2_SEL_MASK,
			     GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
		break;
	case PERIPH_ID_PWM1:
		rk_clrsetreg(&grf->gpio4c_iomux,
			     GRF_GPIO4C6_SEL_MASK,
			     GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
		break;
	case PERIPH_ID_PWM2:
		rk_clrsetreg(&pmugrf->gpio1c_iomux,
			     PMUGRF_GPIO1C3_SEL_MASK,
			     PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
		break;
	case PERIPH_ID_PWM3:
		if (readl(&pmugrf->soc_con0) & (1 << 5))
			rk_clrsetreg(&pmugrf->gpio1b_iomux,
				     PMUGRF_GPIO1B6_SEL_MASK,
				     PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
		else
			rk_clrsetreg(&pmugrf->gpio0a_iomux,
				     PMUGRF_GPIO0A6_SEL_MASK,
				     PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
		break;
	default:
		debug("pwm id = %d iomux error!\n", pwm_id);
		break;
	}
}

static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
				      struct rk3399_pmugrf_regs *pmugrf,
				      int i2c_id)
{
	switch (i2c_id) {
	case PERIPH_ID_I2C0:
		rk_clrsetreg(&pmugrf->gpio1b_iomux,
			     PMUGRF_GPIO1B7_SEL_MASK,
			     PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
		rk_clrsetreg(&pmugrf->gpio1c_iomux,
			     PMUGRF_GPIO1C0_SEL_MASK,
			     PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
		break;
	case PERIPH_ID_I2C1:
	case PERIPH_ID_I2C2:
	case PERIPH_ID_I2C3:
	case PERIPH_ID_I2C4:
	case PERIPH_ID_I2C5:
	default:
		debug("i2c id = %d iomux error!\n", i2c_id);
		break;
	}
}

static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
{
	switch (lcd_id) {
	case PERIPH_ID_LCDC0:
		break;
	default:
		debug("lcdc id = %d iomux error!\n", lcd_id);
		break;
	}
}

static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
				     struct rk3399_pmugrf_regs *pmugrf,
				     enum periph_id spi_id, int cs)
{
	switch (spi_id) {
	case PERIPH_ID_SPI0:
		switch (cs) {
		case 0:
			rk_clrsetreg(&grf->gpio3a_iomux,
				     GRF_GPIO3A7_SEL_MASK,
				     GRF_SPI0NORCODEC_CSN0
				     << GRF_GPIO3A7_SEL_SHIFT);
			break;
		case 1:
			rk_clrsetreg(&grf->gpio3b_iomux,
				     GRF_GPIO3B0_SEL_MASK,
				     GRF_SPI0NORCODEC_CSN1
				     << GRF_GPIO3B0_SEL_SHIFT);
			break;
		default:
			goto err;
		}
		rk_clrsetreg(&grf->gpio3a_iomux,
			     GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
			     | GRF_GPIO3A6_SEL_SHIFT,
			     GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
			     | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
			     | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
		break;
	case PERIPH_ID_SPI1:
		if (cs != 0)
			goto err;
		rk_clrsetreg(&pmugrf->gpio1a_iomux,
			     PMUGRF_GPIO1A7_SEL_MASK,
			     PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
		rk_clrsetreg(&pmugrf->gpio1b_iomux,
			     PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
			     | PMUGRF_GPIO1B2_SEL_MASK,
			     PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
			     | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
			     | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
		break;
	case PERIPH_ID_SPI2:
		if (cs != 0)
			goto err;
		rk_clrsetreg(&grf->gpio2b_iomux,
			     GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
			     | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
			     GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
			     | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
			     | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
			     | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
		break;
	default:
		goto err;
	}

	return 0;
err:
	debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
	return -ENOENT;
}

static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
				       struct rk3399_pmugrf_regs *pmugrf,
				       int uart_id)
{
	switch (uart_id) {
	case PERIPH_ID_UART2:
		/* Using channel-C by default */
		rk_clrsetreg(&grf->gpio4c_iomux,
			     GRF_GPIO4C3_SEL_MASK,
			     GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
		rk_clrsetreg(&grf->gpio4c_iomux,
			     GRF_GPIO4C4_SEL_MASK,
			     GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
		break;
	case PERIPH_ID_UART0:
	case PERIPH_ID_UART1:
	case PERIPH_ID_UART3:
	case PERIPH_ID_UART4:
	default:
		debug("uart id = %d iomux error!\n", uart_id);
		break;
	}
}

static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
{
	switch (mmc_id) {
	case PERIPH_ID_EMMC:
		break;
	case PERIPH_ID_SDCARD:
		rk_clrsetreg(&grf->gpio4b_iomux,
			     GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
			     | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
			     | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
			     GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
			     | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
			     | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
			     | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
			     | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
			     | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
		break;
	default:
		debug("mmc id = %d iomux error!\n", mmc_id);
		break;
	}
}

static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
{
	struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);

	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
	switch (func) {
	case PERIPH_ID_PWM0:
	case PERIPH_ID_PWM1:
	case PERIPH_ID_PWM2:
	case PERIPH_ID_PWM3:
	case PERIPH_ID_PWM4:
		pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
		break;
	case PERIPH_ID_I2C0:
	case PERIPH_ID_I2C1:
	case PERIPH_ID_I2C2:
	case PERIPH_ID_I2C3:
	case PERIPH_ID_I2C4:
	case PERIPH_ID_I2C5:
		pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
		break;
	case PERIPH_ID_SPI0:
	case PERIPH_ID_SPI1:
	case PERIPH_ID_SPI2:
		pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
		break;
	case PERIPH_ID_UART0:
	case PERIPH_ID_UART1:
	case PERIPH_ID_UART2:
	case PERIPH_ID_UART3:
	case PERIPH_ID_UART4:
		pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
		break;
	case PERIPH_ID_LCDC0:
	case PERIPH_ID_LCDC1:
		pinctrl_rk3399_lcdc_config(priv->grf, func);
		break;
	case PERIPH_ID_SDMMC0:
	case PERIPH_ID_SDMMC1:
		pinctrl_rk3399_sdmmc_config(priv->grf, func);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
					struct udevice *periph)
{
	u32 cell[3];
	int ret;

	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
				   "interrupts", cell, ARRAY_SIZE(cell));
	if (ret < 0)
		return -EINVAL;

	switch (cell[1]) {
	case 68:
		return PERIPH_ID_SPI0;
	case 53:
		return PERIPH_ID_SPI1;
	case 52:
		return PERIPH_ID_SPI2;
	case 57:
		return PERIPH_ID_I2C0;
	case 59: /* Note strange order */
		return PERIPH_ID_I2C1;
	case 35:
		return PERIPH_ID_I2C2;
	case 34:
		return PERIPH_ID_I2C3;
	case 56:
		return PERIPH_ID_I2C4;
	case 38:
		return PERIPH_ID_I2C5;
	case 65:
		return PERIPH_ID_SDMMC1;
	}

	return -ENOENT;
}

static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
					   struct udevice *periph)
{
	int func;

	func = rk3399_pinctrl_get_periph_id(dev, periph);
	if (func < 0)
		return func;

	return rk3399_pinctrl_request(dev, func, 0);
}

static struct pinctrl_ops rk3399_pinctrl_ops = {
	.set_state_simple	= rk3399_pinctrl_set_state_simple,
	.request	= rk3399_pinctrl_request,
	.get_periph_id	= rk3399_pinctrl_get_periph_id,
};

static int rk3399_pinctrl_probe(struct udevice *dev)
{
	struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
	int ret = 0;

	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
	debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);

	return ret;
}

static const struct udevice_id rk3399_pinctrl_ids[] = {
	{ .compatible = "rockchip,rk3399-pinctrl" },
	{ }
};

U_BOOT_DRIVER(pinctrl_rk3399) = {
	.name		= "rockchip_rk3399_pinctrl",
	.id		= UCLASS_PINCTRL,
	.of_match	= rk3399_pinctrl_ids,
	.priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
	.ops		= &rk3399_pinctrl_ops,
	.bind		= dm_scan_fdt_dev,
	.probe		= rk3399_pinctrl_probe,
};
Commit	Line	Data
a2c08df3 KY	1	/*
	2	* (C) Copyright 2016 Rockchip Electronics Co., Ltd
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <errno.h>
	10	#include <syscon.h>
	11	#include <asm/io.h>
	12	#include <asm/arch/grf_rk3399.h>
	13	#include <asm/arch/hardware.h>
	14	#include <asm/arch/periph.h>
	15	#include <asm/arch/clock.h>
	16	#include <dm/pinctrl.h>
	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	struct rk3399_pinctrl_priv {
	21	struct rk3399_grf_regs *grf;
	22	struct rk3399_pmugrf_regs *pmugrf;
	23	};
	24
a2c08df3 KY	25	static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
	26	struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
	27	{
	28	switch (pwm_id) {
	29	case PERIPH_ID_PWM0:
	30	rk_clrsetreg(&grf->gpio4c_iomux,
	31	GRF_GPIO4C2_SEL_MASK,
	32	GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
	33	break;
	34	case PERIPH_ID_PWM1:
	35	rk_clrsetreg(&grf->gpio4c_iomux,
	36	GRF_GPIO4C6_SEL_MASK,
	37	GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
	38	break;
	39	case PERIPH_ID_PWM2:
	40	rk_clrsetreg(&pmugrf->gpio1c_iomux,
	41	PMUGRF_GPIO1C3_SEL_MASK,
	42	PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
	43	break;
	44	case PERIPH_ID_PWM3:
	45	if (readl(&pmugrf->soc_con0) & (1 << 5))
	46	rk_clrsetreg(&pmugrf->gpio1b_iomux,
	47	PMUGRF_GPIO1B6_SEL_MASK,
	48	PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
	49	else
	50	rk_clrsetreg(&pmugrf->gpio0a_iomux,
	51	PMUGRF_GPIO0A6_SEL_MASK,
	52	PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
	53	break;
	54	default:
	55	debug("pwm id = %d iomux error!\n", pwm_id);
	56	break;
	57	}
	58	}
	59
	60	static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
	61	struct rk3399_pmugrf_regs *pmugrf,
	62	int i2c_id)
	63	{
	64	switch (i2c_id) {
	65	case PERIPH_ID_I2C0:
	66	rk_clrsetreg(&pmugrf->gpio1b_iomux,
	67	PMUGRF_GPIO1B7_SEL_MASK,
	68	PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
	69	rk_clrsetreg(&pmugrf->gpio1c_iomux,
	70	PMUGRF_GPIO1C0_SEL_MASK,
	71	PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
	72	break;
	73	case PERIPH_ID_I2C1:
	74	case PERIPH_ID_I2C2:
	75	case PERIPH_ID_I2C3:
	76	case PERIPH_ID_I2C4:
	77	case PERIPH_ID_I2C5:
	78	default:
	79	debug("i2c id = %d iomux error!\n", i2c_id);
	80	break;
	81	}
	82	}
	83
	84	static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
	85	{
	86	switch (lcd_id) {
	87	case PERIPH_ID_LCDC0:
	88	break;
89	default:
90	debug("lcdc id = %d iomux error!\n", lcd_id);
91	break;
92	}
93	}
94
95	static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
96	struct rk3399_pmugrf_regs *pmugrf,
97	enum periph_id spi_id, int cs)
98	{
99	switch (spi_id) {
100	case PERIPH_ID_SPI0:
101	switch (cs) {
102	case 0:
103	rk_clrsetreg(&grf->gpio3a_iomux,
104	GRF_GPIO3A7_SEL_MASK,
105	GRF_SPI0NORCODEC_CSN0
106	<< GRF_GPIO3A7_SEL_SHIFT);
107	break;
108	case 1:
109	rk_clrsetreg(&grf->gpio3b_iomux,
110	GRF_GPIO3B0_SEL_MASK,
111	GRF_SPI0NORCODEC_CSN1
112	<< GRF_GPIO3B0_SEL_SHIFT);
113	break;
114	default:
115	goto err;
116	}
117	rk_clrsetreg(&grf->gpio3a_iomux,
118	GRF_GPIO3A4_SEL_MASK \| GRF_GPIO3A5_SEL_SHIFT
119	\| GRF_GPIO3A6_SEL_SHIFT,
120	GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
121	\| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
122	\| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
123	break;
124	case PERIPH_ID_SPI1:
125	if (cs != 0)
126	goto err;
127	rk_clrsetreg(&pmugrf->gpio1a_iomux,
128	PMUGRF_GPIO1A7_SEL_MASK,
129	PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
130	rk_clrsetreg(&pmugrf->gpio1b_iomux,
131	PMUGRF_GPIO1B0_SEL_MASK \| PMUGRF_GPIO1B1_SEL_MASK
132	\| PMUGRF_GPIO1B2_SEL_MASK,
133	PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
134	\| PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
135	\| PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
136	break;
137	case PERIPH_ID_SPI2:
138	if (cs != 0)
139	goto err;
140	rk_clrsetreg(&grf->gpio2b_iomux,
141	GRF_GPIO2B1_SEL_MASK \| GRF_GPIO2B2_SEL_MASK
142	\| GRF_GPIO2B3_SEL_MASK \| GRF_GPIO2B4_SEL_MASK,
143	GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
144	\| GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
145	\| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
146	\| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
147	break;
148	default:
149	goto err;
150	}
151
152	return 0;
153	err:
154	debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
155	return -ENOENT;
156	}
157
158	static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
159	struct rk3399_pmugrf_regs *pmugrf,
160	int uart_id)
161	{
162	switch (uart_id) {
163	case PERIPH_ID_UART2:
164	/* Using channel-C by default */
165	rk_clrsetreg(&grf->gpio4c_iomux,
166	GRF_GPIO4C3_SEL_MASK,
167	GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
168	rk_clrsetreg(&grf->gpio4c_iomux,
169	GRF_GPIO4C4_SEL_MASK,
170	GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
171	break;
172	case PERIPH_ID_UART0:
173	case PERIPH_ID_UART1:
174	case PERIPH_ID_UART3:
175	case PERIPH_ID_UART4:
176	default:
177	debug("uart id = %d iomux error!\n", uart_id);
178	break;
179	}
180	}
181
182	static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
183	{
184	switch (mmc_id) {
185	case PERIPH_ID_EMMC:
186	break;
187	case PERIPH_ID_SDCARD:
188	rk_clrsetreg(&grf->gpio4b_iomux,
189	GRF_GPIO4B0_SEL_MASK \| GRF_GPIO4B1_SEL_MASK
190	\| GRF_GPIO4B2_SEL_MASK \| GRF_GPIO4B3_SEL_MASK
191	\| GRF_GPIO4B4_SEL_MASK \| GRF_GPIO4B5_SEL_MASK,
192	GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
193	\| GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
194	\| GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
195	\| GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
196	\| GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
197	\| GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
198	break;
199	default:
200	debug("mmc id = %d iomux error!\n", mmc_id);
201	break;
202	}
203	}
204
205	static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
206	{
207	struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
208
209	debug("%s: func=%x, flags=%x\n", __func__, func, flags);
210	switch (func) {
211	case PERIPH_ID_PWM0:
212	case PERIPH_ID_PWM1:
213	case PERIPH_ID_PWM2:
214	case PERIPH_ID_PWM3:
215	case PERIPH_ID_PWM4:
216	pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
217	break;
218	case PERIPH_ID_I2C0:
219	case PERIPH_ID_I2C1:
220	case PERIPH_ID_I2C2:
221	case PERIPH_ID_I2C3:
222	case PERIPH_ID_I2C4:
223	case PERIPH_ID_I2C5:
224	pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
225	break;
226	case PERIPH_ID_SPI0:
227	case PERIPH_ID_SPI1:
228	case PERIPH_ID_SPI2:
229	pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
230	break;
231	case PERIPH_ID_UART0:
232	case PERIPH_ID_UART1:
233	case PERIPH_ID_UART2:
234	case PERIPH_ID_UART3:
235	case PERIPH_ID_UART4:
236	pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
237	break;
238	case PERIPH_ID_LCDC0:
239	case PERIPH_ID_LCDC1:
240	pinctrl_rk3399_lcdc_config(priv->grf, func);
241	break;
242	case PERIPH_ID_SDMMC0:
243	case PERIPH_ID_SDMMC1:
244	pinctrl_rk3399_sdmmc_config(priv->grf, func);
245	break;
246	default:
247	return -EINVAL;
248	}
249
250	return 0;
251	}
252
253	static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
254	struct udevice *periph)
255	{
256	u32 cell[3];
257	int ret;
258
e160f7d4	259	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
a2c08df3 KY	260	"interrupts", cell, ARRAY_SIZE(cell));
	261	if (ret < 0)
	262	return -EINVAL;
	263
	264	switch (cell[1]) {
	265	case 68:
	266	return PERIPH_ID_SPI0;
	267	case 53:
	268	return PERIPH_ID_SPI1;
	269	case 52:
	270	return PERIPH_ID_SPI2;
	271	case 57:
	272	return PERIPH_ID_I2C0;
	273	case 59: /* Note strange order */
	274	return PERIPH_ID_I2C1;
	275	case 35:
	276	return PERIPH_ID_I2C2;
	277	case 34:
	278	return PERIPH_ID_I2C3;
	279	case 56:
	280	return PERIPH_ID_I2C4;
	281	case 38:
	282	return PERIPH_ID_I2C5;
	283	case 65:
	284	return PERIPH_ID_SDMMC1;
	285	}
	286
	287	return -ENOENT;
	288	}
	289
	290	static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
	291	struct udevice *periph)
	292	{
	293	int func;
	294
	295	func = rk3399_pinctrl_get_periph_id(dev, periph);
	296	if (func < 0)
	297	return func;
	298
	299	return rk3399_pinctrl_request(dev, func, 0);
	300	}
	301
	302	static struct pinctrl_ops rk3399_pinctrl_ops = {
	303	.set_state_simple = rk3399_pinctrl_set_state_simple,
	304	.request = rk3399_pinctrl_request,
	305	.get_periph_id = rk3399_pinctrl_get_periph_id,
	306	};
	307
	308	static int rk3399_pinctrl_probe(struct udevice *dev)
	309	{
	310	struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
	311	int ret = 0;
	312
	313	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	314	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
	315	debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
	316
	317	return ret;
	318	}
	319
	320	static const struct udevice_id rk3399_pinctrl_ids[] = {
	321	{ .compatible = "rockchip,rk3399-pinctrl" },
	322	{ }
	323	};
324
325	U_BOOT_DRIVER(pinctrl_rk3399) = {
326	.name = "rockchip_rk3399_pinctrl",
327	.id = UCLASS_PINCTRL,
328	.of_match = rk3399_pinctrl_ids,
329	.priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
330	.ops = &rk3399_pinctrl_ops,
331	.bind = dm_scan_fdt_dev,
332	.probe = rk3399_pinctrl_probe,
333	};