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f8ea15f7 ML |
1 | /* |
2 | * (C) Copyright 2009 Faraday Technology | |
3 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
4 | * | |
5 | * Copyright (C) 2010 Andes Technology Corporation | |
6 | * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> | |
7 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
f8ea15f7 ML |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <asm/io.h> | |
d6150db2 | 14 | #include <faraday/ftpmu010.h> |
f8ea15f7 | 15 | |
caddb8e4 | 16 | /* OSCC: OSC Control Register */ |
f8ea15f7 ML |
17 | void ftpmu010_32768osc_enable(void) |
18 | { | |
caddb8e4 | 19 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; |
f8ea15f7 ML |
20 | unsigned int oscc; |
21 | ||
22 | /* enable the 32768Hz oscillator */ | |
23 | oscc = readl(&pmu->OSCC); | |
24 | oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); | |
25 | writel(oscc, &pmu->OSCC); | |
26 | ||
27 | /* wait until ready */ | |
28 | while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) | |
29 | ; | |
30 | ||
31 | /* select 32768Hz oscillator */ | |
32 | oscc = readl(&pmu->OSCC); | |
33 | oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; | |
34 | writel(oscc, &pmu->OSCC); | |
35 | } | |
36 | ||
caddb8e4 ML |
37 | /* MFPSR: Multi-Function Port Setting Register */ |
38 | void ftpmu010_mfpsr_select_dev(unsigned int dev) | |
39 | { | |
40 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; | |
41 | unsigned int mfpsr; | |
42 | ||
43 | mfpsr = readl(&pmu->MFPSR); | |
44 | mfpsr |= dev; | |
45 | writel(mfpsr, &pmu->MFPSR); | |
46 | } | |
47 | ||
48 | void ftpmu010_mfpsr_diselect_dev(unsigned int dev) | |
49 | { | |
50 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; | |
51 | unsigned int mfpsr; | |
52 | ||
53 | mfpsr = readl(&pmu->MFPSR); | |
54 | mfpsr &= ~dev; | |
55 | writel(mfpsr, &pmu->MFPSR); | |
56 | } | |
57 | ||
58 | /* PDLLCR0: PLL/DLL Control Register 0 */ | |
f8ea15f7 ML |
59 | void ftpmu010_dlldis_disable(void) |
60 | { | |
caddb8e4 | 61 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; |
f8ea15f7 ML |
62 | unsigned int pdllcr0; |
63 | ||
64 | pdllcr0 = readl(&pmu->PDLLCR0); | |
65 | pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS; | |
66 | writel(pdllcr0, &pmu->PDLLCR0); | |
67 | } | |
68 | ||
69 | void ftpmu010_sdram_clk_disable(unsigned int cr0) | |
70 | { | |
caddb8e4 | 71 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; |
f8ea15f7 ML |
72 | unsigned int pdllcr0; |
73 | ||
74 | pdllcr0 = readl(&pmu->PDLLCR0); | |
75 | pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); | |
76 | writel(pdllcr0, &pmu->PDLLCR0); | |
77 | } | |
caddb8e4 ML |
78 | |
79 | /* SDRAMHTC: SDRAM Signal Hold Time Control */ | |
80 | void ftpmu010_sdramhtc_set(unsigned int val) | |
81 | { | |
82 | static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; | |
83 | unsigned int sdramhtc; | |
84 | ||
85 | sdramhtc = readl(&pmu->SDRAMHTC); | |
86 | sdramhtc |= val; | |
87 | writel(sdramhtc, &pmu->SDRAMHTC); | |
88 | } |