[people/ms/u-boot.git] / drivers / ps2ser.c

/***********************************************************************
 *
 * (C) Copyright 2004
 * DENX Software Engineering
 * Wolfgang Denk, wd@denx.de
 * All rights reserved.
 *
 * Simple 16550A serial driver
 *
 * Originally from linux source (drivers/char/ps2ser.c)
 *
 * Used by the PS/2 multiplexer driver (ps2mult.c)
 *
 ***********************************************************************/

#include <common.h>

#ifdef CONFIG_PS2SERIAL

#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx)
#include <ns16550.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* #define	DEBUG */

#define PS2SER_BAUD	57600

#ifdef CONFIG_MPC5xxx
#if CONFIG_PS2SERIAL == 1
#define PSC_BASE MPC5XXX_PSC1
#elif CONFIG_PS2SERIAL == 2
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PS2SERIAL == 3
#define PSC_BASE MPC5XXX_PSC3
#elif defined(CONFIG_MGT5100)
#error CONFIG_PS2SERIAL must be in 1, 2 or 3
#elif CONFIG_PS2SERIAL == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PS2SERIAL == 5
#define PSC_BASE MPC5XXX_PSC5
#elif CONFIG_PS2SERIAL == 6
#define PSC_BASE MPC5XXX_PSC6
#else
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif

#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)

#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CFG_CCSRBAR+0x4500)
#elif CONFIG_PS2SERIAL == 2
#define COM_BASE (CFG_CCSRBAR+0x4600)
#else
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif

#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */

static int	ps2ser_getc_hw(void);
static void	ps2ser_interrupt(void *dev_id);

extern struct	serial_state rs_table[]; /* in serial.c */
#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
static struct	serial_state *state;
#endif

static u_char	ps2buf[PS2BUF_SIZE];
static atomic_t	ps2buf_cnt;
static int	ps2buf_in_idx;
static int	ps2buf_out_idx;

#ifdef CONFIG_MPC5xxx
int ps2ser_init(void)
{
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
	unsigned long baseclk;
	int div;

	/* reset PSC */
	psc->command = PSC_SEL_MODE_REG_1;

	/* select clock sources */
#if defined(CONFIG_MGT5100)
	psc->psc_clock_select = 0xdd00;
	baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
	psc->psc_clock_select = 0;
	baseclk = (gd->ipb_clk + 16) / 32;
#endif

	/* switch to UART mode */
	psc->sicr = 0;

	/* configure parity, bit length and so on */
#if defined(CONFIG_MGT5100)
	psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
#elif defined(CONFIG_MPC5200)
	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
#endif
	psc->mode = PSC_MODE_ONE_STOP;

	/* set up UART divisor */
	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
	psc->ctur = (div >> 8) & 0xff;
	psc->ctlr = div & 0xff;

	/* disable all interrupts */
	psc->psc_imr = 0;

	/* reset and enable Rx/Tx */
	psc->command = PSC_RST_RX;
	psc->command = PSC_RST_TX;
	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;

	return (0);
}

#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
int ps2ser_init(void)
{
	NS16550_t com_port = (NS16550_t)COM_BASE;

	com_port->ier = 0x00;
	com_port->lcr = LCR_BKSE | LCR_8N1;
	com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
	com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
	com_port->lcr = LCR_8N1;
	com_port->mcr = (MCR_DTR | MCR_RTS);
	com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);

	return (0);
}

#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */

static inline unsigned int ps2ser_in(int offset)
{
	return readb((unsigned long) state->iomem_base + offset);
}

static inline void ps2ser_out(int offset, int value)
{
	writeb(value, (unsigned long) state->iomem_base + offset);
}

int ps2ser_init(void)
{
	int quot;
	unsigned cval;

	state = rs_table + CONFIG_PS2SERIAL;

	quot = state->baud_base / PS2SER_BAUD;
	cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */

	  /* Set speed, enable interrupts, enable FIFO
	   */
	ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
	ps2ser_out(UART_DLL, quot & 0xff);
	ps2ser_out(UART_DLM, quot >> 8);
	ps2ser_out(UART_LCR, cval);
	ps2ser_out(UART_IER, UART_IER_RDI);
	ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
	ps2ser_out(UART_FCR,
	    UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);

	/* If we read 0xff from the LSR, there is no UART here
	 */
	if (ps2ser_in(UART_LSR) == 0xff) {
		printf ("ps2ser.c: no UART found\n");
		return -1;
	}

	irq_install_handler(state->irq, ps2ser_interrupt, NULL);

	return 0;
}
#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */

void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
#ifdef DEBUG
	printf(">>>> 0x%02x\n", chr);
#endif

#ifdef CONFIG_MPC5xxx
	while (!(psc->psc_status & PSC_SR_TXRDY));

	psc->psc_buffer_8 = chr;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	while ((com_port->lsr & LSR_THRE) == 0);
	com_port->thr = chr;
#else
	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));

	ps2ser_out(UART_TX, chr);
#endif
}

static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
	int res = -1;

#ifdef CONFIG_MPC5xxx
	if (psc->psc_status & PSC_SR_RXRDY) {
		res = (psc->psc_buffer_8);
	}
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	if (com_port->lsr & LSR_DR) {
		res = com_port->rbr;
	}
#else
	if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
		res = (ps2ser_in(UART_RX));
	}
#endif

	return res;
}

int ps2ser_getc(void)
{
	volatile int chr;
	int flags;

#ifdef DEBUG
	printf("<< ");
#endif

	flags = disable_interrupts();

	do {
		if (atomic_read(&ps2buf_cnt) != 0) {
			chr = ps2buf[ps2buf_out_idx++];
			ps2buf_out_idx &= (PS2BUF_SIZE - 1);
			atomic_dec(&ps2buf_cnt);
		} else {
			chr = ps2ser_getc_hw();
		}
	}
	while (chr < 0);

	if (flags) enable_interrupts();

#ifdef DEBUG
	printf("0x%02x\n", chr);
#endif

	return chr;
}

int ps2ser_check(void)
{
	int flags;

	flags = disable_interrupts();
	ps2ser_interrupt(NULL);
	if (flags) enable_interrupts();

	return atomic_read(&ps2buf_cnt);
}

static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
	int chr;
	int status;

	do {
		chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
		status = psc->psc_status;
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
		status = com_port->lsr;
#else
		status = ps2ser_in(UART_IIR);
#endif
		if (chr < 0) continue;

		if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
			ps2buf[ps2buf_in_idx++] = chr;
			ps2buf_in_idx &= (PS2BUF_SIZE - 1);
			atomic_inc(&ps2buf_cnt);
		} else {
			printf ("ps2ser.c: buffer overflow\n");
		}
#ifdef CONFIG_MPC5xxx
	} while (status & PSC_SR_RXRDY);
#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
	} while (status & LSR_DR);
#else
	} while (status & UART_IIR_RDI);
#endif

	if (atomic_read(&ps2buf_cnt)) {
		ps2mult_callback(atomic_read(&ps2buf_cnt));
	}
}

#endif /* CONFIG_PS2SERIAL */
Commit	Line	Data
1c43771b WD	1	/***********************************************************************
	2	*
	3	* (C) Copyright 2004
	4	* DENX Software Engineering
	5	* Wolfgang Denk, wd@denx.de
	6	* All rights reserved.
	7	*
	8	* Simple 16550A serial driver
	9	*
	10	* Originally from linux source (drivers/char/ps2ser.c)
	11	*
	12	* Used by the PS/2 multiplexer driver (ps2mult.c)
	13	*
	14	***********************************************************************/
	15
	16	#include <common.h>
	17
	18	#ifdef CONFIG_PS2SERIAL
	19
	20	#include <asm/io.h>
	21	#include <asm/atomic.h>
	22	#include <ps2mult.h>
966083e9	23	#if defined(CFG_NS16550) \|\| defined(CONFIG_MPC85xx)
bc8bb6d4 WD	24	#include <ns16550.h>
bc8bb6d4 WD	25	#endif
1c43771b	26
d87080b7 WD	27	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	28
1c43771b WD	29	/* #define DEBUG */
	30
	31	#define PS2SER_BAUD 57600
	32
7e6bf358 WD	33	#ifdef CONFIG_MPC5xxx
	34	#if CONFIG_PS2SERIAL == 1
	35	#define PSC_BASE MPC5XXX_PSC1
	36	#elif CONFIG_PS2SERIAL == 2
	37	#define PSC_BASE MPC5XXX_PSC2
	38	#elif CONFIG_PS2SERIAL == 3
	39	#define PSC_BASE MPC5XXX_PSC3
	40	#elif defined(CONFIG_MGT5100)
	41	#error CONFIG_PS2SERIAL must be in 1, 2 or 3
	42	#elif CONFIG_PS2SERIAL == 4
	43	#define PSC_BASE MPC5XXX_PSC4
	44	#elif CONFIG_PS2SERIAL == 5
	45	#define PSC_BASE MPC5XXX_PSC5
	46	#elif CONFIG_PS2SERIAL == 6
	47	#define PSC_BASE MPC5XXX_PSC6
	48	#else
	49	#error CONFIG_PS2SERIAL must be in 1 ... 6
	50	#endif
bc8bb6d4	51
bd3143f0	52	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	53
	54	#if CONFIG_PS2SERIAL == 1
	55	#define COM_BASE (CFG_CCSRBAR+0x4500)
	56	#elif CONFIG_PS2SERIAL == 2
	57	#define COM_BASE (CFG_CCSRBAR+0x4600)
	58	#else
	59	#error CONFIG_PS2SERIAL must be in 1 ... 2
	60	#endif
	61
bd3143f0	62	#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
7e6bf358	63
1c43771b WD	64	static int ps2ser_getc_hw(void);
	65	static void ps2ser_interrupt(void *dev_id);
	66
	67	extern struct serial_state rs_table[]; /* in serial.c */
bd3143f0	68	#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555)
ef978730	69	static struct serial_state *state;
7e6bf358	70	#endif
1c43771b WD	71
	72	static u_char ps2buf[PS2BUF_SIZE];
	73	static atomic_t ps2buf_cnt;
	74	static int ps2buf_in_idx;
	75	static int ps2buf_out_idx;
	76
7e6bf358 WD	77	#ifdef CONFIG_MPC5xxx
	78	int ps2ser_init(void)
	79	{
7e6bf358 WD	80	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
	81	unsigned long baseclk;
	82	int div;
	83
	84	/* reset PSC */
	85	psc->command = PSC_SEL_MODE_REG_1;
	86
	87	/* select clock sources */
	88	#if defined(CONFIG_MGT5100)
	89	psc->psc_clock_select = 0xdd00;
	90	baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
	91	#elif defined(CONFIG_MPC5200)
	92	psc->psc_clock_select = 0;
	93	baseclk = (gd->ipb_clk + 16) / 32;
	94	#endif
	95
	96	/* switch to UART mode */
	97	psc->sicr = 0;
	98
	99	/* configure parity, bit length and so on */
	100	#if defined(CONFIG_MGT5100)
	101	psc->mode = PSC_MODE_ERR \| PSC_MODE_8_BITS \| PSC_MODE_PARNONE;
	102	#elif defined(CONFIG_MPC5200)
	103	psc->mode = PSC_MODE_8_BITS \| PSC_MODE_PARNONE;
	104	#endif
	105	psc->mode = PSC_MODE_ONE_STOP;
	106
	107	/* set up UART divisor */
	108	div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
	109	psc->ctur = (div >> 8) & 0xff;
	110	psc->ctlr = div & 0xff;
	111
	112	/* disable all interrupts */
	113	psc->psc_imr = 0;
	114
	115	/* reset and enable Rx/Tx */
	116	psc->command = PSC_RST_RX;
	117	psc->command = PSC_RST_TX;
	118	psc->command = PSC_RX_ENABLE \| PSC_TX_ENABLE;
	119
	120	return (0);
	121	}
	122
bd3143f0	123	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	124	int ps2ser_init(void)
	125	{
	126	NS16550_t com_port = (NS16550_t)COM_BASE;
	127
	128	com_port->ier = 0x00;
	129	com_port->lcr = LCR_BKSE \| LCR_8N1;
	130	com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
	131	com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
	132	com_port->lcr = LCR_8N1;
	133	com_port->mcr = (MCR_DTR \| MCR_RTS);
	134	com_port->fcr = (FCR_FIFO_EN \| FCR_RXSR \| FCR_TXSR);
	135
	136	return (0);
	137	}
	138
bd3143f0	139	#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */
1c43771b WD	140
	141	static inline unsigned int ps2ser_in(int offset)
	142	{
	143	return readb((unsigned long) state->iomem_base + offset);
	144	}
	145
	146	static inline void ps2ser_out(int offset, int value)
	147	{
	148	writeb(value, (unsigned long) state->iomem_base + offset);
	149	}
	150
	151	int ps2ser_init(void)
	152	{
ef978730 WD	153	int quot;
	154	unsigned cval;
	155
	156	state = rs_table + CONFIG_PS2SERIAL;
	157
	158	quot = state->baud_base / PS2SER_BAUD;
	159	cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
1c43771b WD	160
	161	/* Set speed, enable interrupts, enable FIFO
	162	*/
	163	ps2ser_out(UART_LCR, cval \| UART_LCR_DLAB);
	164	ps2ser_out(UART_DLL, quot & 0xff);
	165	ps2ser_out(UART_DLM, quot >> 8);
	166	ps2ser_out(UART_LCR, cval);
	167	ps2ser_out(UART_IER, UART_IER_RDI);
	168	ps2ser_out(UART_MCR, UART_MCR_OUT2 \| UART_MCR_DTR \| UART_MCR_RTS);
	169	ps2ser_out(UART_FCR,
	170	UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT);
	171
	172	/* If we read 0xff from the LSR, there is no UART here
	173	*/
	174	if (ps2ser_in(UART_LSR) == 0xff) {
	175	printf ("ps2ser.c: no UART found\n");
	176	return -1;
	177	}
	178
	179	irq_install_handler(state->irq, ps2ser_interrupt, NULL);
	180
	181	return 0;
	182	}
bd3143f0	183	#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */
1c43771b WD	184
	185	void ps2ser_putc(int chr)
	186	{
7e6bf358 WD	187	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	188	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
bd3143f0	189	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	190	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	191	#endif
1c43771b WD	192	#ifdef DEBUG
	193	printf(">>>> 0x%02x\n", chr);
	194	#endif
	195
7e6bf358 WD	196	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	197	while (!(psc->psc_status & PSC_SR_TXRDY));
efe2a4d5	198
7e6bf358	199	psc->psc_buffer_8 = chr;
bd3143f0	200	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	201	while ((com_port->lsr & LSR_THRE) == 0);
bc8bb6d4 WD	202	com_port->thr = chr;
7e6bf358	203	#else
1c43771b WD	204	while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
	205
	206	ps2ser_out(UART_TX, chr);
7e6bf358	207	#endif
1c43771b WD	208	}
	209
	210	static int ps2ser_getc_hw(void)
	211	{
7e6bf358 WD	212	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	213	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
bd3143f0	214	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	215	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	216	#endif
1c43771b WD	217	int res = -1;
1c43771b WD	218
7e6bf358 WD	219	#ifdef CONFIG_MPC5xxx
	220	if (psc->psc_status & PSC_SR_RXRDY) {
	221	res = (psc->psc_buffer_8);
	222	}
bd3143f0	223	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4 WD	224	if (com_port->lsr & LSR_DR) {
	225	res = com_port->rbr;
	226	}
7e6bf358	227	#else
1c43771b WD	228	if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
	229	res = (ps2ser_in(UART_RX));
	230	}
7e6bf358	231	#endif
1c43771b WD	232
	233	return res;
	234	}
	235
	236	int ps2ser_getc(void)
	237	{
	238	volatile int chr;
	239	int flags;
	240
	241	#ifdef DEBUG
	242	printf("<< ");
	243	#endif
	244
	245	flags = disable_interrupts();
	246
	247	do {
	248	if (atomic_read(&ps2buf_cnt) != 0) {
	249	chr = ps2buf[ps2buf_out_idx++];
	250	ps2buf_out_idx &= (PS2BUF_SIZE - 1);
	251	atomic_dec(&ps2buf_cnt);
	252	} else {
	253	chr = ps2ser_getc_hw();
	254	}
	255	}
	256	while (chr < 0);
	257
	258	if (flags) enable_interrupts();
	259
	260	#ifdef DEBUG
	261	printf("0x%02x\n", chr);
	262	#endif
	263
	264	return chr;
	265	}
	266
	267	int ps2ser_check(void)
	268	{
	269	int flags;
	270
	271	flags = disable_interrupts();
	272	ps2ser_interrupt(NULL);
	273	if (flags) enable_interrupts();
	274
	275	return atomic_read(&ps2buf_cnt);
	276	}
	277
	278	static void ps2ser_interrupt(void *dev_id)
	279	{
7e6bf358 WD	280	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	281	volatile struct mpc5xxx_psc psc = (struct mpc5xxx_psc )PSC_BASE;
bd3143f0	282	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	283	NS16550_t com_port = (NS16550_t)COM_BASE;
7e6bf358	284	#endif
1c43771b	285	int chr;
7e6bf358	286	int status;
1c43771b WD	287
	288	do {
	289	chr = ps2ser_getc_hw();
7e6bf358 WD	290	#ifdef CONFIG_MPC5xxx
7e6bf358 WD	291	status = psc->psc_status;
bd3143f0	292	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	293	status = com_port->lsr;
7e6bf358 WD	294	#else
	295	status = ps2ser_in(UART_IIR);
	296	#endif
1c43771b WD	297	if (chr < 0) continue;
	298
	299	if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
	300	ps2buf[ps2buf_in_idx++] = chr;
	301	ps2buf_in_idx &= (PS2BUF_SIZE - 1);
	302	atomic_inc(&ps2buf_cnt);
	303	} else {
	304	printf ("ps2ser.c: buffer overflow\n");
	305	}
7e6bf358	306	#ifdef CONFIG_MPC5xxx
efe2a4d5	307	} while (status & PSC_SR_RXRDY);
bd3143f0	308	#elif defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| defined(CONFIG_MPC8555)
bc8bb6d4	309	} while (status & LSR_DR);
7e6bf358 WD	310	#else
	311	} while (status & UART_IIR_RDI);
	312	#endif
1c43771b WD	313
	314	if (atomic_read(&ps2buf_cnt)) {
	315	ps2mult_callback(atomic_read(&ps2buf_cnt));
	316	}
	317	}
	318
	319	#endif /* CONFIG_PS2SERIAL */