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1c43771b WD |
1 | /*********************************************************************** |
2 | * | |
3 | * (C) Copyright 2004 | |
4 | * DENX Software Engineering | |
5 | * Wolfgang Denk, wd@denx.de | |
6 | * All rights reserved. | |
7 | * | |
8 | * Simple 16550A serial driver | |
9 | * | |
10 | * Originally from linux source (drivers/char/ps2ser.c) | |
11 | * | |
12 | * Used by the PS/2 multiplexer driver (ps2mult.c) | |
13 | * | |
14 | ***********************************************************************/ | |
15 | ||
16 | #include <common.h> | |
17 | ||
18 | #ifdef CONFIG_PS2SERIAL | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/atomic.h> | |
22 | #include <ps2mult.h> | |
23 | ||
24 | /* #define DEBUG */ | |
25 | ||
26 | #define PS2SER_BAUD 57600 | |
27 | ||
7e6bf358 WD |
28 | #ifdef CONFIG_MPC5xxx |
29 | #if CONFIG_PS2SERIAL == 1 | |
30 | #define PSC_BASE MPC5XXX_PSC1 | |
31 | #elif CONFIG_PS2SERIAL == 2 | |
32 | #define PSC_BASE MPC5XXX_PSC2 | |
33 | #elif CONFIG_PS2SERIAL == 3 | |
34 | #define PSC_BASE MPC5XXX_PSC3 | |
35 | #elif defined(CONFIG_MGT5100) | |
36 | #error CONFIG_PS2SERIAL must be in 1, 2 or 3 | |
37 | #elif CONFIG_PS2SERIAL == 4 | |
38 | #define PSC_BASE MPC5XXX_PSC4 | |
39 | #elif CONFIG_PS2SERIAL == 5 | |
40 | #define PSC_BASE MPC5XXX_PSC5 | |
41 | #elif CONFIG_PS2SERIAL == 6 | |
42 | #define PSC_BASE MPC5XXX_PSC6 | |
43 | #else | |
44 | #error CONFIG_PS2SERIAL must be in 1 ... 6 | |
45 | #endif | |
46 | #endif /* CONFIG_MPC5xxx */ | |
47 | ||
1c43771b WD |
48 | static int ps2ser_getc_hw(void); |
49 | static void ps2ser_interrupt(void *dev_id); | |
50 | ||
51 | extern struct serial_state rs_table[]; /* in serial.c */ | |
7e6bf358 | 52 | #ifndef CONFIG_MPC5xxx |
ef978730 | 53 | static struct serial_state *state; |
7e6bf358 | 54 | #endif |
1c43771b WD |
55 | |
56 | static u_char ps2buf[PS2BUF_SIZE]; | |
57 | static atomic_t ps2buf_cnt; | |
58 | static int ps2buf_in_idx; | |
59 | static int ps2buf_out_idx; | |
60 | ||
7e6bf358 WD |
61 | #ifdef CONFIG_MPC5xxx |
62 | int ps2ser_init(void) | |
63 | { | |
64 | DECLARE_GLOBAL_DATA_PTR; | |
65 | ||
66 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
67 | unsigned long baseclk; | |
68 | int div; | |
69 | ||
70 | /* reset PSC */ | |
71 | psc->command = PSC_SEL_MODE_REG_1; | |
72 | ||
73 | /* select clock sources */ | |
74 | #if defined(CONFIG_MGT5100) | |
75 | psc->psc_clock_select = 0xdd00; | |
76 | baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; | |
77 | #elif defined(CONFIG_MPC5200) | |
78 | psc->psc_clock_select = 0; | |
79 | baseclk = (gd->ipb_clk + 16) / 32; | |
80 | #endif | |
81 | ||
82 | /* switch to UART mode */ | |
83 | psc->sicr = 0; | |
84 | ||
85 | /* configure parity, bit length and so on */ | |
86 | #if defined(CONFIG_MGT5100) | |
87 | psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; | |
88 | #elif defined(CONFIG_MPC5200) | |
89 | psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; | |
90 | #endif | |
91 | psc->mode = PSC_MODE_ONE_STOP; | |
92 | ||
93 | /* set up UART divisor */ | |
94 | div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD; | |
95 | psc->ctur = (div >> 8) & 0xff; | |
96 | psc->ctlr = div & 0xff; | |
97 | ||
98 | /* disable all interrupts */ | |
99 | psc->psc_imr = 0; | |
100 | ||
101 | /* reset and enable Rx/Tx */ | |
102 | psc->command = PSC_RST_RX; | |
103 | psc->command = PSC_RST_TX; | |
104 | psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; | |
105 | ||
106 | return (0); | |
107 | } | |
108 | ||
109 | #else /* !CONFIG_MPC5xxx */ | |
1c43771b WD |
110 | |
111 | static inline unsigned int ps2ser_in(int offset) | |
112 | { | |
113 | return readb((unsigned long) state->iomem_base + offset); | |
114 | } | |
115 | ||
116 | static inline void ps2ser_out(int offset, int value) | |
117 | { | |
118 | writeb(value, (unsigned long) state->iomem_base + offset); | |
119 | } | |
120 | ||
121 | int ps2ser_init(void) | |
122 | { | |
ef978730 WD |
123 | int quot; |
124 | unsigned cval; | |
125 | ||
126 | state = rs_table + CONFIG_PS2SERIAL; | |
127 | ||
128 | quot = state->baud_base / PS2SER_BAUD; | |
129 | cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */ | |
1c43771b WD |
130 | |
131 | /* Set speed, enable interrupts, enable FIFO | |
132 | */ | |
133 | ps2ser_out(UART_LCR, cval | UART_LCR_DLAB); | |
134 | ps2ser_out(UART_DLL, quot & 0xff); | |
135 | ps2ser_out(UART_DLM, quot >> 8); | |
136 | ps2ser_out(UART_LCR, cval); | |
137 | ps2ser_out(UART_IER, UART_IER_RDI); | |
138 | ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS); | |
139 | ps2ser_out(UART_FCR, | |
140 | UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
141 | ||
142 | /* If we read 0xff from the LSR, there is no UART here | |
143 | */ | |
144 | if (ps2ser_in(UART_LSR) == 0xff) { | |
145 | printf ("ps2ser.c: no UART found\n"); | |
146 | return -1; | |
147 | } | |
148 | ||
149 | irq_install_handler(state->irq, ps2ser_interrupt, NULL); | |
150 | ||
151 | return 0; | |
152 | } | |
7e6bf358 | 153 | #endif /* CONFIG_MPC5xxx */ |
1c43771b WD |
154 | |
155 | void ps2ser_putc(int chr) | |
156 | { | |
7e6bf358 WD |
157 | #ifdef CONFIG_MPC5xxx |
158 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
159 | #endif | |
1c43771b WD |
160 | #ifdef DEBUG |
161 | printf(">>>> 0x%02x\n", chr); | |
162 | #endif | |
163 | ||
7e6bf358 WD |
164 | #ifdef CONFIG_MPC5xxx |
165 | while (!(psc->psc_status & PSC_SR_TXRDY)); | |
efe2a4d5 | 166 | |
7e6bf358 WD |
167 | psc->psc_buffer_8 = chr; |
168 | #else | |
1c43771b WD |
169 | while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE)); |
170 | ||
171 | ps2ser_out(UART_TX, chr); | |
7e6bf358 | 172 | #endif |
1c43771b WD |
173 | } |
174 | ||
175 | static int ps2ser_getc_hw(void) | |
176 | { | |
7e6bf358 WD |
177 | #ifdef CONFIG_MPC5xxx |
178 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
179 | #endif | |
1c43771b WD |
180 | int res = -1; |
181 | ||
7e6bf358 WD |
182 | #ifdef CONFIG_MPC5xxx |
183 | if (psc->psc_status & PSC_SR_RXRDY) { | |
184 | res = (psc->psc_buffer_8); | |
185 | } | |
186 | #else | |
1c43771b WD |
187 | if (ps2ser_in(UART_LSR) & UART_LSR_DR) { |
188 | res = (ps2ser_in(UART_RX)); | |
189 | } | |
7e6bf358 | 190 | #endif |
1c43771b WD |
191 | |
192 | return res; | |
193 | } | |
194 | ||
195 | int ps2ser_getc(void) | |
196 | { | |
197 | volatile int chr; | |
198 | int flags; | |
199 | ||
200 | #ifdef DEBUG | |
201 | printf("<< "); | |
202 | #endif | |
203 | ||
204 | flags = disable_interrupts(); | |
205 | ||
206 | do { | |
207 | if (atomic_read(&ps2buf_cnt) != 0) { | |
208 | chr = ps2buf[ps2buf_out_idx++]; | |
209 | ps2buf_out_idx &= (PS2BUF_SIZE - 1); | |
210 | atomic_dec(&ps2buf_cnt); | |
211 | } else { | |
212 | chr = ps2ser_getc_hw(); | |
213 | } | |
214 | } | |
215 | while (chr < 0); | |
216 | ||
217 | if (flags) enable_interrupts(); | |
218 | ||
219 | #ifdef DEBUG | |
220 | printf("0x%02x\n", chr); | |
221 | #endif | |
222 | ||
223 | return chr; | |
224 | } | |
225 | ||
226 | int ps2ser_check(void) | |
227 | { | |
228 | int flags; | |
229 | ||
230 | flags = disable_interrupts(); | |
231 | ps2ser_interrupt(NULL); | |
232 | if (flags) enable_interrupts(); | |
233 | ||
234 | return atomic_read(&ps2buf_cnt); | |
235 | } | |
236 | ||
237 | static void ps2ser_interrupt(void *dev_id) | |
238 | { | |
7e6bf358 WD |
239 | #ifdef CONFIG_MPC5xxx |
240 | volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; | |
241 | #endif | |
1c43771b | 242 | int chr; |
7e6bf358 | 243 | int status; |
1c43771b WD |
244 | |
245 | do { | |
246 | chr = ps2ser_getc_hw(); | |
7e6bf358 WD |
247 | #ifdef CONFIG_MPC5xxx |
248 | status = psc->psc_status; | |
249 | #else | |
250 | status = ps2ser_in(UART_IIR); | |
251 | #endif | |
1c43771b WD |
252 | if (chr < 0) continue; |
253 | ||
254 | if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) { | |
255 | ps2buf[ps2buf_in_idx++] = chr; | |
256 | ps2buf_in_idx &= (PS2BUF_SIZE - 1); | |
257 | atomic_inc(&ps2buf_cnt); | |
258 | } else { | |
259 | printf ("ps2ser.c: buffer overflow\n"); | |
260 | } | |
7e6bf358 | 261 | #ifdef CONFIG_MPC5xxx |
efe2a4d5 | 262 | } while (status & PSC_SR_RXRDY); |
7e6bf358 WD |
263 | #else |
264 | } while (status & UART_IIR_RDI); | |
265 | #endif | |
1c43771b WD |
266 | |
267 | if (atomic_read(&ps2buf_cnt)) { | |
268 | ps2mult_callback(atomic_read(&ps2buf_cnt)); | |
269 | } | |
270 | } | |
271 | ||
272 | #endif /* CONFIG_PS2SERIAL */ |