[thirdparty/kernel/linux.git] / drivers / pwm / pwm-lpc32xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

struct lpc32xx_pwm_chip {
	struct clk *clk;
	void __iomem *base;
};

#define PWM_ENABLE	BIT(31)
#define PWM_PIN_LEVEL	BIT(30)

static inline struct lpc32xx_pwm_chip *to_lpc32xx_pwm_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			      int duty_ns, int period_ns)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	unsigned long long c;
	int period_cycles, duty_cycles;
	u32 val;
	c = clk_get_rate(lpc32xx->clk);

	/* The highest acceptable divisor is 256, which is represented by 0 */
	period_cycles = div64_u64(c * period_ns,
			       (unsigned long long)NSEC_PER_SEC * 256);
	if (!period_cycles || period_cycles > 256)
		return -ERANGE;
	if (period_cycles == 256)
		period_cycles = 0;

	/* Compute 256 x #duty/period value and care for corner cases */
	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
				period_ns);
	if (!duty_cycles)
		duty_cycles = 1;
	if (duty_cycles > 255)
		duty_cycles = 255;

	val = readl(lpc32xx->base);
	val &= ~0xFFFF;
	val |= (period_cycles << 8) | duty_cycles;
	writel(val, lpc32xx->base);

	return 0;
}

static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;
	int ret;

	ret = clk_prepare_enable(lpc32xx->clk);
	if (ret)
		return ret;

	val = readl(lpc32xx->base);
	val |= PWM_ENABLE;
	writel(val, lpc32xx->base);

	return 0;
}

static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	u32 val;

	val = readl(lpc32xx->base);
	val &= ~PWM_ENABLE;
	writel(val, lpc32xx->base);

	clk_disable_unprepare(lpc32xx->clk);
}

static int lpc32xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	int err;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (pwm->state.enabled)
			lpc32xx_pwm_disable(chip, pwm);

		return 0;
	}

	err = lpc32xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!pwm->state.enabled)
		err = lpc32xx_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops lpc32xx_pwm_ops = {
	.apply = lpc32xx_pwm_apply,
};

static int lpc32xx_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct lpc32xx_pwm_chip *lpc32xx;
	int ret;
	u32 val;

	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*lpc32xx));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	lpc32xx = to_lpc32xx_pwm_chip(chip);

	lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(lpc32xx->base))
		return PTR_ERR(lpc32xx->base);

	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(lpc32xx->clk))
		return PTR_ERR(lpc32xx->clk);

	chip->ops = &lpc32xx_pwm_ops;

	/* If PWM is disabled, configure the output to the default value */
	val = readl(lpc32xx->base);
	val &= ~PWM_PIN_LEVEL;
	writel(val, lpc32xx->base);

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
	{ .compatible = "nxp,lpc3220-pwm", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);

static struct platform_driver lpc32xx_pwm_driver = {
	.driver = {
		.name = "lpc32xx-pwm",
		.of_match_table = lpc32xx_pwm_dt_ids,
	},
	.probe = lpc32xx_pwm_probe,
};
module_platform_driver(lpc32xx_pwm_driver);

MODULE_ALIAS("platform:lpc32xx-pwm");
MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
MODULE_DESCRIPTION("LPC32XX PWM Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a10e763b	1	// SPDX-License-Identifier: GPL-2.0-only
2132fa8d APS	2	/*
2132fa8d APS	3	* Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2132fa8d APS	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/err.h>
	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/pwm.h>
	15	#include <linux/slab.h>
	16
	17	struct lpc32xx_pwm_chip {
2132fa8d APS	18	struct clk *clk;
	19	void __iomem *base;
	20	};
	21
5a9fc9c6	22	#define PWM_ENABLE BIT(31)
acfd92fd	23	#define PWM_PIN_LEVEL BIT(30)
2132fa8d	24
ac4b44ca UKK	25	static inline struct lpc32xx_pwm_chip to_lpc32xx_pwm_chip(struct pwm_chip chip)
	26	{
	27	return pwmchip_get_drvdata(chip);
	28	}
2132fa8d APS	29
	30	static int lpc32xx_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	31	int duty_ns, int period_ns)
	32	{
	33	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
	34	unsigned long long c;
	35	int period_cycles, duty_cycles;
affb923d	36	u32 val;
5a9fc9c6	37	c = clk_get_rate(lpc32xx->clk);
2132fa8d	38
5a9fc9c6 VZ	39	/* The highest acceptable divisor is 256, which is represented by 0 */
	40	period_cycles = div64_u64(c * period_ns,
	41	(unsigned long long)NSEC_PER_SEC * 256);
d6dbdf0d VZ	42	if (!period_cycles \|\| period_cycles > 256)
	43	return -ERANGE;
	44	if (period_cycles == 256)
5a9fc9c6	45	period_cycles = 0;
2132fa8d	46
5a9fc9c6 VZ	47	/* Compute 256 x #duty/period value and care for corner cases */
	48	duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
	49	period_ns);
	50	if (!duty_cycles)
	51	duty_cycles = 1;
	52	if (duty_cycles > 255)
	53	duty_cycles = 255;
2132fa8d	54
4aae44f6	55	val = readl(lpc32xx->base);
affb923d	56	val &= ~0xFFFF;
5a9fc9c6	57	val \|= (period_cycles << 8) \| duty_cycles;
4aae44f6	58	writel(val, lpc32xx->base);
2132fa8d APS	59
	60	return 0;
	61	}
	62
	63	static int lpc32xx_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	64	{
	65	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	66	u32 val;
	67	int ret;
	68
82aff048	69	ret = clk_prepare_enable(lpc32xx->clk);
08ee77b5 AL	70	if (ret)
	71	return ret;
	72
4aae44f6	73	val = readl(lpc32xx->base);
08ee77b5	74	val \|= PWM_ENABLE;
4aae44f6	75	writel(val, lpc32xx->base);
2132fa8d	76
08ee77b5	77	return 0;
2132fa8d APS	78	}
	79
	80	static void lpc32xx_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	81	{
	82	struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
08ee77b5 AL	83	u32 val;
08ee77b5 AL	84
4aae44f6	85	val = readl(lpc32xx->base);
08ee77b5	86	val &= ~PWM_ENABLE;
4aae44f6	87	writel(val, lpc32xx->base);
2132fa8d	88
82aff048	89	clk_disable_unprepare(lpc32xx->clk);
2132fa8d APS	90	}
2132fa8d APS	91
5fa3b87f UKK	92	static int lpc32xx_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	93	const struct pwm_state *state)
	94	{
	95	int err;
	96
	97	if (state->polarity != PWM_POLARITY_NORMAL)
	98	return -EINVAL;
	99
	100	if (!state->enabled) {
	101	if (pwm->state.enabled)
	102	lpc32xx_pwm_disable(chip, pwm);
	103
	104	return 0;
	105	}
	106
80943bbd	107	err = lpc32xx_pwm_config(chip, pwm, state->duty_cycle, state->period);
5fa3b87f UKK	108	if (err)
	109	return err;
	110
	111	if (!pwm->state.enabled)
	112	err = lpc32xx_pwm_enable(chip, pwm);
	113
	114	return err;
	115	}
	116
2132fa8d	117	static const struct pwm_ops lpc32xx_pwm_ops = {
5fa3b87f	118	.apply = lpc32xx_pwm_apply,
2132fa8d APS	119	};
	120
	121	static int lpc32xx_pwm_probe(struct platform_device *pdev)
	122	{
ac4b44ca	123	struct pwm_chip *chip;
2132fa8d	124	struct lpc32xx_pwm_chip *lpc32xx;
2132fa8d	125	int ret;
acfd92fd	126	u32 val;
2132fa8d	127
ac4b44ca UKK	128	chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*lpc32xx));
	129	if (IS_ERR(chip))
	130	return PTR_ERR(chip);
	131	lpc32xx = to_lpc32xx_pwm_chip(chip);
2132fa8d	132
fd7c575a	133	lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1 TR	134	if (IS_ERR(lpc32xx->base))
6d4294d1 TR	135	return PTR_ERR(lpc32xx->base);
2132fa8d APS	136
	137	lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
	138	if (IS_ERR(lpc32xx->clk))
	139	return PTR_ERR(lpc32xx->clk);
	140
ac4b44ca	141	chip->ops = &lpc32xx_pwm_ops;
2132fa8d	142
3d2813fb	143	/* If PWM is disabled, configure the output to the default value */
4aae44f6	144	val = readl(lpc32xx->base);
3d2813fb	145	val &= ~PWM_PIN_LEVEL;
4aae44f6	146	writel(val, lpc32xx->base);
3d2813fb	147
ac4b44ca	148	ret = devm_pwmchip_add(&pdev->dev, chip);
2132fa8d APS	149	if (ret < 0) {
	150	dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
	151	return ret;
	152	}
	153
2132fa8d APS	154	return 0;
	155	}
	156
f1a8870a	157	static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
2132fa8d APS	158	{ .compatible = "nxp,lpc3220-pwm", },
	159	{ /* sentinel */ }
	160	};
	161	MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
	162
	163	static struct platform_driver lpc32xx_pwm_driver = {
	164	.driver = {
	165	.name = "lpc32xx-pwm",
3cb3b2bf	166	.of_match_table = lpc32xx_pwm_dt_ids,
2132fa8d APS	167	},
2132fa8d APS	168	.probe = lpc32xx_pwm_probe,
2132fa8d APS	169	};
	170	module_platform_driver(lpc32xx_pwm_driver);
	171
	172	MODULE_ALIAS("platform:lpc32xx-pwm");
	173	MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
	174	MODULE_DESCRIPTION("LPC32XX PWM Driver");
	175	MODULE_LICENSE("GPL v2");