[people/ms/u-boot.git] / drivers / pwm / rk_pwm.c

/*
 * Copyright (c) 2016 Google, Inc
 * Written by Simon Glass <sjg@chromium.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <power/regulator.h>

DECLARE_GLOBAL_DATA_PTR;

struct rk_pwm_priv {
	struct rk3288_pwm *regs;
	ulong freq;
	uint enable_conf;
};

static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
{
	struct rk_pwm_priv *priv = dev_get_priv(dev);

	debug("%s: polarity=%u\n", __func__, polarity);
	priv->enable_conf &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
	if (polarity)
		priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
	else
		priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;

	return 0;
}

static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
			     uint duty_ns)
{
	struct rk_pwm_priv *priv = dev_get_priv(dev);
	struct rk3288_pwm *regs = priv->regs;
	unsigned long period, duty;

	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
	writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
		PWM_CONTINUOUS | priv->enable_conf |
		RK_PWM_DISABLE,
		&regs->ctrl);

	period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
	duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);

	writel(period, &regs->period_hpr);
	writel(duty, &regs->duty_lpr);
	debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);

	return 0;
}

static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
	struct rk_pwm_priv *priv = dev_get_priv(dev);
	struct rk3288_pwm *regs = priv->regs;

	debug("%s: Enable '%s'\n", __func__, dev->name);
	clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);

	return 0;
}

static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
{
	struct rk_pwm_priv *priv = dev_get_priv(dev);

	priv->regs = (struct rk3288_pwm *)devfdt_get_addr(dev);

	return 0;
}

static int rk_pwm_probe(struct udevice *dev)
{
	struct rk_pwm_priv *priv = dev_get_priv(dev);
	struct clk clk;
	int ret = 0;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		debug("%s get clock fail!\n", __func__);
		return -EINVAL;
	}
	priv->freq = clk_get_rate(&clk);
	priv->enable_conf = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;

	return 0;
}

static const struct pwm_ops rk_pwm_ops = {
	.set_invert	= rk_pwm_set_invert,
	.set_config	= rk_pwm_set_config,
	.set_enable	= rk_pwm_set_enable,
};

static const struct udevice_id rk_pwm_ids[] = {
	{ .compatible = "rockchip,rk3288-pwm" },
	{ }
};

U_BOOT_DRIVER(rk_pwm) = {
	.name	= "rk_pwm",
	.id	= UCLASS_PWM,
	.of_match = rk_pwm_ids,
	.ops	= &rk_pwm_ops,
	.ofdata_to_platdata	= rk_pwm_ofdata_to_platdata,
	.probe		= rk_pwm_probe,
	.priv_auto_alloc_size	= sizeof(struct rk_pwm_priv),
};
Commit	Line	Data
0e23fd81 SG	1	/*
	2	* Copyright (c) 2016 Google, Inc
	3	* Written by Simon Glass <sjg@chromium.org>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
12406ae2	9	#include <clk.h>
0e23fd81 SG	10	#include <div64.h>
	11	#include <dm.h>
	12	#include <pwm.h>
	13	#include <regmap.h>
	14	#include <syscon.h>
	15	#include <asm/io.h>
0e23fd81 SG	16	#include <asm/arch/pwm.h>
	17	#include <power/regulator.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	struct rk_pwm_priv {
	22	struct rk3288_pwm *regs;
12406ae2	23	ulong freq;
874ee59a	24	uint enable_conf;
0e23fd81 SG	25	};
0e23fd81 SG	26
874ee59a KY	27	static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
	28	{
	29	struct rk_pwm_priv *priv = dev_get_priv(dev);
	30
	31	debug("%s: polarity=%u\n", __func__, polarity);
06f4e36b	32	priv->enable_conf &= ~(PWM_DUTY_MASK \| PWM_INACTIVE_MASK);
874ee59a KY	33	if (polarity)
	34	priv->enable_conf \|= PWM_DUTY_NEGATIVE \| PWM_INACTIVE_POSTIVE;
	35	else
	36	priv->enable_conf \|= PWM_DUTY_POSTIVE \| PWM_INACTIVE_NEGATIVE;
	37
	38	return 0;
	39	}
	40
0e23fd81 SG	41	static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
	42	uint duty_ns)
	43	{
	44	struct rk_pwm_priv *priv = dev_get_priv(dev);
	45	struct rk3288_pwm *regs = priv->regs;
	46	unsigned long period, duty;
	47
	48	debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
	49	writel(PWM_SEL_SRC_CLK \| PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \|
874ee59a	50	PWM_CONTINUOUS \| priv->enable_conf \|
0e23fd81 SG	51	RK_PWM_DISABLE,
	52	&regs->ctrl);
	53
12406ae2 KY	54	period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
12406ae2 KY	55	duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
0e23fd81 SG	56
	57	writel(period, &regs->period_hpr);
	58	writel(duty, &regs->duty_lpr);
	59	debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
	60
	61	return 0;
	62	}
	63
	64	static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
	65	{
	66	struct rk_pwm_priv *priv = dev_get_priv(dev);
	67	struct rk3288_pwm *regs = priv->regs;
	68
	69	debug("%s: Enable '%s'\n", __func__, dev->name);
	70	clrsetbits_le32(&regs->ctrl, RK_PWM_ENABLE, enable ? RK_PWM_ENABLE : 0);
	71
	72	return 0;
	73	}
	74
	75	static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
	76	{
	77	struct rk_pwm_priv *priv = dev_get_priv(dev);
0e23fd81	78
a821c4af	79	priv->regs = (struct rk3288_pwm *)devfdt_get_addr(dev);
0e23fd81 SG	80
	81	return 0;
	82	}
	83
	84	static int rk_pwm_probe(struct udevice *dev)
	85	{
	86	struct rk_pwm_priv *priv = dev_get_priv(dev);
12406ae2 KY	87	struct clk clk;
12406ae2 KY	88	int ret = 0;
0e23fd81	89
12406ae2 KY	90	ret = clk_get_by_index(dev, 0, &clk);
	91	if (ret < 0) {
	92	debug("%s get clock fail!\n", __func__);
	93	return -EINVAL;
	94	}
	95	priv->freq = clk_get_rate(&clk);
38510598	96	priv->enable_conf = PWM_DUTY_POSTIVE \| PWM_INACTIVE_POSTIVE;
12406ae2	97
0e23fd81 SG	98	return 0;
	99	}
	100
	101	static const struct pwm_ops rk_pwm_ops = {
874ee59a	102	.set_invert = rk_pwm_set_invert,
0e23fd81 SG	103	.set_config = rk_pwm_set_config,
	104	.set_enable = rk_pwm_set_enable,
	105	};
	106
	107	static const struct udevice_id rk_pwm_ids[] = {
	108	{ .compatible = "rockchip,rk3288-pwm" },
	109	{ }
	110	};
	111
	112	U_BOOT_DRIVER(rk_pwm) = {
	113	.name = "rk_pwm",
	114	.id = UCLASS_PWM,
	115	.of_match = rk_pwm_ids,
	116	.ops = &rk_pwm_ops,
	117	.ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
	118	.probe = rk_pwm_probe,
	119	.priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
	120	};