[people/ms/u-boot.git] / drivers / qe / uec_phy.h

/*
 * Copyright (C) 2005 Freescale Semiconductor, Inc.
 *
 * Author: Shlomi Gridish <gridish@freescale.com>
 *
 * Description: UCC ethernet driver -- PHY handling
 *		Driver for UEC on QE
 *		Based on 8260_io/fcc_enet.c
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#ifndef __UEC_PHY_H__
#define __UEC_PHY_H__

#define MII_end ((u32)-2)
#define MII_read ((u32)-1)

#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004

#define UGETH_AN_TIMEOUT	2000

/* 1000BT control (Marvell & BCM54xx at least) */
#define MII_1000BASETCONTROL		      0x09
#define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
#define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100

/* 1000BT status */
#define MII_1000BASETSTATUS	0x0a
#define LPA_1000FULL		0x0400
#define LPA_1000HALF		0x0200

/* Cicada Extended Control Register 1 */
#define MII_CIS8201_EXT_CON1	    0x17
#define MII_CIS8201_EXTCON1_INIT    0x0000

/* Cicada Interrupt Mask Register */
#define MII_CIS8201_IMASK	    0x19
#define MII_CIS8201_IMASK_IEN	    0x8000
#define MII_CIS8201_IMASK_SPEED	    0x4000
#define MII_CIS8201_IMASK_LINK	    0x2000
#define MII_CIS8201_IMASK_DUPLEX    0x1000
#define MII_CIS8201_IMASK_MASK	    0xf000

/* Cicada Interrupt Status Register */
#define MII_CIS8201_ISTAT	    0x1a
#define MII_CIS8201_ISTAT_STATUS    0x8000
#define MII_CIS8201_ISTAT_SPEED	    0x4000
#define MII_CIS8201_ISTAT_LINK	    0x2000
#define MII_CIS8201_ISTAT_DUPLEX    0x1000

/* Cicada Auxiliary Control/Status Register */
#define MII_CIS8201_AUX_CONSTAT	       0x1c
#define MII_CIS8201_AUXCONSTAT_INIT    0x0004
#define MII_CIS8201_AUXCONSTAT_DUPLEX  0x0020
#define MII_CIS8201_AUXCONSTAT_SPEED   0x0018
#define MII_CIS8201_AUXCONSTAT_GBIT    0x0010
#define MII_CIS8201_AUXCONSTAT_100     0x0008

/* 88E1011 PHY Status Register */
#define MII_M1011_PHY_SPEC_STATUS		0x11
#define MII_M1011_PHY_SPEC_STATUS_1000		0x8000
#define MII_M1011_PHY_SPEC_STATUS_100		0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK	0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX	0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED	0x0800
#define MII_M1011_PHY_SPEC_STATUS_LINK		0x0400

#define MII_M1011_IEVENT		0x13
#define MII_M1011_IEVENT_CLEAR		0x0000

#define MII_M1011_IMASK			0x12
#define MII_M1011_IMASK_INIT		0x6400
#define MII_M1011_IMASK_CLEAR		0x0000

/* 88E1111 PHY Register */
#define MII_M1111_PHY_EXT_CR            0x14
#define MII_M1111_RX_DELAY              0x80
#define MII_M1111_TX_DELAY              0x2
#define MII_M1111_PHY_EXT_SR            0x1b
#define MII_M1111_HWCFG_MODE_MASK       0xf
#define MII_M1111_HWCFG_MODE_RGMII      0xb

#define MII_DM9161_SCR			0x10
#define MII_DM9161_SCR_INIT		0x0610
#define MII_DM9161_SCR_RMII_INIT	0x0710

/* DM9161 Specified Configuration and Status Register */
#define MII_DM9161_SCSR			0x11
#define MII_DM9161_SCSR_100F		0x8000
#define MII_DM9161_SCSR_100H		0x4000
#define MII_DM9161_SCSR_10F		0x2000
#define MII_DM9161_SCSR_10H		0x1000

/* DM9161 Interrupt Register */
#define MII_DM9161_INTR			0x15
#define MII_DM9161_INTR_PEND		0x8000
#define MII_DM9161_INTR_DPLX_MASK	0x0800
#define MII_DM9161_INTR_SPD_MASK	0x0400
#define MII_DM9161_INTR_LINK_MASK	0x0200
#define MII_DM9161_INTR_MASK		0x0100
#define MII_DM9161_INTR_DPLX_CHANGE	0x0010
#define MII_DM9161_INTR_SPD_CHANGE	0x0008
#define MII_DM9161_INTR_LINK_CHANGE	0x0004
#define MII_DM9161_INTR_INIT		0x0000
#define MII_DM9161_INTR_STOP	\
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)

/* DM9161 10BT Configuration/Status */
#define MII_DM9161_10BTCSR		0x12
#define MII_DM9161_10BTCSR_INIT		0x7800

#define MII_BASIC_FEATURES    (SUPPORTED_10baseT_Half | \
		 SUPPORTED_10baseT_Full | \
		 SUPPORTED_100baseT_Half | \
		 SUPPORTED_100baseT_Full | \
		 SUPPORTED_Autoneg | \
		 SUPPORTED_TP | \
		 SUPPORTED_MII)

#define MII_GBIT_FEATURES    (MII_BASIC_FEATURES | \
		 SUPPORTED_1000baseT_Half | \
		 SUPPORTED_1000baseT_Full)

#define MII_READ_COMMAND		0x00000001

#define MII_INTERRUPT_DISABLED		0x0
#define MII_INTERRUPT_ENABLED		0x1

#define SPEED_10    10
#define SPEED_100   100
#define SPEED_1000  1000

/* Duplex, half or full. */
#define DUPLEX_HALF		0x00
#define DUPLEX_FULL		0x01

/* Indicates what features are supported by the interface. */
#define SUPPORTED_10baseT_Half		(1 << 0)
#define SUPPORTED_10baseT_Full		(1 << 1)
#define SUPPORTED_100baseT_Half		(1 << 2)
#define SUPPORTED_100baseT_Full		(1 << 3)
#define SUPPORTED_1000baseT_Half	(1 << 4)
#define SUPPORTED_1000baseT_Full	(1 << 5)
#define SUPPORTED_Autoneg		(1 << 6)
#define SUPPORTED_TP			(1 << 7)
#define SUPPORTED_AUI			(1 << 8)
#define SUPPORTED_MII			(1 << 9)
#define SUPPORTED_FIBRE			(1 << 10)
#define SUPPORTED_BNC			(1 << 11)
#define SUPPORTED_10000baseT_Full	(1 << 12)

#define ADVERTISED_10baseT_Half		(1 << 0)
#define ADVERTISED_10baseT_Full		(1 << 1)
#define ADVERTISED_100baseT_Half	(1 << 2)
#define ADVERTISED_100baseT_Full	(1 << 3)
#define ADVERTISED_1000baseT_Half	(1 << 4)
#define ADVERTISED_1000baseT_Full	(1 << 5)
#define ADVERTISED_Autoneg		(1 << 6)
#define ADVERTISED_TP			(1 << 7)
#define ADVERTISED_AUI			(1 << 8)
#define ADVERTISED_MII			(1 << 9)
#define ADVERTISED_FIBRE		(1 << 10)
#define ADVERTISED_BNC			(1 << 11)
#define ADVERTISED_10000baseT_Full	(1 << 12)

/* Advertisement control register. */
#define ADVERTISE_SLCT		0x001f	/* Selector bits	       */
#define ADVERTISE_CSMA		0x0001	/* Only selector supported     */
#define ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex  */
#define ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex  */
#define ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets  */
#define ADVERTISE_RESV		0x1c00	/* Unused...		       */
#define ADVERTISE_RFAULT	0x2000	/* Say we can detect faults    */
#define ADVERTISE_LPACK		0x4000	/* Ack link partners response  */
#define ADVERTISE_NPAGE		0x8000	/* Next page bit	       */

#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
			ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
		       ADVERTISE_100HALF | ADVERTISE_100FULL)

/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
	/* Information about the PHY type */
	/* And management functions */
	struct phy_info *phyinfo;

	struct eth_device *dev;

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;
	int pause;

	/* The most recently read link state */
	int link;

	/* Enabled Interrupts */
	u32 interrupts;

	u32 advertising;
	int autoneg;
	int mii_id;

	/* private data pointer */
	/* For use by PHYs to maintain extra state */
	void *priv;

	/* Provided by ethernet driver */
	int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
	void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
			    int val);
};

/* struct phy_info: a structure which defines attributes for a PHY
 *
 * id will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be ANDed with phy_id_mask to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 * There are 6 commands which take a ugeth_mii_info structure.
 * Each PHY must declare config_aneg, and read_status.
 */
struct phy_info {
	u32 phy_id;
	char *name;
	unsigned int phy_id_mask;
	u32 features;

	/* Called to initialize the PHY */
	int (*init) (struct uec_mii_info * mii_info);

	/* Called to suspend the PHY for power */
	int (*suspend) (struct uec_mii_info * mii_info);

	/* Reconfigures autonegotiation (or disables it) */
	int (*config_aneg) (struct uec_mii_info * mii_info);

	/* Determines the negotiated speed and duplex */
	int (*read_status) (struct uec_mii_info * mii_info);

	/* Clears any pending interrupts */
	int (*ack_interrupt) (struct uec_mii_info * mii_info);

	/* Enables or disables interrupts */
	int (*config_intr) (struct uec_mii_info * mii_info);

	/* Clears up any memory if needed */
	void (*close) (struct uec_mii_info * mii_info);
};

struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
		    int value);
int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
				  u32 interrupts);
#endif /* __UEC_PHY_H__ */
Commit	Line	Data
7737d5c6 DL	1	/*
	2	* Copyright (C) 2005 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Shlomi Gridish <gridish@freescale.com>
	5	*
	6	* Description: UCC ethernet driver -- PHY handling
dd520bf3 WD	7	* Driver for UEC on QE
dd520bf3 WD	8	* Based on 8260_io/fcc_enet.c
7737d5c6	9	*
dd520bf3 WD	10	* This program is free software; you can redistribute it and/or modify it
dd520bf3 WD	11	* under the terms of the GNU General Public License as published by the
7737d5c6 DL	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	*/
	16	#ifndef __UEC_PHY_H__
	17	#define __UEC_PHY_H__
	18
	19	#define MII_end ((u32)-2)
	20	#define MII_read ((u32)-1)
	21
dd520bf3 WD	22	#define MIIMIND_BUSY 0x00000001
dd520bf3 WD	23	#define MIIMIND_NOTVALID 0x00000004
7737d5c6	24
dd520bf3	25	#define UGETH_AN_TIMEOUT 2000
7737d5c6 DL	26
7737d5c6 DL	27	/* 1000BT control (Marvell & BCM54xx at least) */
dd520bf3	28	#define MII_1000BASETCONTROL 0x09
7737d5c6 DL	29	#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
	30	#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
	31
91cdaa3a AV	32	/* 1000BT status */
	33	#define MII_1000BASETSTATUS 0x0a
	34	#define LPA_1000FULL 0x0400
	35	#define LPA_1000HALF 0x0200
	36
7737d5c6	37	/* Cicada Extended Control Register 1 */
dd520bf3	38	#define MII_CIS8201_EXT_CON1 0x17
7737d5c6 DL	39	#define MII_CIS8201_EXTCON1_INIT 0x0000
	40
	41	/* Cicada Interrupt Mask Register */
dd520bf3 WD	42	#define MII_CIS8201_IMASK 0x19
	43	#define MII_CIS8201_IMASK_IEN 0x8000
	44	#define MII_CIS8201_IMASK_SPEED 0x4000
	45	#define MII_CIS8201_IMASK_LINK 0x2000
7737d5c6	46	#define MII_CIS8201_IMASK_DUPLEX 0x1000
dd520bf3	47	#define MII_CIS8201_IMASK_MASK 0xf000
7737d5c6 DL	48
7737d5c6 DL	49	/* Cicada Interrupt Status Register */
dd520bf3	50	#define MII_CIS8201_ISTAT 0x1a
7737d5c6	51	#define MII_CIS8201_ISTAT_STATUS 0x8000
dd520bf3 WD	52	#define MII_CIS8201_ISTAT_SPEED 0x4000
dd520bf3 WD	53	#define MII_CIS8201_ISTAT_LINK 0x2000
7737d5c6 DL	54	#define MII_CIS8201_ISTAT_DUPLEX 0x1000
	55
	56	/* Cicada Auxiliary Control/Status Register */
dd520bf3	57	#define MII_CIS8201_AUX_CONSTAT 0x1c
7737d5c6 DL	58	#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
	59	#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
	60	#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
	61	#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
	62	#define MII_CIS8201_AUXCONSTAT_100 0x0008
	63
	64	/* 88E1011 PHY Status Register */
dd520bf3 WD	65	#define MII_M1011_PHY_SPEC_STATUS 0x11
	66	#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
	67	#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
	68	#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
	69	#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
	70	#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
	71	#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
	72
	73	#define MII_M1011_IEVENT 0x13
	74	#define MII_M1011_IEVENT_CLEAR 0x0000
	75
	76	#define MII_M1011_IMASK 0x12
	77	#define MII_M1011_IMASK_INIT 0x6400
	78	#define MII_M1011_IMASK_CLEAR 0x0000
	79
41410eee HW	80	/* 88E1111 PHY Register */
	81	#define MII_M1111_PHY_EXT_CR 0x14
	82	#define MII_M1111_RX_DELAY 0x80
	83	#define MII_M1111_TX_DELAY 0x2
	84	#define MII_M1111_PHY_EXT_SR 0x1b
	85	#define MII_M1111_HWCFG_MODE_MASK 0xf
	86	#define MII_M1111_HWCFG_MODE_RGMII 0xb
	87
dd520bf3 WD	88	#define MII_DM9161_SCR 0x10
dd520bf3 WD	89	#define MII_DM9161_SCR_INIT 0x0610
7737d5c6 DL	90	#define MII_DM9161_SCR_RMII_INIT 0x0710
	91
	92	/* DM9161 Specified Configuration and Status Register */
dd520bf3 WD	93	#define MII_DM9161_SCSR 0x11
	94	#define MII_DM9161_SCSR_100F 0x8000
	95	#define MII_DM9161_SCSR_100H 0x4000
	96	#define MII_DM9161_SCSR_10F 0x2000
	97	#define MII_DM9161_SCSR_10H 0x1000
7737d5c6 DL	98
7737d5c6 DL	99	/* DM9161 Interrupt Register */
dd520bf3 WD	100	#define MII_DM9161_INTR 0x15
	101	#define MII_DM9161_INTR_PEND 0x8000
	102	#define MII_DM9161_INTR_DPLX_MASK 0x0800
	103	#define MII_DM9161_INTR_SPD_MASK 0x0400
	104	#define MII_DM9161_INTR_LINK_MASK 0x0200
	105	#define MII_DM9161_INTR_MASK 0x0100
	106	#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
	107	#define MII_DM9161_INTR_SPD_CHANGE 0x0008
	108	#define MII_DM9161_INTR_LINK_CHANGE 0x0004
	109	#define MII_DM9161_INTR_INIT 0x0000
	110	#define MII_DM9161_INTR_STOP \
7737d5c6 DL	111	(MII_DM9161_INTR_DPLX_MASK \| MII_DM9161_INTR_SPD_MASK \
	112	\| MII_DM9161_INTR_LINK_MASK \| MII_DM9161_INTR_MASK)
	113
	114	/* DM9161 10BT Configuration/Status */
dd520bf3 WD	115	#define MII_DM9161_10BTCSR 0x12
dd520bf3 WD	116	#define MII_DM9161_10BTCSR_INIT 0x7800
7737d5c6 DL	117
7737d5c6 DL	118	#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half \| \
dd520bf3 WD	119	SUPPORTED_10baseT_Full \| \
	120	SUPPORTED_100baseT_Half \| \
	121	SUPPORTED_100baseT_Full \| \
	122	SUPPORTED_Autoneg \| \
	123	SUPPORTED_TP \| \
	124	SUPPORTED_MII)
7737d5c6 DL	125
7737d5c6 DL	126	#define MII_GBIT_FEATURES (MII_BASIC_FEATURES \| \
dd520bf3 WD	127	SUPPORTED_1000baseT_Half \| \
dd520bf3 WD	128	SUPPORTED_1000baseT_Full)
7737d5c6	129
dd520bf3	130	#define MII_READ_COMMAND 0x00000001
7737d5c6	131
dd520bf3 WD	132	#define MII_INTERRUPT_DISABLED 0x0
dd520bf3 WD	133	#define MII_INTERRUPT_ENABLED 0x1
7737d5c6 DL	134
	135	#define SPEED_10 10
	136	#define SPEED_100 100
	137	#define SPEED_1000 1000
	138
	139	/* Duplex, half or full. */
dd520bf3 WD	140	#define DUPLEX_HALF 0x00
dd520bf3 WD	141	#define DUPLEX_FULL 0x01
7737d5c6 DL	142
7737d5c6 DL	143	/* Indicates what features are supported by the interface. */
dd520bf3 WD	144	#define SUPPORTED_10baseT_Half (1 << 0)
	145	#define SUPPORTED_10baseT_Full (1 << 1)
	146	#define SUPPORTED_100baseT_Half (1 << 2)
	147	#define SUPPORTED_100baseT_Full (1 << 3)
	148	#define SUPPORTED_1000baseT_Half (1 << 4)
	149	#define SUPPORTED_1000baseT_Full (1 << 5)
	150	#define SUPPORTED_Autoneg (1 << 6)
	151	#define SUPPORTED_TP (1 << 7)
	152	#define SUPPORTED_AUI (1 << 8)
	153	#define SUPPORTED_MII (1 << 9)
	154	#define SUPPORTED_FIBRE (1 << 10)
	155	#define SUPPORTED_BNC (1 << 11)
	156	#define SUPPORTED_10000baseT_Full (1 << 12)
	157
	158	#define ADVERTISED_10baseT_Half (1 << 0)
	159	#define ADVERTISED_10baseT_Full (1 << 1)
	160	#define ADVERTISED_100baseT_Half (1 << 2)
	161	#define ADVERTISED_100baseT_Full (1 << 3)
	162	#define ADVERTISED_1000baseT_Half (1 << 4)
	163	#define ADVERTISED_1000baseT_Full (1 << 5)
	164	#define ADVERTISED_Autoneg (1 << 6)
	165	#define ADVERTISED_TP (1 << 7)
	166	#define ADVERTISED_AUI (1 << 8)
	167	#define ADVERTISED_MII (1 << 9)
	168	#define ADVERTISED_FIBRE (1 << 10)
	169	#define ADVERTISED_BNC (1 << 11)
	170	#define ADVERTISED_10000baseT_Full (1 << 12)
7737d5c6 DL	171
7737d5c6 DL	172	/* Advertisement control register. */
dd520bf3 WD	173	#define ADVERTISE_SLCT 0x001f /* Selector bits */
	174	#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
	175	#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
	176	#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
	177	#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
	178	#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
	179	#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
	180	#define ADVERTISE_RESV 0x1c00 /* Unused... */
	181	#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
	182	#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
	183	#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
7737d5c6 DL	184
7737d5c6 DL	185	#define ADVERTISE_FULL (ADVERTISE_100FULL \| ADVERTISE_10FULL \| \
dd520bf3	186	ADVERTISE_CSMA)
7737d5c6	187	#define ADVERTISE_ALL (ADVERTISE_10HALF \| ADVERTISE_10FULL \| \
dd520bf3	188	ADVERTISE_100HALF \| ADVERTISE_100FULL)
7737d5c6 DL	189
	190	/* Taken from mii_if_info and sungem_phy.h */
	191	struct uec_mii_info {
dd520bf3 WD	192	/* Information about the PHY type */
	193	/* And management functions */
	194	struct phy_info *phyinfo;
7737d5c6	195
dd520bf3	196	struct eth_device *dev;
7737d5c6	197
dd520bf3 WD	198	/* forced speed & duplex (no autoneg)
	199	* partner speed & duplex & pause (autoneg)
	200	*/
	201	int speed;
	202	int duplex;
	203	int pause;
7737d5c6	204
dd520bf3 WD	205	/* The most recently read link state */
dd520bf3 WD	206	int link;
7737d5c6	207
dd520bf3 WD	208	/* Enabled Interrupts */
dd520bf3 WD	209	u32 interrupts;
7737d5c6	210
dd520bf3 WD	211	u32 advertising;
	212	int autoneg;
	213	int mii_id;
7737d5c6	214
dd520bf3 WD	215	/* private data pointer */
	216	/* For use by PHYs to maintain extra state */
	217	void *priv;
7737d5c6	218
dd520bf3 WD	219	/* Provided by ethernet driver */
	220	int (mdio_read) (struct eth_device dev, int mii_id, int reg);
	221	void (mdio_write) (struct eth_device dev, int mii_id, int reg,
	222	int val);
7737d5c6 DL	223	};
	224
	225	/* struct phy_info: a structure which defines attributes for a PHY
	226	*
	227	* id will contain a number which represents the PHY. During
	228	* startup, the driver will poll the PHY to find out what its
	229	* UID--as defined by registers 2 and 3--is. The 32-bit result
	230	* gotten from the PHY will be ANDed with phy_id_mask to
	231	* discard any bits which may change based on revision numbers
	232	* unimportant to functionality
	233	*
	234	* There are 6 commands which take a ugeth_mii_info structure.
	235	* Each PHY must declare config_aneg, and read_status.
	236	*/
	237	struct phy_info {
dd520bf3 WD	238	u32 phy_id;
	239	char *name;
	240	unsigned int phy_id_mask;
	241	u32 features;
7737d5c6	242
dd520bf3 WD	243	/* Called to initialize the PHY */
dd520bf3 WD	244	int (init) (struct uec_mii_info mii_info);
7737d5c6	245
dd520bf3 WD	246	/* Called to suspend the PHY for power */
dd520bf3 WD	247	int (suspend) (struct uec_mii_info mii_info);
7737d5c6	248
dd520bf3 WD	249	/* Reconfigures autonegotiation (or disables it) */
dd520bf3 WD	250	int (config_aneg) (struct uec_mii_info mii_info);
7737d5c6	251
dd520bf3 WD	252	/* Determines the negotiated speed and duplex */
dd520bf3 WD	253	int (read_status) (struct uec_mii_info mii_info);
7737d5c6	254
dd520bf3 WD	255	/* Clears any pending interrupts */
dd520bf3 WD	256	int (ack_interrupt) (struct uec_mii_info mii_info);
7737d5c6	257
dd520bf3 WD	258	/* Enables or disables interrupts */
dd520bf3 WD	259	int (config_intr) (struct uec_mii_info mii_info);
7737d5c6	260
dd520bf3 WD	261	/* Clears up any memory if needed */
dd520bf3 WD	262	void (close) (struct uec_mii_info mii_info);
7737d5c6 DL	263	};
7737d5c6 DL	264
da9d4610 AF	265	struct phy_info uec_get_phy_info (struct uec_mii_info mii_info);
da9d4610 AF	266	void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
dd520bf3	267	int value);
da9d4610	268	int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
dd520bf3 WD	269	void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
	270	void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
	271	u32 interrupts);
7737d5c6	272	#endif /* __UEC_PHY_H__ */