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reset: zynqmp: Add reset controller for ZynqMP SoC
[thirdparty/u-boot.git] / drivers / reset / Kconfig
CommitLineData
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SW
1menu "Reset Controller Support"
2
3config DM_RESET
4 bool "Enable reset controllers using Driver Model"
5 depends on DM && OF_CONTROL
6 help
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
11 cases this API is applicable to chips outside the CPU as well,
12 although driving such reset isgnals using GPIOs may be more
13 appropriate in this case.
14
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15config SANDBOX_RESET
16 bool "Enable the sandbox reset test driver"
17 depends on DM_MAILBOX && SANDBOX
18 help
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
21 doing anything beyond a little error checking.
22
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23config STI_RESET
24 bool "Enable the STi reset"
25 depends on ARCH_STI
26 help
27 Support for reset controllers on STMicroelectronics STiH407 family SoCs.
28 Say Y if you want to control reset signals provided by system config
29 block.
30
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31config STM32_RESET
32 bool "Enable the STM32 reset"
71f6354b 33 depends on ARCH_STM32 || ARCH_STM32MP
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34 help
35 Support for reset controllers on STMicroelectronics STM32 family SoCs.
1bc5d3a5 36 This reset driver is compatible with STM32 F4/F7 and H7 SoCs.
23a06416 37
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38config TEGRA_CAR_RESET
39 bool "Enable Tegra CAR-based reset driver"
40 depends on TEGRA_CAR
41 help
42 Enable support for manipulating Tegra's on-SoC reset signals via
43 direct register access to the Tegra CAR (Clock And Reset controller).
44
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45config TEGRA186_RESET
46 bool "Enable Tegra186 BPMP-based reset driver"
47 depends on TEGRA186_BPMP
48 help
49 Enable support for manipulating Tegra's on-SoC reset signals via IPC
50 requests to the BPMP (Boot and Power Management Processor).
51
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AD
52config RESET_TI_SCI
53 bool "TI System Control Interface (TI SCI) reset driver"
54 depends on DM_RESET && TI_SCI_PROTOCOL
55 help
56 This enables the reset driver support over TI System Control Interface
57 available on some new TI's SoCs. If you wish to use reset resources
58 managed by the TI System Controller, say Y here. Otherwise, say N.
59
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ÁFR
60config RESET_BCM6345
61 bool "Reset controller driver for BCM6345"
62 depends on DM_RESET && ARCH_BMIPS
63 help
64 Support reset controller on BCM6345.
65
4fb96c48
MY
66config RESET_UNIPHIER
67 bool "Reset controller driver for UniPhier SoCs"
68 depends on ARCH_UNIPHIER
69 default y
70 help
71 Support for reset controllers on UniPhier SoCs.
72 Say Y if you want to control reset signals provided by System Control
73 block, Media I/O block, Peripheral Block.
74
b2424cd2 75config RESET_AST2500
858d4976 76 bool "Reset controller driver for AST2500 SoCs"
611a28ce 77 depends on DM_RESET
858d4976 78 default y if ASPEED_AST2500
79 help
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80 Support for reset controller on AST2500 SoC.
81 Say Y if you want to control reset signals of different peripherals
82 through System Control Unit (SCU).
858d4976 83
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84config RESET_AST2600
85 bool "Reset controller driver for AST2600 SoCs"
86 depends on DM_RESET
87 default y if ASPEED_AST2600
88 help
89 Support for reset controller on AST2600 SoC.
90 Say Y if you want to control reset signals of different peripherals
91 through System Control Unit (SCU).
92
760188c1
EZ
93config RESET_ROCKCHIP
94 bool "Reset controller driver for Rockchip SoCs"
95 depends on DM_RESET && ARCH_ROCKCHIP && CLK
96 default y
97 help
98 Support for reset controller on rockchip SoC. The main limitation
99 though is that some reset signals, like I2C or MISC reset multiple
100 devices.
101
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102config RESET_HSDK
103 bool "Synopsys HSDK Reset Driver"
104 depends on DM_RESET && TARGET_HSDK
105 default y
106 help
107 This enables the reset controller driver for HSDK board.
108
20367bb5
NA
109config RESET_MESON
110 bool "Reset controller driver for Amlogic Meson SoCs"
111 depends on DM_RESET && ARCH_MESON
112 imply REGMAP
113 default y
114 help
115 Support for reset controller on Amlogic Meson SoC.
116
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DN
117config RESET_SOCFPGA
118 bool "Reset controller driver for SoCFPGA"
119 depends on DM_RESET && ARCH_SOCFPGA
120 default y
121 help
122 Support for reset controller on SoCFPGA platform.
123
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WG
124config RESET_MEDIATEK
125 bool "Reset controller driver for MediaTek SoCs"
126 depends on DM_RESET && ARCH_MEDIATEK && CLK
127 default y
128 help
129 Support for reset controller on MediaTek SoCs.
130
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WG
131config RESET_MTMIPS
132 bool "Reset controller driver for MediaTek MIPS platform"
133 depends on DM_RESET && ARCH_MTMIPS
134 default y
135 help
136 Support for reset controller on MediaTek MIPS platform.
137
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138config RESET_SUNXI
139 bool "RESET support for Allwinner SoCs"
140 depends on DM_RESET && ARCH_SUNXI
141 default y
142 help
143 This enables support for common reset driver for
144 Allwinner SoCs.
145
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SG
146config RESET_HISILICON
147 bool "Reset controller driver for HiSilicon SoCs"
148 depends on DM_RESET
149 help
150 Support for reset controller on HiSilicon SoCs.
151
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PW
152config RESET_IMX7
153 bool "i.MX7/8 Reset Driver"
154 depends on DM_RESET && (ARCH_MX7 || ARCH_IMX8M)
155 default y
156 help
157 Support for reset controller on i.MX7/8 SoCs.
158
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159config RESET_IPQ419
160 bool "Reset driver for Qualcomm IPQ40xx SoCs"
161 depends on DM_RESET && ARCH_IPQ40XX
162 default y
163 help
164 Support for reset controller on Qualcomm
165 IPQ40xx SoCs.
166
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SSK
167config RESET_SIFIVE
168 bool "Reset Driver for SiFive SoC's"
70415e1e 169 depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
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SSK
170 default y
171 help
172 PRCI module within SiFive SoC's provides mechanism to reset
173 different hw blocks like DDR, gemgxl. With this driver we leverage
174 U-Boot's reset framework to reset these hardware blocks.
175
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176config RESET_SYSCON
177 bool "Enable generic syscon reset driver support"
178 depends on DM_RESET
179 help
180 Support generic syscon mapped register reset devices.
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NSJ
181
182config RESET_RASPBERRYPI
183 bool "Raspberry Pi 4 Firmware Reset Controller Driver"
184 depends on DM_RESET && ARCH_BCM283X
185 default USB_XHCI_PCI
186 help
187 Raspberry Pi 4's co-processor controls some of the board's HW
188 initialization process, but it's up to Linux to trigger it when
189 relevant. This driver provides a reset controller capable of
190 interfacing with RPi4's co-processor and model these firmware
191 initialization routines as reset lines.
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EC
192
193config RESET_SCMI
194 bool "Enable SCMI reset domain driver"
195 select SCMI_FIRMWARE
196 help
197 Enable this option if you want to support reset controller
198 devices exposed by a SCMI agent based on SCMI reset domain
199 protocol communication with a SCMI server.
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MS
200
201config RESET_ZYNQMP
202 bool "Reset Driver for Xilinx ZynqMP SoC's"
203 depends on DM_RESET && ZYNQMP_FIRMWARE
204 help
205 Support for reset controller on Xilinx ZynqMP SoC. Driver is only
206 passing request via Xilinx firmware interface to TF-A and PMU
207 firmware.
208
89c1e2da 209endmenu