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8e8e69d6 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
abf97755 AS |
2 | /* |
3 | * Copyright (c) 2017, Impinj, Inc. | |
4 | * | |
5 | * i.MX7 System Reset Controller (SRC) driver | |
6 | * | |
7 | * Author: Andrey Smirnov <andrew.smirnov@gmail.com> | |
abf97755 AS |
8 | */ |
9 | ||
10 | #include <linux/mfd/syscon.h> | |
a442abbb | 11 | #include <linux/module.h> |
10590358 | 12 | #include <linux/of_device.h> |
abf97755 AS |
13 | #include <linux/platform_device.h> |
14 | #include <linux/reset-controller.h> | |
15 | #include <linux/regmap.h> | |
16 | #include <dt-bindings/reset/imx7-reset.h> | |
c979dbf5 | 17 | #include <dt-bindings/reset/imx8mq-reset.h> |
e08672c0 | 18 | #include <dt-bindings/reset/imx8mp-reset.h> |
abf97755 | 19 | |
10590358 AS |
20 | struct imx7_src_signal { |
21 | unsigned int offset, bit; | |
22 | }; | |
23 | ||
24 | struct imx7_src_variant { | |
25 | const struct imx7_src_signal *signals; | |
26 | unsigned int signals_num; | |
27 | struct reset_control_ops ops; | |
28 | }; | |
29 | ||
abf97755 AS |
30 | struct imx7_src { |
31 | struct reset_controller_dev rcdev; | |
32 | struct regmap *regmap; | |
10590358 | 33 | const struct imx7_src_signal *signals; |
abf97755 AS |
34 | }; |
35 | ||
36 | enum imx7_src_registers { | |
37 | SRC_A7RCR0 = 0x0004, | |
38 | SRC_M4RCR = 0x000c, | |
39 | SRC_ERCR = 0x0014, | |
40 | SRC_HSICPHY_RCR = 0x001c, | |
41 | SRC_USBOPHY1_RCR = 0x0020, | |
42 | SRC_USBOPHY2_RCR = 0x0024, | |
43 | SRC_MIPIPHY_RCR = 0x0028, | |
44 | SRC_PCIEPHY_RCR = 0x002c, | |
45 | SRC_DDRC_RCR = 0x1000, | |
46 | }; | |
47 | ||
10590358 AS |
48 | static int imx7_reset_update(struct imx7_src *imx7src, |
49 | unsigned long id, unsigned int value) | |
50 | { | |
51 | const struct imx7_src_signal *signal = &imx7src->signals[id]; | |
52 | ||
53 | return regmap_update_bits(imx7src->regmap, | |
54 | signal->offset, signal->bit, value); | |
55 | } | |
abf97755 AS |
56 | |
57 | static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { | |
58 | [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, | |
59 | [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, | |
60 | [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, | |
61 | [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, | |
62 | [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, | |
63 | [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, | |
64 | [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, | |
65 | [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, | |
66 | [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, | |
67 | [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, | |
68 | [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, | |
69 | [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, | |
70 | [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, | |
71 | [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, | |
72 | [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, | |
73 | [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, | |
74 | [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, | |
75 | [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, | |
76 | [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, | |
77 | [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, | |
78 | [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, | |
79 | [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, | |
80 | [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, | |
de248327 | 81 | [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, |
abf97755 AS |
82 | [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, |
83 | [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, | |
84 | }; | |
85 | ||
86 | static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev) | |
87 | { | |
88 | return container_of(rcdev, struct imx7_src, rcdev); | |
89 | } | |
90 | ||
91 | static int imx7_reset_set(struct reset_controller_dev *rcdev, | |
92 | unsigned long id, bool assert) | |
93 | { | |
94 | struct imx7_src *imx7src = to_imx7_src(rcdev); | |
10590358 AS |
95 | const unsigned int bit = imx7src->signals[id].bit; |
96 | unsigned int value = assert ? bit : 0; | |
abf97755 AS |
97 | |
98 | switch (id) { | |
99 | case IMX7_RESET_PCIEPHY: | |
100 | /* | |
101 | * wait for more than 10us to release phy g_rst and | |
102 | * btnrst | |
103 | */ | |
104 | if (!assert) | |
105 | udelay(10); | |
106 | break; | |
107 | ||
108 | case IMX7_RESET_PCIE_CTRL_APPS_EN: | |
10590358 | 109 | value = assert ? 0 : bit; |
abf97755 AS |
110 | break; |
111 | } | |
112 | ||
10590358 | 113 | return imx7_reset_update(imx7src, id, value); |
abf97755 AS |
114 | } |
115 | ||
116 | static int imx7_reset_assert(struct reset_controller_dev *rcdev, | |
117 | unsigned long id) | |
118 | { | |
119 | return imx7_reset_set(rcdev, id, true); | |
120 | } | |
121 | ||
122 | static int imx7_reset_deassert(struct reset_controller_dev *rcdev, | |
123 | unsigned long id) | |
124 | { | |
125 | return imx7_reset_set(rcdev, id, false); | |
126 | } | |
127 | ||
10590358 AS |
128 | static const struct imx7_src_variant variant_imx7 = { |
129 | .signals = imx7_src_signals, | |
130 | .signals_num = ARRAY_SIZE(imx7_src_signals), | |
131 | .ops = { | |
132 | .assert = imx7_reset_assert, | |
133 | .deassert = imx7_reset_deassert, | |
134 | }, | |
abf97755 AS |
135 | }; |
136 | ||
c979dbf5 AS |
137 | enum imx8mq_src_registers { |
138 | SRC_A53RCR0 = 0x0004, | |
139 | SRC_HDMI_RCR = 0x0030, | |
140 | SRC_DISP_RCR = 0x0034, | |
141 | SRC_GPU_RCR = 0x0040, | |
142 | SRC_VPU_RCR = 0x0044, | |
143 | SRC_PCIE2_RCR = 0x0048, | |
144 | SRC_MIPIPHY1_RCR = 0x004c, | |
145 | SRC_MIPIPHY2_RCR = 0x0050, | |
146 | SRC_DDRC2_RCR = 0x1004, | |
147 | }; | |
148 | ||
e08672c0 AH |
149 | enum imx8mp_src_registers { |
150 | SRC_SUPERMIX_RCR = 0x0018, | |
151 | SRC_AUDIOMIX_RCR = 0x001c, | |
152 | SRC_MLMIX_RCR = 0x0028, | |
153 | SRC_GPU2D_RCR = 0x0038, | |
154 | SRC_GPU3D_RCR = 0x003c, | |
155 | SRC_VPU_G1_RCR = 0x0048, | |
156 | SRC_VPU_G2_RCR = 0x004c, | |
157 | SRC_VPUVC8KE_RCR = 0x0050, | |
158 | SRC_NOC_RCR = 0x0054, | |
159 | }; | |
160 | ||
c979dbf5 AS |
161 | static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { |
162 | [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, | |
163 | [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, | |
164 | [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, | |
165 | [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, | |
166 | [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, | |
167 | [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, | |
168 | [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, | |
169 | [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, | |
170 | [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, | |
171 | [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, | |
172 | [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, | |
173 | [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, | |
174 | [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, | |
175 | [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, | |
176 | [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, | |
177 | [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, | |
178 | [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, | |
179 | [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, | |
180 | [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, | |
181 | [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, | |
182 | [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, | |
183 | [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, | |
184 | [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, | |
942b4c10 GG |
185 | [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, |
186 | [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, | |
187 | [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, | |
c979dbf5 AS |
188 | [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, |
189 | BIT(2) | BIT(1) }, | |
190 | [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, | |
191 | [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, | |
192 | [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, | |
193 | [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, | |
194 | [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, | |
195 | [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, | |
196 | [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, | |
197 | [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR, | |
198 | BIT(2) | BIT(1) }, | |
199 | [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, | |
200 | [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, | |
201 | [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, | |
202 | [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, | |
203 | [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, | |
204 | [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, | |
205 | [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, | |
206 | [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, | |
207 | [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, | |
208 | [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, | |
209 | [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, | |
210 | [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, | |
211 | [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, | |
212 | [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, | |
213 | [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, | |
214 | }; | |
215 | ||
216 | static int imx8mq_reset_set(struct reset_controller_dev *rcdev, | |
217 | unsigned long id, bool assert) | |
218 | { | |
219 | struct imx7_src *imx7src = to_imx7_src(rcdev); | |
220 | const unsigned int bit = imx7src->signals[id].bit; | |
221 | unsigned int value = assert ? bit : 0; | |
222 | ||
223 | switch (id) { | |
224 | case IMX8MQ_RESET_PCIEPHY: | |
225 | case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */ | |
226 | /* | |
227 | * wait for more than 10us to release phy g_rst and | |
228 | * btnrst | |
229 | */ | |
230 | if (!assert) | |
231 | udelay(10); | |
232 | break; | |
233 | ||
234 | case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: | |
235 | case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ | |
942b4c10 GG |
236 | case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ |
237 | case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ | |
238 | case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ | |
c979dbf5 AS |
239 | case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ |
240 | case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ | |
241 | value = assert ? 0 : bit; | |
242 | break; | |
243 | } | |
244 | ||
245 | return imx7_reset_update(imx7src, id, value); | |
246 | } | |
247 | ||
248 | static int imx8mq_reset_assert(struct reset_controller_dev *rcdev, | |
249 | unsigned long id) | |
250 | { | |
251 | return imx8mq_reset_set(rcdev, id, true); | |
252 | } | |
253 | ||
254 | static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev, | |
255 | unsigned long id) | |
256 | { | |
257 | return imx8mq_reset_set(rcdev, id, false); | |
258 | } | |
259 | ||
260 | static const struct imx7_src_variant variant_imx8mq = { | |
261 | .signals = imx8mq_src_signals, | |
262 | .signals_num = ARRAY_SIZE(imx8mq_src_signals), | |
263 | .ops = { | |
264 | .assert = imx8mq_reset_assert, | |
265 | .deassert = imx8mq_reset_deassert, | |
266 | }, | |
267 | }; | |
268 | ||
e08672c0 AH |
269 | static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = { |
270 | [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, | |
271 | [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, | |
272 | [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, | |
273 | [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, | |
274 | [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, | |
275 | [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, | |
276 | [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, | |
277 | [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, | |
278 | [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, | |
279 | [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, | |
280 | [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, | |
281 | [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, | |
282 | [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, | |
283 | [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, | |
284 | [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, | |
285 | [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, | |
286 | [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, | |
287 | [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, | |
288 | [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) }, | |
289 | [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, | |
290 | [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, | |
291 | [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) }, | |
292 | [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) }, | |
293 | [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) }, | |
294 | [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) }, | |
295 | [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, | |
296 | [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, | |
297 | [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, | |
298 | [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, | |
299 | [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) }, | |
300 | [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) }, | |
301 | [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) }, | |
302 | [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, | |
303 | [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, | |
304 | [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) }, | |
305 | [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) }, | |
306 | [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) }, | |
307 | [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) }, | |
308 | }; | |
309 | ||
310 | static int imx8mp_reset_set(struct reset_controller_dev *rcdev, | |
311 | unsigned long id, bool assert) | |
312 | { | |
313 | struct imx7_src *imx7src = to_imx7_src(rcdev); | |
314 | const unsigned int bit = imx7src->signals[id].bit; | |
315 | unsigned int value = assert ? bit : 0; | |
316 | ||
317 | switch (id) { | |
318 | case IMX8MP_RESET_PCIEPHY: | |
319 | /* | |
320 | * wait for more than 10us to release phy g_rst and | |
321 | * btnrst | |
322 | */ | |
323 | if (!assert) | |
324 | udelay(10); | |
325 | break; | |
326 | ||
327 | case IMX8MP_RESET_PCIE_CTRL_APPS_EN: | |
328 | value = assert ? 0 : bit; | |
329 | break; | |
330 | } | |
331 | ||
332 | return imx7_reset_update(imx7src, id, value); | |
333 | } | |
334 | ||
335 | static int imx8mp_reset_assert(struct reset_controller_dev *rcdev, | |
336 | unsigned long id) | |
337 | { | |
338 | return imx8mp_reset_set(rcdev, id, true); | |
339 | } | |
340 | ||
341 | static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev, | |
342 | unsigned long id) | |
343 | { | |
344 | return imx8mp_reset_set(rcdev, id, false); | |
345 | } | |
346 | ||
347 | static const struct imx7_src_variant variant_imx8mp = { | |
348 | .signals = imx8mp_src_signals, | |
349 | .signals_num = ARRAY_SIZE(imx8mp_src_signals), | |
350 | .ops = { | |
351 | .assert = imx8mp_reset_assert, | |
352 | .deassert = imx8mp_reset_deassert, | |
353 | }, | |
354 | }; | |
355 | ||
abf97755 AS |
356 | static int imx7_reset_probe(struct platform_device *pdev) |
357 | { | |
358 | struct imx7_src *imx7src; | |
359 | struct device *dev = &pdev->dev; | |
360 | struct regmap_config config = { .name = "src" }; | |
10590358 | 361 | const struct imx7_src_variant *variant = of_device_get_match_data(dev); |
abf97755 AS |
362 | |
363 | imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL); | |
364 | if (!imx7src) | |
365 | return -ENOMEM; | |
366 | ||
10590358 | 367 | imx7src->signals = variant->signals; |
abf97755 AS |
368 | imx7src->regmap = syscon_node_to_regmap(dev->of_node); |
369 | if (IS_ERR(imx7src->regmap)) { | |
370 | dev_err(dev, "Unable to get imx7-src regmap"); | |
371 | return PTR_ERR(imx7src->regmap); | |
372 | } | |
373 | regmap_attach_dev(dev, imx7src->regmap, &config); | |
374 | ||
375 | imx7src->rcdev.owner = THIS_MODULE; | |
10590358 AS |
376 | imx7src->rcdev.nr_resets = variant->signals_num; |
377 | imx7src->rcdev.ops = &variant->ops; | |
abf97755 AS |
378 | imx7src->rcdev.of_node = dev->of_node; |
379 | ||
380 | return devm_reset_controller_register(dev, &imx7src->rcdev); | |
381 | } | |
382 | ||
383 | static const struct of_device_id imx7_reset_dt_ids[] = { | |
10590358 | 384 | { .compatible = "fsl,imx7d-src", .data = &variant_imx7 }, |
c979dbf5 | 385 | { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq }, |
e08672c0 | 386 | { .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp }, |
abf97755 AS |
387 | { /* sentinel */ }, |
388 | }; | |
a442abbb | 389 | MODULE_DEVICE_TABLE(of, imx7_reset_dt_ids); |
abf97755 AS |
390 | |
391 | static struct platform_driver imx7_reset_driver = { | |
392 | .probe = imx7_reset_probe, | |
393 | .driver = { | |
394 | .name = KBUILD_MODNAME, | |
395 | .of_match_table = imx7_reset_dt_ids, | |
396 | }, | |
397 | }; | |
a442abbb AH |
398 | module_platform_driver(imx7_reset_driver); |
399 | ||
400 | MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>"); | |
401 | MODULE_DESCRIPTION("NXP i.MX7 reset driver"); | |
402 | MODULE_LICENSE("GPL v2"); |