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affae2bf WD |
1 | /* |
2 | * (C) Copyright 2002 SIXNET, dge@sixnetio.com. | |
3 | * | |
ec4c544b WD |
4 | * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> |
5 | * Stephan Linz <linz@li-pro.net> | |
6 | * | |
affae2bf WD |
7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
ec4c544b WD |
27 | * Date & Time support for DS1306 RTC using SPI: |
28 | * | |
29 | * - SXNI855T: it uses its own soft SPI here in this file | |
30 | * - all other: use the external spi_xfer() function | |
31 | * (see include/spi.h) | |
affae2bf WD |
32 | */ |
33 | ||
34 | #include <common.h> | |
35 | #include <command.h> | |
36 | #include <rtc.h> | |
ec4c544b | 37 | #include <spi.h> |
affae2bf | 38 | |
871c18dd | 39 | #if defined(CONFIG_CMD_DATE) |
affae2bf | 40 | |
ec4c544b WD |
41 | #define RTC_SECONDS 0x00 |
42 | #define RTC_MINUTES 0x01 | |
43 | #define RTC_HOURS 0x02 | |
44 | #define RTC_DAY_OF_WEEK 0x03 | |
45 | #define RTC_DATE_OF_MONTH 0x04 | |
46 | #define RTC_MONTH 0x05 | |
47 | #define RTC_YEAR 0x06 | |
48 | ||
49 | #define RTC_SECONDS_ALARM0 0x07 | |
50 | #define RTC_MINUTES_ALARM0 0x08 | |
51 | #define RTC_HOURS_ALARM0 0x09 | |
52 | #define RTC_DAY_OF_WEEK_ALARM0 0x0a | |
53 | ||
54 | #define RTC_SECONDS_ALARM1 0x0b | |
55 | #define RTC_MINUTES_ALARM1 0x0c | |
56 | #define RTC_HOURS_ALARM1 0x0d | |
57 | #define RTC_DAY_OF_WEEK_ALARM1 0x0e | |
58 | ||
59 | #define RTC_CONTROL 0x0f | |
60 | #define RTC_STATUS 0x10 | |
61 | #define RTC_TRICKLE_CHARGER 0x11 | |
62 | ||
63 | #define RTC_USER_RAM_BASE 0x20 | |
64 | ||
ec4c544b WD |
65 | static unsigned int bin2bcd (unsigned int n); |
66 | static unsigned char bcd2bin (unsigned char c); | |
ec4c544b | 67 | |
ec4c544b WD |
68 | /* ************************************************************************* */ |
69 | #ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ | |
70 | ||
71 | static void soft_spi_send (unsigned char n); | |
72 | static unsigned char soft_spi_read (void); | |
73 | static void init_spi (void); | |
affae2bf WD |
74 | |
75 | /*----------------------------------------------------------------------- | |
76 | * Definitions | |
77 | */ | |
78 | ||
79 | #define PB_SPISCK 0x00000002 /* PB 30 */ | |
80 | #define PB_SPIMOSI 0x00000004 /* PB 29 */ | |
81 | #define PB_SPIMISO 0x00000008 /* PB 28 */ | |
82 | #define PB_SPI_CE 0x00010000 /* PB 15 */ | |
83 | ||
84 | /* ------------------------------------------------------------------------- */ | |
85 | ||
86 | /* read clock time from DS1306 and return it in *tmp */ | |
b73a19e1 | 87 | int rtc_get (struct rtc_time *tmp) |
affae2bf | 88 | { |
ec4c544b WD |
89 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
90 | unsigned char spi_byte; /* Data Byte */ | |
91 | ||
92 | init_spi (); /* set port B for software SPI */ | |
93 | ||
94 | /* Now we can enable the DS1306 RTC */ | |
95 | immap->im_cpm.cp_pbdat |= PB_SPI_CE; | |
96 | udelay (10); | |
97 | ||
98 | /* Shift out the address (0) of the time in the Clock Chip */ | |
99 | soft_spi_send (0); | |
100 | ||
101 | /* Put the clock readings into the rtc_time structure */ | |
102 | tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ | |
103 | tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ | |
104 | ||
105 | /* Hours are trickier */ | |
106 | spi_byte = soft_spi_read (); /* Read Hours into temporary value */ | |
107 | if (spi_byte & 0x40) { | |
108 | /* 12 hour mode bit is set (time is in 1-12 format) */ | |
109 | if (spi_byte & 0x20) { | |
110 | /* since PM we add 11 to get 0-23 for hours */ | |
111 | tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; | |
112 | } else { | |
113 | /* since AM we subtract 1 to get 0-23 for hours */ | |
114 | tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; | |
115 | } | |
116 | } else { | |
117 | /* Otherwise, 0-23 hour format */ | |
118 | tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); | |
119 | } | |
affae2bf | 120 | |
ec4c544b WD |
121 | soft_spi_read (); /* Read and discard Day of week */ |
122 | tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ | |
123 | tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ | |
affae2bf | 124 | |
ec4c544b WD |
125 | /* Read Year and convert to this century */ |
126 | tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; | |
affae2bf | 127 | |
ec4c544b WD |
128 | /* Now we can disable the DS1306 RTC */ |
129 | immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ | |
130 | udelay (10); | |
affae2bf | 131 | |
ec4c544b | 132 | GregorianDay (tmp); /* Determine the day of week */ |
affae2bf | 133 | |
ec4c544b WD |
134 | debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
135 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, | |
136 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); | |
b73a19e1 YT |
137 | |
138 | return 0; | |
ec4c544b WD |
139 | } |
140 | ||
141 | /* ------------------------------------------------------------------------- */ | |
142 | ||
143 | /* set clock time in DS1306 RTC and in MPC8xx RTC */ | |
144 | void rtc_set (struct rtc_time *tmp) | |
145 | { | |
146 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
147 | ||
148 | init_spi (); /* set port B for software SPI */ | |
149 | ||
150 | /* Now we can enable the DS1306 RTC */ | |
151 | immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ | |
152 | udelay (10); | |
153 | ||
154 | /* First disable write protect in the clock chip control register */ | |
155 | soft_spi_send (0x8F); /* send address of the control register */ | |
156 | soft_spi_send (0x00); /* send control register contents */ | |
157 | ||
158 | /* Now disable the DS1306 to terminate the write */ | |
159 | immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; | |
160 | udelay (10); | |
161 | ||
162 | /* Now enable the DS1306 to initiate a new write */ | |
163 | immap->im_cpm.cp_pbdat |= PB_SPI_CE; | |
164 | udelay (10); | |
165 | ||
166 | /* Next, send the address of the clock time write registers */ | |
167 | soft_spi_send (0x80); /* send address of the first time register */ | |
168 | ||
169 | /* Use Burst Mode to send all of the time data to the clock */ | |
170 | bin2bcd (tmp->tm_sec); | |
171 | soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ | |
172 | soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ | |
173 | soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ | |
174 | soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ | |
175 | soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ | |
176 | soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ | |
177 | soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ | |
178 | ||
179 | /* Now we can disable the Clock chip to terminate the burst write */ | |
180 | immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ | |
181 | udelay (10); | |
182 | ||
183 | /* Now we can enable the Clock chip to initiate a new write */ | |
184 | immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ | |
185 | udelay (10); | |
186 | ||
187 | /* First we Enable write protect in the clock chip control register */ | |
188 | soft_spi_send (0x8F); /* send address of the control register */ | |
189 | soft_spi_send (0x40); /* send out Control Register contents */ | |
190 | ||
191 | /* Now disable the DS1306 */ | |
192 | immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ | |
193 | udelay (10); | |
194 | ||
195 | /* Set standard MPC8xx clock to the same time so Linux will | |
196 | * see the time even if it doesn't have a DS1306 clock driver. | |
197 | * This helps with experimenting with standard kernels. | |
198 | */ | |
199 | { | |
200 | ulong tim; | |
201 | ||
202 | tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, | |
203 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); | |
204 | ||
205 | immap->im_sitk.sitk_rtck = KAPWR_KEY; | |
206 | immap->im_sit.sit_rtc = tim; | |
affae2bf | 207 | } |
affae2bf | 208 | |
ec4c544b WD |
209 | debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
210 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, | |
211 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); | |
212 | } | |
affae2bf | 213 | |
ec4c544b | 214 | /* ------------------------------------------------------------------------- */ |
affae2bf | 215 | |
ec4c544b WD |
216 | /* Initialize Port B for software SPI */ |
217 | static void init_spi (void) | |
218 | { | |
219 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
affae2bf | 220 | |
ec4c544b WD |
221 | /* Force output pins to begin at logic 0 */ |
222 | immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); | |
affae2bf | 223 | |
ec4c544b WD |
224 | /* Set these 3 signals as outputs */ |
225 | immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); | |
226 | ||
227 | immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ | |
228 | udelay (10); | |
affae2bf WD |
229 | } |
230 | ||
231 | /* ------------------------------------------------------------------------- */ | |
232 | ||
ec4c544b WD |
233 | /* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ |
234 | static void soft_spi_send (unsigned char n) | |
affae2bf | 235 | { |
ec4c544b WD |
236 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
237 | unsigned char bitpos; /* bit position to receive */ | |
238 | unsigned char i; /* Loop Control */ | |
239 | ||
240 | /* bit position to send, start with most significant bit */ | |
241 | bitpos = 0x80; | |
242 | ||
243 | /* Send 8 bits to software SPI */ | |
244 | for (i = 0; i < 8; i++) { /* Loop for 8 bits */ | |
245 | immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ | |
246 | ||
247 | if (n & bitpos) | |
248 | immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ | |
249 | else | |
250 | immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ | |
251 | udelay (10); | |
252 | ||
253 | immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ | |
254 | udelay (10); | |
255 | ||
256 | bitpos >>= 1; /* Shift for next bit position */ | |
257 | } | |
affae2bf WD |
258 | } |
259 | ||
260 | /* ------------------------------------------------------------------------- */ | |
261 | ||
ec4c544b WD |
262 | /* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ |
263 | static unsigned char soft_spi_read (void) | |
affae2bf | 264 | { |
ec4c544b WD |
265 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
266 | ||
267 | unsigned char spi_byte = 0; /* Return value, assume success */ | |
268 | unsigned char bitpos; /* bit position to receive */ | |
269 | unsigned char i; /* Loop Control */ | |
270 | ||
271 | /* bit position to receive, start with most significant bit */ | |
272 | bitpos = 0x80; | |
273 | ||
274 | /* Read 8 bits here */ | |
275 | for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ | |
276 | immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ | |
277 | udelay (10); | |
278 | if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ | |
279 | spi_byte |= bitpos; /* Set data accordingly */ | |
280 | immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ | |
281 | udelay (10); | |
282 | bitpos >>= 1; /* Shift for next bit position */ | |
283 | } | |
284 | ||
285 | return spi_byte; /* Return the byte read */ | |
affae2bf WD |
286 | } |
287 | ||
288 | /* ------------------------------------------------------------------------- */ | |
289 | ||
ec4c544b | 290 | void rtc_reset (void) |
affae2bf | 291 | { |
ec4c544b WD |
292 | return; /* nothing to do */ |
293 | } | |
294 | ||
295 | #else /* not CONFIG_SXNI855T */ | |
296 | /* ************************************************************************* */ | |
297 | ||
3f85ce27 WD |
298 | static unsigned char rtc_read (unsigned char reg); |
299 | static void rtc_write (unsigned char reg, unsigned char val); | |
300 | ||
d255bb0e HS |
301 | static struct spi_slave *slave; |
302 | ||
ec4c544b | 303 | /* read clock time from DS1306 and return it in *tmp */ |
b73a19e1 | 304 | int rtc_get (struct rtc_time *tmp) |
ec4c544b WD |
305 | { |
306 | unsigned char sec, min, hour, mday, wday, mon, year; | |
307 | ||
d255bb0e HS |
308 | /* |
309 | * Assuming Vcc = 2.0V (lowest speed) | |
310 | * | |
311 | * REVISIT: If we add an rtc_init() function we can do this | |
312 | * step just once. | |
313 | */ | |
314 | if (!slave) { | |
315 | slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, | |
316 | SPI_MODE_3 | SPI_CS_HIGH); | |
317 | if (!slave) | |
318 | return; | |
319 | } | |
320 | ||
321 | if (spi_claim_bus(slave)) | |
322 | return; | |
323 | ||
ec4c544b WD |
324 | sec = rtc_read (RTC_SECONDS); |
325 | min = rtc_read (RTC_MINUTES); | |
326 | hour = rtc_read (RTC_HOURS); | |
327 | mday = rtc_read (RTC_DATE_OF_MONTH); | |
328 | wday = rtc_read (RTC_DAY_OF_WEEK); | |
329 | mon = rtc_read (RTC_MONTH); | |
330 | year = rtc_read (RTC_YEAR); | |
331 | ||
d255bb0e HS |
332 | spi_release_bus(slave); |
333 | ||
ec4c544b WD |
334 | debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " |
335 | "hr: %02x min: %02x sec: %02x\n", | |
336 | year, mon, mday, wday, hour, min, sec); | |
337 | debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", | |
338 | rtc_read (RTC_DAY_OF_WEEK_ALARM0), | |
339 | rtc_read (RTC_HOURS_ALARM0), | |
340 | rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); | |
341 | debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", | |
342 | rtc_read (RTC_DAY_OF_WEEK_ALARM1), | |
343 | rtc_read (RTC_HOURS_ALARM1), | |
344 | rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); | |
345 | ||
346 | tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ | |
347 | tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ | |
348 | ||
349 | /* convert Hours */ | |
350 | tmp->tm_hour = (hour & 0x40) | |
351 | ? ((hour & 0x20) /* 12 hour mode */ | |
352 | ? bcd2bin (hour & 0x1F) + 11 /* PM */ | |
353 | : bcd2bin (hour & 0x1F) - 1 /* AM */ | |
354 | ) | |
355 | : bcd2bin (hour & 0x3F); /* 24 hour mode */ | |
356 | ||
357 | tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ | |
358 | tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ | |
359 | tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ | |
360 | tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ | |
361 | tmp->tm_yday = 0; | |
362 | tmp->tm_isdst = 0; | |
363 | ||
364 | debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", | |
365 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, | |
366 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); | |
b73a19e1 YT |
367 | |
368 | return 0; | |
affae2bf WD |
369 | } |
370 | ||
371 | /* ------------------------------------------------------------------------- */ | |
372 | ||
ec4c544b WD |
373 | /* set clock time from *tmp in DS1306 RTC */ |
374 | void rtc_set (struct rtc_time *tmp) | |
affae2bf | 375 | { |
d255bb0e HS |
376 | /* Assuming Vcc = 2.0V (lowest speed) */ |
377 | if (!slave) { | |
378 | slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, | |
379 | SPI_MODE_3 | SPI_CS_HIGH); | |
380 | if (!slave) | |
381 | return; | |
382 | } | |
383 | ||
384 | if (spi_claim_bus(slave)) | |
385 | return; | |
386 | ||
ec4c544b WD |
387 | debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
388 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, | |
389 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); | |
390 | ||
ec4c544b | 391 | rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); |
da4849fb WD |
392 | rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); |
393 | rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); | |
394 | rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); | |
395 | rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); | |
396 | rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); | |
397 | rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); | |
d255bb0e HS |
398 | |
399 | spi_release_bus(slave); | |
affae2bf WD |
400 | } |
401 | ||
402 | /* ------------------------------------------------------------------------- */ | |
403 | ||
ec4c544b WD |
404 | /* reset the DS1306 */ |
405 | void rtc_reset (void) | |
406 | { | |
d255bb0e HS |
407 | /* Assuming Vcc = 2.0V (lowest speed) */ |
408 | if (!slave) { | |
409 | slave = spi_setup_slave(0, CFG_SPI_RTC_DEVID, 600000, | |
410 | SPI_MODE_3 | SPI_CS_HIGH); | |
411 | if (!slave) | |
412 | return; | |
413 | } | |
414 | ||
415 | if (spi_claim_bus(slave)) | |
416 | return; | |
417 | ||
ec4c544b WD |
418 | /* clear the control register */ |
419 | rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ | |
420 | rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ | |
421 | ||
422 | /* reset all alarms */ | |
423 | rtc_write (RTC_SECONDS_ALARM0, 0x00); | |
424 | rtc_write (RTC_SECONDS_ALARM1, 0x00); | |
425 | rtc_write (RTC_MINUTES_ALARM0, 0x00); | |
426 | rtc_write (RTC_MINUTES_ALARM1, 0x00); | |
427 | rtc_write (RTC_HOURS_ALARM0, 0x00); | |
428 | rtc_write (RTC_HOURS_ALARM1, 0x00); | |
429 | rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); | |
430 | rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); | |
d255bb0e HS |
431 | |
432 | spi_release_bus(slave); | |
ec4c544b WD |
433 | } |
434 | ||
435 | /* ------------------------------------------------------------------------- */ | |
affae2bf | 436 | |
ec4c544b WD |
437 | static unsigned char rtc_read (unsigned char reg) |
438 | { | |
d255bb0e | 439 | int ret; |
affae2bf | 440 | |
d255bb0e HS |
441 | ret = spi_w8r8(slave, reg); |
442 | return ret < 0 ? 0 : ret; | |
affae2bf WD |
443 | } |
444 | ||
445 | /* ------------------------------------------------------------------------- */ | |
446 | ||
ec4c544b | 447 | static void rtc_write (unsigned char reg, unsigned char val) |
affae2bf | 448 | { |
ec4c544b WD |
449 | unsigned char dout[2]; /* SPI Output Data Bytes */ |
450 | unsigned char din[2]; /* SPI Input Data Bytes */ | |
affae2bf | 451 | |
ec4c544b WD |
452 | dout[0] = 0x80 | reg; |
453 | dout[1] = val; | |
affae2bf | 454 | |
d255bb0e | 455 | spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); |
ec4c544b | 456 | } |
affae2bf | 457 | |
ec4c544b | 458 | #endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ |
affae2bf | 459 | |
ec4c544b | 460 | /* ------------------------------------------------------------------------- */ |
affae2bf | 461 | |
ec4c544b WD |
462 | static unsigned char bcd2bin (unsigned char n) |
463 | { | |
464 | return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); | |
affae2bf WD |
465 | } |
466 | ||
467 | /* ------------------------------------------------------------------------- */ | |
468 | ||
ec4c544b | 469 | static unsigned int bin2bcd (unsigned int n) |
affae2bf | 470 | { |
ec4c544b | 471 | return (((n / 10) << 4) | (n % 10)); |
affae2bf | 472 | } |
affae2bf WD |
473 | /* ------------------------------------------------------------------------- */ |
474 | ||
475 | #endif |