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7f3923a1 CV |
1 | /* |
2 | * An SPI driver for the Philips PCF2123 RTC | |
3 | * Copyright 2009 Cyber Switching, Inc. | |
4 | * | |
5 | * Author: Chris Verges <chrisv@cyberswitching.com> | |
6 | * Maintainers: http://www.cyberswitching.com | |
7 | * | |
8 | * based on the RS5C348 driver in this same directory. | |
9 | * | |
10 | * Thanks to Christian Pellegrin <chripell@fsfe.org> for | |
11 | * the sysfs contributions to this driver. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
17 | * Please note that the CS is active high, so platform data | |
18 | * should look something like: | |
19 | * | |
20 | * static struct spi_board_info ek_spi_devices[] = { | |
369015fb SK |
21 | * ... |
22 | * { | |
23 | * .modalias = "rtc-pcf2123", | |
24 | * .chip_select = 1, | |
25 | * .controller_data = (void *)AT91_PIN_PA10, | |
7f3923a1 CV |
26 | * .max_speed_hz = 1000 * 1000, |
27 | * .mode = SPI_CS_HIGH, | |
28 | * .bus_num = 0, | |
29 | * }, | |
30 | * ... | |
31 | *}; | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/bcd.h> | |
36 | #include <linux/delay.h> | |
37 | #include <linux/device.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/kernel.h> | |
3fc70077 | 41 | #include <linux/of.h> |
7f3923a1 | 42 | #include <linux/string.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
7f3923a1 CV |
44 | #include <linux/rtc.h> |
45 | #include <linux/spi/spi.h> | |
2113852b | 46 | #include <linux/module.h> |
5ed12f12 | 47 | #include <linux/sysfs.h> |
7f3923a1 | 48 | |
f3d2570a | 49 | #define DRV_VERSION "0.6" |
7f3923a1 | 50 | |
245cb74b | 51 | /* REGISTERS */ |
7f3923a1 CV |
52 | #define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */ |
53 | #define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */ | |
54 | #define PCF2123_REG_SC (0x02) /* datetime */ | |
55 | #define PCF2123_REG_MN (0x03) | |
56 | #define PCF2123_REG_HR (0x04) | |
57 | #define PCF2123_REG_DM (0x05) | |
58 | #define PCF2123_REG_DW (0x06) | |
59 | #define PCF2123_REG_MO (0x07) | |
60 | #define PCF2123_REG_YR (0x08) | |
245cb74b JC |
61 | #define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */ |
62 | #define PCF2123_REG_ALRM_HR (0x0a) | |
63 | #define PCF2123_REG_ALRM_DM (0x0b) | |
64 | #define PCF2123_REG_ALRM_DW (0x0c) | |
65 | #define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */ | |
66 | #define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */ | |
67 | #define PCF2123_REG_CTDWN_TMR (0x0f) | |
68 | ||
69 | /* PCF2123_REG_CTRL1 BITS */ | |
70 | #define CTRL1_CLEAR (0) /* Clear */ | |
71 | #define CTRL1_CORR_INT BIT(1) /* Correction irq enable */ | |
72 | #define CTRL1_12_HOUR BIT(2) /* 12 hour time */ | |
73 | #define CTRL1_SW_RESET (BIT(3) | BIT(4) | BIT(6)) /* Software reset */ | |
74 | #define CTRL1_STOP BIT(5) /* Stop the clock */ | |
75 | #define CTRL1_EXT_TEST BIT(7) /* External clock test mode */ | |
76 | ||
77 | /* PCF2123_REG_CTRL2 BITS */ | |
78 | #define CTRL2_TIE BIT(0) /* Countdown timer irq enable */ | |
79 | #define CTRL2_AIE BIT(1) /* Alarm irq enable */ | |
80 | #define CTRL2_TF BIT(2) /* Countdown timer flag */ | |
81 | #define CTRL2_AF BIT(3) /* Alarm flag */ | |
82 | #define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */ | |
83 | #define CTRL2_MSF BIT(5) /* Minute or second irq flag */ | |
84 | #define CTRL2_SI BIT(6) /* Second irq enable */ | |
85 | #define CTRL2_MI BIT(7) /* Minute irq enable */ | |
86 | ||
87 | /* PCF2123_REG_SC BITS */ | |
88 | #define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */ | |
89 | ||
90 | /* PCF2123_REG_ALRM_XX BITS */ | |
91 | #define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */ | |
92 | ||
93 | /* PCF2123_REG_TMR_CLKOUT BITS */ | |
94 | #define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */ | |
95 | #define CD_TMR_64HZ (1) /* 64 Hz countdown timer */ | |
96 | #define CD_TMR_1HZ (2) /* 1 Hz countdown timer */ | |
97 | #define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */ | |
98 | #define CD_TMR_TE BIT(3) /* Countdown timer enable */ | |
99 | ||
100 | /* PCF2123_REG_OFFSET BITS */ | |
101 | #define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */ | |
102 | #define OFFSET_COARSE BIT(7) /* Coarse mode offset */ | |
103 | ||
104 | /* READ/WRITE ADDRESS BITS */ | |
105 | #define PCF2123_WRITE BIT(4) | |
106 | #define PCF2123_READ (BIT(4) | BIT(7)) | |
7f3923a1 | 107 | |
7f3923a1 CV |
108 | |
109 | static struct spi_driver pcf2123_driver; | |
110 | ||
111 | struct pcf2123_sysfs_reg { | |
f3d2570a | 112 | struct device_attribute attr; |
7f3923a1 CV |
113 | char name[2]; |
114 | }; | |
115 | ||
116 | struct pcf2123_plat_data { | |
117 | struct rtc_device *rtc; | |
118 | struct pcf2123_sysfs_reg regs[16]; | |
119 | }; | |
120 | ||
121 | /* | |
122 | * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select | |
123 | * is released properly after an SPI write. This function should be | |
124 | * called after EVERY read/write call over SPI. | |
125 | */ | |
126 | static inline void pcf2123_delay_trec(void) | |
127 | { | |
128 | ndelay(30); | |
129 | } | |
130 | ||
66c056d6 JC |
131 | static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size) |
132 | { | |
133 | struct spi_device *spi = to_spi_device(dev); | |
134 | int ret; | |
135 | ||
136 | reg |= PCF2123_READ; | |
137 | ret = spi_write_then_read(spi, ®, 1, rxbuf, size); | |
138 | pcf2123_delay_trec(); | |
139 | ||
140 | return ret; | |
141 | } | |
142 | ||
809b453b JC |
143 | static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size) |
144 | { | |
145 | struct spi_device *spi = to_spi_device(dev); | |
146 | int ret; | |
147 | ||
148 | txbuf[0] |= PCF2123_WRITE; | |
149 | ret = spi_write(spi, txbuf, size); | |
150 | pcf2123_delay_trec(); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val) | |
156 | { | |
157 | u8 txbuf[2]; | |
158 | ||
159 | txbuf[0] = reg; | |
160 | txbuf[1] = val; | |
161 | return pcf2123_write(dev, txbuf, sizeof(txbuf)); | |
162 | } | |
163 | ||
7f3923a1 CV |
164 | static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr, |
165 | char *buffer) | |
166 | { | |
f3d2570a | 167 | struct pcf2123_sysfs_reg *r; |
66c056d6 | 168 | u8 rxbuf[1]; |
f3d2570a | 169 | unsigned long reg; |
7f3923a1 CV |
170 | int ret; |
171 | ||
f3d2570a CV |
172 | r = container_of(attr, struct pcf2123_sysfs_reg, attr); |
173 | ||
4c5591c1 JH |
174 | ret = kstrtoul(r->name, 16, ®); |
175 | if (ret) | |
176 | return ret; | |
f3d2570a | 177 | |
66c056d6 | 178 | ret = pcf2123_read(dev, reg, rxbuf, 1); |
7f3923a1 | 179 | if (ret < 0) |
f3d2570a | 180 | return -EIO; |
66c056d6 | 181 | |
f3d2570a | 182 | return sprintf(buffer, "0x%x\n", rxbuf[0]); |
7f3923a1 CV |
183 | } |
184 | ||
185 | static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr, | |
186 | const char *buffer, size_t count) { | |
f3d2570a | 187 | struct pcf2123_sysfs_reg *r; |
f3d2570a CV |
188 | unsigned long reg; |
189 | unsigned long val; | |
190 | ||
7f3923a1 CV |
191 | int ret; |
192 | ||
f3d2570a CV |
193 | r = container_of(attr, struct pcf2123_sysfs_reg, attr); |
194 | ||
4c5591c1 JH |
195 | ret = kstrtoul(r->name, 16, ®); |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | ret = kstrtoul(buffer, 10, &val); | |
200 | if (ret) | |
201 | return ret; | |
f3d2570a | 202 | |
809b453b | 203 | pcf2123_write_reg(dev, reg, val); |
7f3923a1 CV |
204 | if (ret < 0) |
205 | return -EIO; | |
7f3923a1 CV |
206 | return count; |
207 | } | |
208 | ||
209 | static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm) | |
210 | { | |
66c056d6 | 211 | u8 rxbuf[7]; |
7f3923a1 CV |
212 | int ret; |
213 | ||
66c056d6 | 214 | ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf)); |
7f3923a1 CV |
215 | if (ret < 0) |
216 | return ret; | |
7f3923a1 CV |
217 | |
218 | tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F); | |
219 | tm->tm_min = bcd2bin(rxbuf[1] & 0x7F); | |
220 | tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */ | |
221 | tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F); | |
222 | tm->tm_wday = rxbuf[4] & 0x07; | |
223 | tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */ | |
224 | tm->tm_year = bcd2bin(rxbuf[6]); | |
225 | if (tm->tm_year < 70) | |
226 | tm->tm_year += 100; /* assume we are in 1970...2069 */ | |
227 | ||
228 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
229 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
230 | __func__, | |
231 | tm->tm_sec, tm->tm_min, tm->tm_hour, | |
232 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
233 | ||
821f51c4 | 234 | return rtc_valid_tm(tm); |
7f3923a1 CV |
235 | } |
236 | ||
237 | static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm) | |
238 | { | |
7f3923a1 CV |
239 | u8 txbuf[8]; |
240 | int ret; | |
241 | ||
242 | dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, " | |
243 | "mday=%d, mon=%d, year=%d, wday=%d\n", | |
244 | __func__, | |
245 | tm->tm_sec, tm->tm_min, tm->tm_hour, | |
246 | tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); | |
247 | ||
248 | /* Stop the counter first */ | |
809b453b | 249 | ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); |
7f3923a1 CV |
250 | if (ret < 0) |
251 | return ret; | |
7f3923a1 CV |
252 | |
253 | /* Set the new time */ | |
809b453b | 254 | txbuf[0] = PCF2123_REG_SC; |
7f3923a1 CV |
255 | txbuf[1] = bin2bcd(tm->tm_sec & 0x7F); |
256 | txbuf[2] = bin2bcd(tm->tm_min & 0x7F); | |
257 | txbuf[3] = bin2bcd(tm->tm_hour & 0x3F); | |
258 | txbuf[4] = bin2bcd(tm->tm_mday & 0x3F); | |
259 | txbuf[5] = tm->tm_wday & 0x07; | |
260 | txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */ | |
261 | txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100); | |
262 | ||
809b453b | 263 | ret = pcf2123_write(dev, txbuf, sizeof(txbuf)); |
7f3923a1 CV |
264 | if (ret < 0) |
265 | return ret; | |
7f3923a1 CV |
266 | |
267 | /* Start the counter */ | |
809b453b | 268 | ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); |
7f3923a1 CV |
269 | if (ret < 0) |
270 | return ret; | |
7f3923a1 CV |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
1e094b94 JC |
275 | static int pcf2123_reset(struct device *dev) |
276 | { | |
277 | int ret; | |
278 | u8 rxbuf[2]; | |
279 | ||
280 | ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET); | |
281 | if (ret < 0) | |
282 | return ret; | |
283 | ||
284 | /* Stop the counter */ | |
285 | dev_dbg(dev, "stopping RTC\n"); | |
286 | ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP); | |
287 | if (ret < 0) | |
288 | return ret; | |
289 | ||
290 | /* See if the counter was actually stopped */ | |
291 | dev_dbg(dev, "checking for presence of RTC\n"); | |
292 | ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf)); | |
293 | if (ret < 0) | |
294 | return ret; | |
295 | ||
296 | dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n", | |
297 | rxbuf[0], rxbuf[1]); | |
298 | if (!(rxbuf[0] & CTRL1_STOP)) | |
299 | return -ENODEV; | |
300 | ||
301 | /* Start the counter */ | |
302 | ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR); | |
303 | if (ret < 0) | |
304 | return ret; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
7f3923a1 CV |
309 | static const struct rtc_class_ops pcf2123_rtc_ops = { |
310 | .read_time = pcf2123_rtc_read_time, | |
311 | .set_time = pcf2123_rtc_set_time, | |
312 | }; | |
313 | ||
5a167f45 | 314 | static int pcf2123_probe(struct spi_device *spi) |
7f3923a1 CV |
315 | { |
316 | struct rtc_device *rtc; | |
317 | struct pcf2123_plat_data *pdata; | |
7f3923a1 CV |
318 | int ret, i; |
319 | ||
dd48ccc4 JH |
320 | pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data), |
321 | GFP_KERNEL); | |
7f3923a1 CV |
322 | if (!pdata) |
323 | return -ENOMEM; | |
324 | spi->dev.platform_data = pdata; | |
325 | ||
1e094b94 JC |
326 | ret = pcf2123_reset(&spi->dev); |
327 | if (ret < 0) { | |
7f3923a1 CV |
328 | dev_err(&spi->dev, "chip not found\n"); |
329 | goto kfree_exit; | |
330 | } | |
331 | ||
332 | dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n"); | |
333 | dev_info(&spi->dev, "spiclk %u KHz.\n", | |
334 | (spi->max_speed_hz + 500) / 1000); | |
335 | ||
7f3923a1 | 336 | /* Finalize the initialization */ |
dd48ccc4 | 337 | rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name, |
7f3923a1 CV |
338 | &pcf2123_rtc_ops, THIS_MODULE); |
339 | ||
340 | if (IS_ERR(rtc)) { | |
341 | dev_err(&spi->dev, "failed to register.\n"); | |
342 | ret = PTR_ERR(rtc); | |
343 | goto kfree_exit; | |
344 | } | |
345 | ||
346 | pdata->rtc = rtc; | |
347 | ||
348 | for (i = 0; i < 16; i++) { | |
5ed12f12 | 349 | sysfs_attr_init(&pdata->regs[i].attr.attr); |
7f3923a1 CV |
350 | sprintf(pdata->regs[i].name, "%1x", i); |
351 | pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR; | |
352 | pdata->regs[i].attr.attr.name = pdata->regs[i].name; | |
353 | pdata->regs[i].attr.show = pcf2123_show; | |
354 | pdata->regs[i].attr.store = pcf2123_store; | |
355 | ret = device_create_file(&spi->dev, &pdata->regs[i].attr); | |
356 | if (ret) { | |
357 | dev_err(&spi->dev, "Unable to create sysfs %s\n", | |
358 | pdata->regs[i].name); | |
f3d2570a | 359 | goto sysfs_exit; |
7f3923a1 CV |
360 | } |
361 | } | |
362 | ||
363 | return 0; | |
f3d2570a CV |
364 | |
365 | sysfs_exit: | |
366 | for (i--; i >= 0; i--) | |
367 | device_remove_file(&spi->dev, &pdata->regs[i].attr); | |
368 | ||
7f3923a1 | 369 | kfree_exit: |
7f3923a1 CV |
370 | spi->dev.platform_data = NULL; |
371 | return ret; | |
372 | } | |
373 | ||
5a167f45 | 374 | static int pcf2123_remove(struct spi_device *spi) |
7f3923a1 | 375 | { |
ffc75bb8 | 376 | struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev); |
7f3923a1 CV |
377 | int i; |
378 | ||
379 | if (pdata) { | |
7f3923a1 CV |
380 | for (i = 0; i < 16; i++) |
381 | if (pdata->regs[i].name[0]) | |
382 | device_remove_file(&spi->dev, | |
383 | &pdata->regs[i].attr); | |
7f3923a1 CV |
384 | } |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
3fc70077 JC |
389 | #ifdef CONFIG_OF |
390 | static const struct of_device_id pcf2123_dt_ids[] = { | |
391 | { .compatible = "nxp,rtc-pcf2123", }, | |
392 | { /* sentinel */ } | |
393 | }; | |
394 | MODULE_DEVICE_TABLE(of, pcf2123_dt_ids); | |
395 | #endif | |
396 | ||
7f3923a1 CV |
397 | static struct spi_driver pcf2123_driver = { |
398 | .driver = { | |
399 | .name = "rtc-pcf2123", | |
3fc70077 | 400 | .of_match_table = of_match_ptr(pcf2123_dt_ids), |
7f3923a1 CV |
401 | }, |
402 | .probe = pcf2123_probe, | |
5a167f45 | 403 | .remove = pcf2123_remove, |
7f3923a1 CV |
404 | }; |
405 | ||
109e9418 | 406 | module_spi_driver(pcf2123_driver); |
7f3923a1 CV |
407 | |
408 | MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>"); | |
409 | MODULE_DESCRIPTION("NXP PCF2123 RTC driver"); | |
410 | MODULE_LICENSE("GPL"); | |
411 | MODULE_VERSION(DRV_VERSION); |