[thirdparty/kernel/stable.git] / drivers / rtc / rtc-pcf2123.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * An SPI driver for the Philips PCF2123 RTC
 * Copyright 2009 Cyber Switching, Inc.
 *
 * Author: Chris Verges <chrisv@cyberswitching.com>
 * Maintainers: http://www.cyberswitching.com
 *
 * based on the RS5C348 driver in this same directory.
 *
 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
 * the sysfs contributions to this driver.
 *
 * Please note that the CS is active high, so platform data
 * should look something like:
 *
 * static struct spi_board_info ek_spi_devices[] = {
 *	...
 *	{
 *		.modalias		= "rtc-pcf2123",
 *		.chip_select		= 1,
 *		.controller_data	= (void *)AT91_PIN_PA10,
 *		.max_speed_hz		= 1000 * 1000,
 *		.mode			= SPI_CS_HIGH,
 *		.bus_num		= 0,
 *	},
 *	...
 *};
 */

#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/sysfs.h>

/* REGISTERS */
#define PCF2123_REG_CTRL1	(0x00)	/* Control Register 1 */
#define PCF2123_REG_CTRL2	(0x01)	/* Control Register 2 */
#define PCF2123_REG_SC		(0x02)	/* datetime */
#define PCF2123_REG_MN		(0x03)
#define PCF2123_REG_HR		(0x04)
#define PCF2123_REG_DM		(0x05)
#define PCF2123_REG_DW		(0x06)
#define PCF2123_REG_MO		(0x07)
#define PCF2123_REG_YR		(0x08)
#define PCF2123_REG_ALRM_MN	(0x09)	/* Alarm Registers */
#define PCF2123_REG_ALRM_HR	(0x0a)
#define PCF2123_REG_ALRM_DM	(0x0b)
#define PCF2123_REG_ALRM_DW	(0x0c)
#define PCF2123_REG_OFFSET	(0x0d)	/* Clock Rate Offset Register */
#define PCF2123_REG_TMR_CLKOUT	(0x0e)	/* Timer Registers */
#define PCF2123_REG_CTDWN_TMR	(0x0f)

/* PCF2123_REG_CTRL1 BITS */
#define CTRL1_CLEAR		(0)	/* Clear */
#define CTRL1_CORR_INT		BIT(1)	/* Correction irq enable */
#define CTRL1_12_HOUR		BIT(2)	/* 12 hour time */
#define CTRL1_SW_RESET	(BIT(3) | BIT(4) | BIT(6))	/* Software reset */
#define CTRL1_STOP		BIT(5)	/* Stop the clock */
#define CTRL1_EXT_TEST		BIT(7)	/* External clock test mode */

/* PCF2123_REG_CTRL2 BITS */
#define CTRL2_TIE		BIT(0)	/* Countdown timer irq enable */
#define CTRL2_AIE		BIT(1)	/* Alarm irq enable */
#define CTRL2_TF		BIT(2)	/* Countdown timer flag */
#define CTRL2_AF		BIT(3)	/* Alarm flag */
#define CTRL2_TI_TP		BIT(4)	/* Irq pin generates pulse */
#define CTRL2_MSF		BIT(5)	/* Minute or second irq flag */
#define CTRL2_SI		BIT(6)	/* Second irq enable */
#define CTRL2_MI		BIT(7)	/* Minute irq enable */

/* PCF2123_REG_SC BITS */
#define OSC_HAS_STOPPED		BIT(7)	/* Clock has been stopped */

/* PCF2123_REG_ALRM_XX BITS */
#define ALRM_ENABLE		BIT(7)	/* MN, HR, DM, or DW alarm enable */

/* PCF2123_REG_TMR_CLKOUT BITS */
#define CD_TMR_4096KHZ		(0)	/* 4096 KHz countdown timer */
#define CD_TMR_64HZ		(1)	/* 64 Hz countdown timer */
#define CD_TMR_1HZ		(2)	/* 1 Hz countdown timer */
#define CD_TMR_60th_HZ		(3)	/* 60th Hz countdown timer */
#define CD_TMR_TE		BIT(3)	/* Countdown timer enable */

/* PCF2123_REG_OFFSET BITS */
#define OFFSET_SIGN_BIT		6	/* 2's complement sign bit */
#define OFFSET_COARSE		BIT(7)	/* Coarse mode offset */
#define OFFSET_STEP		(2170)	/* Offset step in parts per billion */

/* READ/WRITE ADDRESS BITS */
#define PCF2123_WRITE		BIT(4)
#define PCF2123_READ		(BIT(4) | BIT(7))


static struct spi_driver pcf2123_driver;

struct pcf2123_sysfs_reg {
	struct device_attribute attr;
	char name[2];
};

struct pcf2123_plat_data {
	struct rtc_device *rtc;
	struct pcf2123_sysfs_reg regs[16];
};

/*
 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
 * is released properly after an SPI write.  This function should be
 * called after EVERY read/write call over SPI.
 */
static inline void pcf2123_delay_trec(void)
{
	ndelay(30);
}

static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	reg |= PCF2123_READ;
	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	txbuf[0] |= PCF2123_WRITE;
	ret = spi_write(spi, txbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
{
	u8 txbuf[2];

	txbuf[0] = reg;
	txbuf[1] = val;
	return pcf2123_write(dev, txbuf, sizeof(txbuf));
}

static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
			    char *buffer)
{
	struct pcf2123_sysfs_reg *r;
	u8 rxbuf[1];
	unsigned long reg;
	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = pcf2123_read(dev, reg, rxbuf, 1);
	if (ret < 0)
		return -EIO;

	return sprintf(buffer, "0x%x\n", rxbuf[0]);
}

static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
			     const char *buffer, size_t count)
{
	struct pcf2123_sysfs_reg *r;
	unsigned long reg;
	unsigned long val;

	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = kstrtoul(buffer, 10, &val);
	if (ret)
		return ret;

	ret = pcf2123_write_reg(dev, reg, val);
	if (ret < 0)
		return -EIO;
	return count;
}

static int pcf2123_read_offset(struct device *dev, long *offset)
{
	int ret;
	s8 reg;

	ret = pcf2123_read(dev, PCF2123_REG_OFFSET, &reg, 1);
	if (ret < 0)
		return ret;

	if (reg & OFFSET_COARSE)
		reg <<= 1; /* multiply by 2 and sign extend */
	else
		reg = sign_extend32(reg, OFFSET_SIGN_BIT);

	*offset = ((long)reg) * OFFSET_STEP;

	return 0;
}

/*
 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
 * The main difference between the two is normal offset adjusts the first
 * second of n minutes every other hour, with 61, 62 and 63 being shoved
 * into the 60th minute.
 * The coarse adjustment does the same, but every hour.
 * the two overlap, with every even normal offset value corresponding
 * to a coarse offset. Based on this algorithm, it seems that despite the
 * name, coarse offset is a better fit for overlapping values.
 */
static int pcf2123_set_offset(struct device *dev, long offset)
{
	s8 reg;

	if (offset > OFFSET_STEP * 127)
		reg = 127;
	else if (offset < OFFSET_STEP * -128)
		reg = -128;
	else
		reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);

	/* choose fine offset only for odd values in the normal range */
	if (reg & 1 && reg <= 63 && reg >= -64) {
		/* Normal offset. Clear the coarse bit */
		reg &= ~OFFSET_COARSE;
	} else {
		/* Coarse offset. Divide by 2 and set the coarse bit */
		reg >>= 1;
		reg |= OFFSET_COARSE;
	}

	return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
}

static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	u8 rxbuf[7];
	int ret;

	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	if (rxbuf[0] & OSC_HAS_STOPPED) {
		dev_info(dev, "clock was stopped. Time is not valid\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	tm->tm_wday = rxbuf[4] & 0x07;
	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(rxbuf[6]);
	if (tm->tm_year < 70)
		tm->tm_year += 100;	/* assume we are in 1970...2069 */

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	u8 txbuf[8];
	int ret;

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	/* Stop the counter first */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* Set the new time */
	txbuf[0] = PCF2123_REG_SC;
	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	txbuf[5] = tm->tm_wday & 0x07;
	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);

	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
	if (ret < 0)
		return ret;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static int pcf2123_reset(struct device *dev)
{
	int ret;
	u8  rxbuf[2];

	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	if (ret < 0)
		return ret;

	/* Stop the counter */
	dev_dbg(dev, "stopping RTC\n");
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* See if the counter was actually stopped */
	dev_dbg(dev, "checking for presence of RTC\n");
	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
		rxbuf[0], rxbuf[1]);
	if (!(rxbuf[0] & CTRL1_STOP))
		return -ENODEV;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static const struct rtc_class_ops pcf2123_rtc_ops = {
	.read_time	= pcf2123_rtc_read_time,
	.set_time	= pcf2123_rtc_set_time,
	.read_offset	= pcf2123_read_offset,
	.set_offset	= pcf2123_set_offset,

};

static int pcf2123_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	struct rtc_time tm;
	struct pcf2123_plat_data *pdata;
	int ret, i;

	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
				GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;
	spi->dev.platform_data = pdata;

	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
	if (ret < 0) {
		ret = pcf2123_reset(&spi->dev);
		if (ret < 0) {
			dev_err(&spi->dev, "chip not found\n");
			goto kfree_exit;
		}
	}

	dev_info(&spi->dev, "spiclk %u KHz.\n",
			(spi->max_speed_hz + 500) / 1000);

	/* Finalize the initialization */
	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
			&pcf2123_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc)) {
		dev_err(&spi->dev, "failed to register.\n");
		ret = PTR_ERR(rtc);
		goto kfree_exit;
	}

	pdata->rtc = rtc;

	for (i = 0; i < 16; i++) {
		sysfs_attr_init(&pdata->regs[i].attr.attr);
		sprintf(pdata->regs[i].name, "%1x", i);
		pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
		pdata->regs[i].attr.attr.name = pdata->regs[i].name;
		pdata->regs[i].attr.show = pcf2123_show;
		pdata->regs[i].attr.store = pcf2123_store;
		ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
		if (ret) {
			dev_err(&spi->dev, "Unable to create sysfs %s\n",
				pdata->regs[i].name);
			goto sysfs_exit;
		}
	}

	return 0;

sysfs_exit:
	for (i--; i >= 0; i--)
		device_remove_file(&spi->dev, &pdata->regs[i].attr);

kfree_exit:
	spi->dev.platform_data = NULL;
	return ret;
}

static int pcf2123_remove(struct spi_device *spi)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
	int i;

	if (pdata) {
		for (i = 0; i < 16; i++)
			if (pdata->regs[i].name[0])
				device_remove_file(&spi->dev,
						   &pdata->regs[i].attr);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id pcf2123_dt_ids[] = {
	{ .compatible = "nxp,rtc-pcf2123", },
	{ .compatible = "microcrystal,rv2123", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
#endif

static struct spi_driver pcf2123_driver = {
	.driver	= {
			.name	= "rtc-pcf2123",
			.of_match_table = of_match_ptr(pcf2123_dt_ids),
	},
	.probe	= pcf2123_probe,
	.remove	= pcf2123_remove,
};

module_spi_driver(pcf2123_driver);

MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
7f3923a1 CV	2	/*
	3	* An SPI driver for the Philips PCF2123 RTC
	4	* Copyright 2009 Cyber Switching, Inc.
	5	*
	6	* Author: Chris Verges <chrisv@cyberswitching.com>
	7	* Maintainers: http://www.cyberswitching.com
	8	*
	9	* based on the RS5C348 driver in this same directory.
	10	*
	11	* Thanks to Christian Pellegrin <chripell@fsfe.org> for
	12	* the sysfs contributions to this driver.
	13	*
7f3923a1 CV	14	* Please note that the CS is active high, so platform data
	15	* should look something like:
	16	*
	17	* static struct spi_board_info ek_spi_devices[] = {
369015fb SK	18	* ...
	19	* {
	20	* .modalias = "rtc-pcf2123",
	21	* .chip_select = 1,
	22	* .controller_data = (void *)AT91_PIN_PA10,
7f3923a1 CV	23	* .max_speed_hz = 1000 * 1000,
	24	* .mode = SPI_CS_HIGH,
	25	* .bus_num = 0,
	26	* },
	27	* ...
	28	*};
7f3923a1 CV	29	*/
	30
	31	#include <linux/bcd.h>
	32	#include <linux/delay.h>
	33	#include <linux/device.h>
	34	#include <linux/errno.h>
	35	#include <linux/init.h>
	36	#include <linux/kernel.h>
3fc70077	37	#include <linux/of.h>
7f3923a1	38	#include <linux/string.h>
5a0e3ad6	39	#include <linux/slab.h>
7f3923a1 CV	40	#include <linux/rtc.h>
7f3923a1 CV	41	#include <linux/spi/spi.h>
2113852b	42	#include <linux/module.h>
5ed12f12	43	#include <linux/sysfs.h>
7f3923a1	44
245cb74b	45	/* REGISTERS */
7f3923a1 CV	46	#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
	47	#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
	48	#define PCF2123_REG_SC (0x02) /* datetime */
	49	#define PCF2123_REG_MN (0x03)
	50	#define PCF2123_REG_HR (0x04)
	51	#define PCF2123_REG_DM (0x05)
	52	#define PCF2123_REG_DW (0x06)
	53	#define PCF2123_REG_MO (0x07)
	54	#define PCF2123_REG_YR (0x08)
245cb74b JC	55	#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
	56	#define PCF2123_REG_ALRM_HR (0x0a)
	57	#define PCF2123_REG_ALRM_DM (0x0b)
	58	#define PCF2123_REG_ALRM_DW (0x0c)
	59	#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
	60	#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
	61	#define PCF2123_REG_CTDWN_TMR (0x0f)
	62
	63	/* PCF2123_REG_CTRL1 BITS */
	64	#define CTRL1_CLEAR (0) /* Clear */
	65	#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
	66	#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
	67	#define CTRL1_SW_RESET (BIT(3) \| BIT(4) \| BIT(6)) /* Software reset */
	68	#define CTRL1_STOP BIT(5) /* Stop the clock */
	69	#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
	70
	71	/* PCF2123_REG_CTRL2 BITS */
	72	#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
	73	#define CTRL2_AIE BIT(1) /* Alarm irq enable */
	74	#define CTRL2_TF BIT(2) /* Countdown timer flag */
	75	#define CTRL2_AF BIT(3) /* Alarm flag */
	76	#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
	77	#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
	78	#define CTRL2_SI BIT(6) /* Second irq enable */
	79	#define CTRL2_MI BIT(7) /* Minute irq enable */
	80
	81	/* PCF2123_REG_SC BITS */
	82	#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
	83
	84	/* PCF2123_REG_ALRM_XX BITS */
	85	#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
	86
	87	/* PCF2123_REG_TMR_CLKOUT BITS */
	88	#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
	89	#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
	90	#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
	91	#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
	92	#define CD_TMR_TE BIT(3) /* Countdown timer enable */
	93
	94	/* PCF2123_REG_OFFSET BITS */
82df3e04	95	#define OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
245cb74b	96	#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
bae2f647	97	#define OFFSET_STEP (2170) /* Offset step in parts per billion */
245cb74b JC	98
	99	/* READ/WRITE ADDRESS BITS */
	100	#define PCF2123_WRITE BIT(4)
	101	#define PCF2123_READ (BIT(4) \| BIT(7))
7f3923a1	102
7f3923a1 CV	103
	104	static struct spi_driver pcf2123_driver;
	105
	106	struct pcf2123_sysfs_reg {
f3d2570a	107	struct device_attribute attr;
7f3923a1 CV	108	char name[2];
	109	};
	110
	111	struct pcf2123_plat_data {
	112	struct rtc_device *rtc;
	113	struct pcf2123_sysfs_reg regs[16];
	114	};
	115
	116	/*
	117	* Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
	118	* is released properly after an SPI write. This function should be
	119	* called after EVERY read/write call over SPI.
	120	*/
	121	static inline void pcf2123_delay_trec(void)
	122	{
	123	ndelay(30);
	124	}
	125
66c056d6 JC	126	static int pcf2123_read(struct device dev, u8 reg, u8 rxbuf, size_t size)
	127	{
	128	struct spi_device *spi = to_spi_device(dev);
	129	int ret;
	130
	131	reg \|= PCF2123_READ;
	132	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	133	pcf2123_delay_trec();
	134
	135	return ret;
	136	}
	137
809b453b JC	138	static int pcf2123_write(struct device dev, u8 txbuf, size_t size)
	139	{
	140	struct spi_device *spi = to_spi_device(dev);
	141	int ret;
	142
	143	txbuf[0] \|= PCF2123_WRITE;
	144	ret = spi_write(spi, txbuf, size);
	145	pcf2123_delay_trec();
	146
	147	return ret;
	148	}
	149
	150	static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
	151	{
	152	u8 txbuf[2];
	153
	154	txbuf[0] = reg;
	155	txbuf[1] = val;
	156	return pcf2123_write(dev, txbuf, sizeof(txbuf));
	157	}
	158
7f3923a1 CV	159	static ssize_t pcf2123_show(struct device dev, struct device_attribute attr,
	160	char *buffer)
	161	{
f3d2570a	162	struct pcf2123_sysfs_reg *r;
66c056d6	163	u8 rxbuf[1];
f3d2570a	164	unsigned long reg;
7f3923a1 CV	165	int ret;
7f3923a1 CV	166
f3d2570a CV	167	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	168
4c5591c1 JH	169	ret = kstrtoul(r->name, 16, &reg);
	170	if (ret)
	171	return ret;
f3d2570a	172
66c056d6	173	ret = pcf2123_read(dev, reg, rxbuf, 1);
7f3923a1	174	if (ret < 0)
f3d2570a	175	return -EIO;
66c056d6	176
f3d2570a	177	return sprintf(buffer, "0x%x\n", rxbuf[0]);
7f3923a1 CV	178	}
	179
	180	static ssize_t pcf2123_store(struct device dev, struct device_attribute attr,
83ab7dad CJ	181	const char *buffer, size_t count)
83ab7dad CJ	182	{
f3d2570a	183	struct pcf2123_sysfs_reg *r;
f3d2570a CV	184	unsigned long reg;
	185	unsigned long val;
	186
7f3923a1 CV	187	int ret;
7f3923a1 CV	188
f3d2570a CV	189	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	190
4c5591c1 JH	191	ret = kstrtoul(r->name, 16, &reg);
	192	if (ret)
	193	return ret;
	194
	195	ret = kstrtoul(buffer, 10, &val);
	196	if (ret)
	197	return ret;
f3d2570a	198
83ab7dad	199	ret = pcf2123_write_reg(dev, reg, val);
7f3923a1 CV	200	if (ret < 0)
7f3923a1 CV	201	return -EIO;
7f3923a1 CV	202	return count;
	203	}
	204
bae2f647 JC	205	static int pcf2123_read_offset(struct device dev, long offset)
	206	{
	207	int ret;
	208	s8 reg;
	209
	210	ret = pcf2123_read(dev, PCF2123_REG_OFFSET, &reg, 1);
	211	if (ret < 0)
	212	return ret;
	213
	214	if (reg & OFFSET_COARSE)
	215	reg <<= 1; /* multiply by 2 and sign extend */
	216	else
82df3e04	217	reg = sign_extend32(reg, OFFSET_SIGN_BIT);
bae2f647 JC	218
	219	offset = ((long)reg) OFFSET_STEP;
	220
	221	return 0;
	222	}
	223
	224	/*
	225	* The offset register is a 7 bit signed value with a coarse bit in bit 7.
	226	* The main difference between the two is normal offset adjusts the first
	227	* second of n minutes every other hour, with 61, 62 and 63 being shoved
	228	* into the 60th minute.
	229	* The coarse adjustment does the same, but every hour.
	230	* the two overlap, with every even normal offset value corresponding
	231	* to a coarse offset. Based on this algorithm, it seems that despite the
	232	* name, coarse offset is a better fit for overlapping values.
	233	*/
	234	static int pcf2123_set_offset(struct device *dev, long offset)
	235	{
	236	s8 reg;
	237
	238	if (offset > OFFSET_STEP * 127)
	239	reg = 127;
	240	else if (offset < OFFSET_STEP * -128)
	241	reg = -128;
	242	else
	243	reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
	244
	245	/* choose fine offset only for odd values in the normal range */
	246	if (reg & 1 && reg <= 63 && reg >= -64) {
	247	/* Normal offset. Clear the coarse bit */
	248	reg &= ~OFFSET_COARSE;
	249	} else {
	250	/* Coarse offset. Divide by 2 and set the coarse bit */
	251	reg >>= 1;
	252	reg \|= OFFSET_COARSE;
	253	}
	254
	255	return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
	256	}
	257
7f3923a1 CV	258	static int pcf2123_rtc_read_time(struct device dev, struct rtc_time tm)
7f3923a1 CV	259	{
66c056d6	260	u8 rxbuf[7];
7f3923a1 CV	261	int ret;
7f3923a1 CV	262
66c056d6	263	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
7f3923a1 CV	264	if (ret < 0)
7f3923a1 CV	265	return ret;
7f3923a1	266
f07fa924 JC	267	if (rxbuf[0] & OSC_HAS_STOPPED) {
	268	dev_info(dev, "clock was stopped. Time is not valid\n");
	269	return -EINVAL;
	270	}
	271
7f3923a1 CV	272	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	273	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	274	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	275	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	276	tm->tm_wday = rxbuf[4] & 0x07;
	277	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	278	tm->tm_year = bcd2bin(rxbuf[6]);
	279	if (tm->tm_year < 70)
	280	tm->tm_year += 100; /* assume we are in 1970...2069 */
	281
	282	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	283	"mday=%d, mon=%d, year=%d, wday=%d\n",
	284	__func__,
	285	tm->tm_sec, tm->tm_min, tm->tm_hour,
	286	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	287
22652ba7	288	return 0;
7f3923a1 CV	289	}
	290
	291	static int pcf2123_rtc_set_time(struct device dev, struct rtc_time tm)
	292	{
7f3923a1 CV	293	u8 txbuf[8];
	294	int ret;
	295
	296	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	297	"mday=%d, mon=%d, year=%d, wday=%d\n",
	298	__func__,
	299	tm->tm_sec, tm->tm_min, tm->tm_hour,
	300	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	301
	302	/* Stop the counter first */
809b453b	303	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
7f3923a1 CV	304	if (ret < 0)
7f3923a1 CV	305	return ret;
7f3923a1 CV	306
7f3923a1 CV	307	/* Set the new time */
809b453b	308	txbuf[0] = PCF2123_REG_SC;
7f3923a1 CV	309	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	310	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	311	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	312	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	313	txbuf[5] = tm->tm_wday & 0x07;
	314	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	315	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
	316
809b453b	317	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
7f3923a1 CV	318	if (ret < 0)
7f3923a1 CV	319	return ret;
7f3923a1 CV	320
7f3923a1 CV	321	/* Start the counter */
809b453b	322	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
7f3923a1 CV	323	if (ret < 0)
7f3923a1 CV	324	return ret;
7f3923a1 CV	325
	326	return 0;
	327	}
	328
1e094b94 JC	329	static int pcf2123_reset(struct device *dev)
	330	{
	331	int ret;
	332	u8 rxbuf[2];
	333
	334	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	335	if (ret < 0)
	336	return ret;
	337
	338	/* Stop the counter */
	339	dev_dbg(dev, "stopping RTC\n");
	340	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	341	if (ret < 0)
	342	return ret;
	343
	344	/* See if the counter was actually stopped */
	345	dev_dbg(dev, "checking for presence of RTC\n");
	346	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	347	if (ret < 0)
	348	return ret;
	349
	350	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
	351	rxbuf[0], rxbuf[1]);
	352	if (!(rxbuf[0] & CTRL1_STOP))
	353	return -ENODEV;
	354
	355	/* Start the counter */
	356	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	357	if (ret < 0)
	358	return ret;
	359
	360	return 0;
	361	}
	362
7f3923a1 CV	363	static const struct rtc_class_ops pcf2123_rtc_ops = {
	364	.read_time = pcf2123_rtc_read_time,
	365	.set_time = pcf2123_rtc_set_time,
bae2f647 JC	366	.read_offset = pcf2123_read_offset,
	367	.set_offset = pcf2123_set_offset,
	368
7f3923a1 CV	369	};
7f3923a1 CV	370
5a167f45	371	static int pcf2123_probe(struct spi_device *spi)
7f3923a1 CV	372	{
7f3923a1 CV	373	struct rtc_device *rtc;
f07fa924	374	struct rtc_time tm;
7f3923a1	375	struct pcf2123_plat_data *pdata;
7f3923a1 CV	376	int ret, i;
7f3923a1 CV	377
dd48ccc4 JH	378	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
dd48ccc4 JH	379	GFP_KERNEL);
7f3923a1 CV	380	if (!pdata)
	381	return -ENOMEM;
	382	spi->dev.platform_data = pdata;
	383
f07fa924	384	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
1e094b94	385	if (ret < 0) {
f07fa924 JC	386	ret = pcf2123_reset(&spi->dev);
	387	if (ret < 0) {
	388	dev_err(&spi->dev, "chip not found\n");
	389	goto kfree_exit;
	390	}
7f3923a1 CV	391	}
7f3923a1 CV	392
7f3923a1 CV	393	dev_info(&spi->dev, "spiclk %u KHz.\n",
	394	(spi->max_speed_hz + 500) / 1000);
	395
7f3923a1	396	/* Finalize the initialization */
dd48ccc4	397	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
7f3923a1 CV	398	&pcf2123_rtc_ops, THIS_MODULE);
	399
	400	if (IS_ERR(rtc)) {
	401	dev_err(&spi->dev, "failed to register.\n");
	402	ret = PTR_ERR(rtc);
	403	goto kfree_exit;
	404	}
	405
	406	pdata->rtc = rtc;
	407
	408	for (i = 0; i < 16; i++) {
5ed12f12	409	sysfs_attr_init(&pdata->regs[i].attr.attr);
7f3923a1 CV	410	sprintf(pdata->regs[i].name, "%1x", i);
	411	pdata->regs[i].attr.attr.mode = S_IRUGO \| S_IWUSR;
	412	pdata->regs[i].attr.attr.name = pdata->regs[i].name;
	413	pdata->regs[i].attr.show = pcf2123_show;
	414	pdata->regs[i].attr.store = pcf2123_store;
	415	ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
	416	if (ret) {
	417	dev_err(&spi->dev, "Unable to create sysfs %s\n",
	418	pdata->regs[i].name);
f3d2570a	419	goto sysfs_exit;
7f3923a1 CV	420	}
	421	}
	422
	423	return 0;
f3d2570a CV	424
	425	sysfs_exit:
	426	for (i--; i >= 0; i--)
	427	device_remove_file(&spi->dev, &pdata->regs[i].attr);
	428
7f3923a1	429	kfree_exit:
7f3923a1 CV	430	spi->dev.platform_data = NULL;
	431	return ret;
	432	}
	433
5a167f45	434	static int pcf2123_remove(struct spi_device *spi)
7f3923a1	435	{
ffc75bb8	436	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
7f3923a1 CV	437	int i;
	438
	439	if (pdata) {
7f3923a1 CV	440	for (i = 0; i < 16; i++)
	441	if (pdata->regs[i].name[0])
	442	device_remove_file(&spi->dev,
	443	&pdata->regs[i].attr);
7f3923a1 CV	444	}
	445
	446	return 0;
	447	}
	448
3fc70077 JC	449	#ifdef CONFIG_OF
	450	static const struct of_device_id pcf2123_dt_ids[] = {
	451	{ .compatible = "nxp,rtc-pcf2123", },
3c3d7101	452	{ .compatible = "microcrystal,rv2123", },
3fc70077 JC	453	{ /* sentinel */ }
	454	};
	455	MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
	456	#endif
	457
7f3923a1 CV	458	static struct spi_driver pcf2123_driver = {
	459	.driver = {
	460	.name = "rtc-pcf2123",
3fc70077	461	.of_match_table = of_match_ptr(pcf2123_dt_ids),
7f3923a1 CV	462	},
7f3923a1 CV	463	.probe = pcf2123_probe,
5a167f45	464	.remove = pcf2123_remove,
7f3923a1 CV	465	};
7f3923a1 CV	466
109e9418	467	module_spi_driver(pcf2123_driver);
7f3923a1 CV	468
	469	MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
	470	MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
	471	MODULE_LICENSE("GPL");