[thirdparty/kernel/stable.git] / drivers / rtc / rtc-stmp3xxx.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale STMP37XX/STMP378X Real Time Clock driver
 *
 * Copyright (c) 2007 Sigmatel, Inc.
 * Peter Hartley, <peter.hartley@sigmatel.com>
 *
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/rtc.h>
#include <linux/slab.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/stmp_device.h>
#include <linux/stmp3xxx_rtc_wdt.h>

#define STMP3XXX_RTC_CTRL			0x0
#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN		0x00000001
#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN	0x00000002
#define STMP3XXX_RTC_CTRL_ALARM_IRQ		0x00000004
#define STMP3XXX_RTC_CTRL_WATCHDOGEN		0x00000010

#define STMP3XXX_RTC_STAT			0x10
#define STMP3XXX_RTC_STAT_STALE_SHIFT		16
#define STMP3XXX_RTC_STAT_RTC_PRESENT		0x80000000
#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT	0x10000000
#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT	0x08000000

#define STMP3XXX_RTC_SECONDS			0x30

#define STMP3XXX_RTC_ALARM			0x40

#define STMP3XXX_RTC_WATCHDOG			0x50

#define STMP3XXX_RTC_PERSISTENT0		0x60
#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN		(1 << 2)
#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP	(1 << 4)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP	(1 << 5)
#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)

#define STMP3XXX_RTC_PERSISTENT1		0x70
/* missing bitmask in headers */
#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER	0x80000000

struct stmp3xxx_rtc_data {
	struct rtc_device *rtc;
	void __iomem *io;
	int irq_alarm;
};

#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
/**
 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
 * @dev: the parent device of the watchdog (= the RTC)
 * @timeout: the desired value for the timeout register of the watchdog.
 *           0 disables the watchdog
 *
 * The watchdog needs one register and two bits which are in the RTC domain.
 * To handle the resource conflict, the RTC driver will create another
 * platform_device for the watchdog driver as a child of the RTC device.
 * The watchdog driver is passed the below accessor function via platform_data
 * to configure the watchdog. Locking is not needed because accessing SET/CLR
 * registers is atomic.
 */

static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (timeout) {
		writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
		       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
		       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	}
}

static struct stmp3xxx_wdt_pdata wdt_pdata = {
	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
};

static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
	int rc = -1;
	struct platform_device *wdt_pdev =
		platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);

	if (wdt_pdev) {
		wdt_pdev->dev.parent = &rtc_pdev->dev;
		wdt_pdev->dev.platform_data = &wdt_pdata;
		rc = platform_device_add(wdt_pdev);
	}

	if (rc)
		dev_err(&rtc_pdev->dev,
			"failed to register stmp3xxx_rtc_wdt\n");
}
#else
static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
{
}
#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */

static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
{
	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
	/*
	 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	 * states:
	 * | The order in which registers are updated is
	 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	 * | (This list is in bitfield order, from LSB to MSB, as they would
	 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	 * | register. For example, the Seconds register corresponds to
	 * | STALE_REGS or NEW_REGS containing 0x80.)
	 */
	do {
		if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
				(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
			return 0;
		udelay(1);
	} while (--timeout > 0);
	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
		(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
}

/* Time read/write */
static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
{
	int ret;
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	ret = stmp3xxx_wait_time(rtc_data);
	if (ret)
		return ret;

	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
	return 0;
}

static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
	return stmp3xxx_wait_time(rtc_data);
}

/* interrupt(s) handler */
static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);

	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
		rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	if (enabled) {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_SET);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	} else {
		writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
				STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
			rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
				STMP_OFFSET_REG_CLR);
		writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
			rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	}
	return 0;
}

static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
	return 0;
}

static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);

	stmp3xxx_alarm_irq_enable(dev, alm->enabled);

	return 0;
}

static const struct rtc_class_ops stmp3xxx_rtc_ops = {
	.alarm_irq_enable =
			  stmp3xxx_alarm_irq_enable,
	.read_time	= stmp3xxx_rtc_gettime,
	.set_time	= stmp3xxx_rtc_settime,
	.read_alarm	= stmp3xxx_rtc_read_alarm,
	.set_alarm	= stmp3xxx_rtc_set_alarm,
};

static int stmp3xxx_rtc_remove(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);

	if (!rtc_data)
		return 0;

	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	return 0;
}

static int stmp3xxx_rtc_probe(struct platform_device *pdev)
{
	struct stmp3xxx_rtc_data *rtc_data;
	struct resource *r;
	u32 rtc_stat;
	u32 pers0_set, pers0_clr;
	u32 crystalfreq = 0;
	int err;

	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
	if (!rtc_data)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "failed to get resource\n");
		return -ENXIO;
	}

	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!rtc_data->io) {
		dev_err(&pdev->dev, "ioremap failed\n");
		return -EIO;
	}

	rtc_data->irq_alarm = platform_get_irq(pdev, 0);

	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
		dev_err(&pdev->dev, "no device onboard\n");
		return -ENODEV;
	}

	platform_set_drvdata(pdev, rtc_data);

	/*
	 * Resetting the rtc stops the watchdog timer that is potentially
	 * running. So (assuming it is running on purpose) don't reset if the
	 * watchdog is enabled.
	 */
	if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
	    STMP3XXX_RTC_CTRL_WATCHDOGEN) {
		dev_info(&pdev->dev,
			 "Watchdog is running, skip resetting rtc\n");
	} else {
		err = stmp_reset_block(rtc_data->io);
		if (err) {
			dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
				err);
			return err;
		}
	}

	/*
	 * Obviously the rtc needs a clock input to be able to run.
	 * This clock can be provided by an external 32k crystal. If that one is
	 * missing XTAL must not be disabled in suspend which consumes a
	 * lot of power. Normally the presence and exact frequency (supported
	 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	 * proves these fuses are not blown correctly on all machines, so the
	 * frequency can be overridden in the device tree.
	 */
	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
		crystalfreq = 32000;
	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
		crystalfreq = 32768;

	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
			     &crystalfreq);

	switch (crystalfreq) {
	case 32000:
		/* keep 32kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
			STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		break;
	case 32768:
		/* keep 32.768kHz crystal running in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
		break;
	default:
		dev_warn(&pdev->dev,
			 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
		/* fall-through */
	case 0:
		/* keep XTAL on in low-power mode */
		pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
		pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
			STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	}

	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
			STMP_OFFSET_REG_SET);

	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);

	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
			STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
		rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);

	rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc_data->rtc))
		return PTR_ERR(rtc_data->rtc);

	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
			stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
	if (err) {
		dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
			rtc_data->irq_alarm);
		return err;
	}

	rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
	rtc_data->rtc->range_max = U32_MAX;

	err = rtc_register_device(rtc_data->rtc);
	if (err)
		return err;

	stmp3xxx_wdt_register(pdev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int stmp3xxx_rtc_suspend(struct device *dev)
{
	return 0;
}

static int stmp3xxx_rtc_resume(struct device *dev)
{
	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);

	stmp_reset_block(rtc_data->io);
	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
			STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
		rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
			stmp3xxx_rtc_resume);

static const struct of_device_id rtc_dt_ids[] = {
	{ .compatible = "fsl,stmp3xxx-rtc", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rtc_dt_ids);

static struct platform_driver stmp3xxx_rtcdrv = {
	.probe		= stmp3xxx_rtc_probe,
	.remove		= stmp3xxx_rtc_remove,
	.driver		= {
		.name	= "stmp3xxx-rtc",
		.pm	= &stmp3xxx_rtc_pm_ops,
		.of_match_table = rtc_dt_ids,
	},
};

module_platform_driver(stmp3xxx_rtcdrv);

MODULE_DESCRIPTION("STMP3xxx RTC Driver");
MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
		"Wolfram Sang <w.sang@pengutronix.de>");
MODULE_LICENSE("GPL");
Commit	Line	Data
838d2d91	1	// SPDX-License-Identifier: GPL-2.0+
df17f631	2	/*
	3	* Freescale STMP37XX/STMP378X Real Time Clock driver
	4	*
	5	* Copyright (c) 2007 Sigmatel, Inc.
	6	* Peter Hartley, <peter.hartley@sigmatel.com>
	7	*
	8	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	9	* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
7e794cb7	10	* Copyright 2011 Wolfram Sang, Pengutronix e.K.
df17f631	11	*/
df17f631	12	#include <linux/kernel.h>
df17f631	13	#include <linux/module.h>
b5167159	14	#include <linux/io.h>
df17f631	15	#include <linux/init.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/interrupt.h>
28a0c883	18	#include <linux/delay.h>
df17f631	19	#include <linux/rtc.h>
5a0e3ad6	20	#include <linux/slab.h>
dd8d20a3	21	#include <linux/of_device.h>
c8a6046e	22	#include <linux/of.h>
1a71fb84 WS	23	#include <linux/stmp_device.h>
1a71fb84 WS	24	#include <linux/stmp3xxx_rtc_wdt.h>
df17f631	25
47eac337 WS	26	#define STMP3XXX_RTC_CTRL 0x0
	27	#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
	28	#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
	29	#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
1a71fb84	30	#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
47eac337 WS	31
	32	#define STMP3XXX_RTC_STAT 0x10
	33	#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
	34	#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
7f48b21b UKK	35	#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
7f48b21b UKK	36	#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
47eac337 WS	37
	38	#define STMP3XXX_RTC_SECONDS 0x30
	39
	40	#define STMP3XXX_RTC_ALARM 0x40
	41
1a71fb84 WS	42	#define STMP3XXX_RTC_WATCHDOG 0x50
1a71fb84 WS	43
47eac337	44	#define STMP3XXX_RTC_PERSISTENT0 0x60
7f48b21b UKK	45	#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
	46	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
	47	#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
	48	#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
	49	#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
	50	#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
	51	#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
df17f631	52
1a71fb84 WS	53	#define STMP3XXX_RTC_PERSISTENT1 0x70
	54	/* missing bitmask in headers */
	55	#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
	56
df17f631	57	struct stmp3xxx_rtc_data {
df17f631	58	struct rtc_device *rtc;
df17f631	59	void __iomem *io;
7e794cb7	60	int irq_alarm;
df17f631	61	};
df17f631	62
1a71fb84 WS	63	#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
	64	/**
	65	* stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
	66	* @dev: the parent device of the watchdog (= the RTC)
	67	* @timeout: the desired value for the timeout register of the watchdog.
	68	* 0 disables the watchdog
	69	*
	70	* The watchdog needs one register and two bits which are in the RTC domain.
	71	* To handle the resource conflict, the RTC driver will create another
	72	* platform_device for the watchdog driver as a child of the RTC device.
	73	* The watchdog driver is passed the below accessor function via platform_data
	74	* to configure the watchdog. Locking is not needed because accessing SET/CLR
	75	* registers is atomic.
	76	*/
	77
	78	static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
	79	{
	80	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	81
	82	if (timeout) {
	83	writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
	84	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	85	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
	86	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	87	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
	88	} else {
	89	writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
	90	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
	91	writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
	92	rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
	93	}
	94	}
	95
	96	static struct stmp3xxx_wdt_pdata wdt_pdata = {
	97	.wdt_set_timeout = stmp3xxx_wdt_set_timeout,
	98	};
	99
	100	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	101	{
3497610a	102	int rc = -1;
1a71fb84 WS	103	struct platform_device *wdt_pdev =
	104	platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
	105
	106	if (wdt_pdev) {
	107	wdt_pdev->dev.parent = &rtc_pdev->dev;
	108	wdt_pdev->dev.platform_data = &wdt_pdata;
3497610a	109	rc = platform_device_add(wdt_pdev);
1a71fb84	110	}
3497610a SM	111
	112	if (rc)
	113	dev_err(&rtc_pdev->dev,
	114	"failed to register stmp3xxx_rtc_wdt\n");
1a71fb84 WS	115	}
	116	#else
	117	static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
	118	{
	119	}
	120	#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
	121
28a0c883	122	static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
df17f631	123	{
28a0c883	124	int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
df17f631	125	/*
28a0c883 LW	126	* The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
	127	* states:
	128	* \| The order in which registers are updated is
	129	* \| Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
	130	* \| (This list is in bitfield order, from LSB to MSB, as they would
	131	* \| appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
	132	* \| register. For example, the Seconds register corresponds to
	133	* \| STALE_REGS or NEW_REGS containing 0x80.)
df17f631	134	*/
28a0c883 LW	135	do {
	136	if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	137	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
	138	return 0;
	139	udelay(1);
	140	} while (--timeout > 0);
	141	return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
	142	(0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
df17f631	143	}
	144
	145	/* Time read/write */
	146	static int stmp3xxx_rtc_gettime(struct device dev, struct rtc_time rtc_tm)
	147	{
28a0c883	148	int ret;
df17f631	149	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	150
28a0c883 LW	151	ret = stmp3xxx_wait_time(rtc_data);
	152	if (ret)
	153	return ret;
	154
a659a081	155	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
df17f631	156	return 0;
	157	}
	158
622eb9b4	159	static int stmp3xxx_rtc_settime(struct device dev, struct rtc_time rtc_tm)
df17f631	160	{
	161	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	162
622eb9b4	163	writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
28a0c883	164	return stmp3xxx_wait_time(rtc_data);
df17f631	165	}
	166
	167	/* interrupt(s) handler */
	168	static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
	169	{
	170	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
7e794cb7	171	u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
df17f631	172
47eac337	173	if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
b5167159	174	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
24417829	175	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7 WS	176	rtc_update_irq(rtc_data->rtc, 1, RTC_AF \| RTC_IRQF);
7e794cb7 WS	177	return IRQ_HANDLED;
df17f631	178	}
df17f631	179
7e794cb7	180	return IRQ_NONE;
df17f631	181	}
	182
	183	static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
	184	{
	185	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	186
df17f631	187	if (enabled) {
b5167159 WS	188	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	189	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	190	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	191	STMP_OFFSET_REG_SET);
b5167159	192	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	193	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
df17f631	194	} else {
b5167159 WS	195	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
b5167159 WS	196	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
24417829 HG	197	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	198	STMP_OFFSET_REG_CLR);
b5167159	199	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	200	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	201	}
	202	return 0;
	203	}
	204
df17f631	205	static int stmp3xxx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alm)
	206	{
	207	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
	208
a659a081	209	rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
df17f631	210	return 0;
	211	}
	212
	213	static int stmp3xxx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm)
	214	{
df17f631	215	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	216
a659a081	217	writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
7e794cb7 WS	218
	219	stmp3xxx_alarm_irq_enable(dev, alm->enabled);
	220
df17f631	221	return 0;
	222	}
	223
34c7b3ac	224	static const struct rtc_class_ops stmp3xxx_rtc_ops = {
df17f631	225	.alarm_irq_enable =
df17f631	226	stmp3xxx_alarm_irq_enable,
df17f631	227	.read_time = stmp3xxx_rtc_gettime,
622eb9b4	228	.set_time = stmp3xxx_rtc_settime,
df17f631	229	.read_alarm = stmp3xxx_rtc_read_alarm,
	230	.set_alarm = stmp3xxx_rtc_set_alarm,
	231	};
	232
	233	static int stmp3xxx_rtc_remove(struct platform_device *pdev)
	234	{
	235	struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
	236
	237	if (!rtc_data)
	238	return 0;
	239
7e794cb7	240	writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	241	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
df17f631	242
	243	return 0;
	244	}
	245
	246	static int stmp3xxx_rtc_probe(struct platform_device *pdev)
	247	{
	248	struct stmp3xxx_rtc_data *rtc_data;
	249	struct resource *r;
7f48b21b UKK	250	u32 rtc_stat;
	251	u32 pers0_set, pers0_clr;
	252	u32 crystalfreq = 0;
df17f631	253	int err;
df17f631	254
87a81420	255	rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
df17f631	256	if (!rtc_data)
	257	return -ENOMEM;
	258
	259	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	260	if (!r) {
	261	dev_err(&pdev->dev, "failed to get resource\n");
87a81420	262	return -ENXIO;
df17f631	263	}
df17f631	264
87a81420	265	rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
df17f631	266	if (!rtc_data->io) {
df17f631	267	dev_err(&pdev->dev, "ioremap failed\n");
87a81420	268	return -EIO;
df17f631	269	}
	270
	271	rtc_data->irq_alarm = platform_get_irq(pdev, 0);
df17f631	272
7f48b21b UKK	273	rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
7f48b21b UKK	274	if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
df17f631	275	dev_err(&pdev->dev, "no device onboard\n");
87a81420	276	return -ENODEV;
df17f631	277	}
df17f631	278
a91d2bab WS	279	platform_set_drvdata(pdev, rtc_data);
a91d2bab WS	280
dff700fa UKK	281	/*
	282	* Resetting the rtc stops the watchdog timer that is potentially
	283	* running. So (assuming it is running on purpose) don't reset if the
	284	* watchdog is enabled.
	285	*/
	286	if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
	287	STMP3XXX_RTC_CTRL_WATCHDOGEN) {
	288	dev_info(&pdev->dev,
	289	"Watchdog is running, skip resetting rtc\n");
	290	} else {
	291	err = stmp_reset_block(rtc_data->io);
	292	if (err) {
	293	dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
	294	err);
	295	return err;
	296	}
4e80b188 FE	297	}
4e80b188 FE	298
7f48b21b UKK	299	/*
	300	* Obviously the rtc needs a clock input to be able to run.
	301	* This clock can be provided by an external 32k crystal. If that one is
	302	* missing XTAL must not be disabled in suspend which consumes a
	303	* lot of power. Normally the presence and exact frequency (supported
	304	* are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
	305	* proves these fuses are not blown correctly on all machines, so the
	306	* frequency can be overridden in the device tree.
	307	*/
	308	if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
	309	crystalfreq = 32000;
	310	else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
	311	crystalfreq = 32768;
	312
	313	of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
	314	&crystalfreq);
	315
	316	switch (crystalfreq) {
	317	case 32000:
	318	/* keep 32kHz crystal running in low-power mode */
	319	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ \|
	320	STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	321	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	322	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	323	break;
	324	case 32768:
	325	/* keep 32.768kHz crystal running in low-power mode */
	326	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	327	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	328	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP \|
	329	STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
	330	break;
	331	default:
	332	dev_warn(&pdev->dev,
	333	"invalid crystal-freq specified in device-tree. Assuming no crystal\n");
	334	/* fall-through */
	335	case 0:
	336	/* keep XTAL on in low-power mode */
	337	pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
	338	pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP \|
	339	STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
	340	}
	341
24417829 HG	342	writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
24417829 HG	343	STMP_OFFSET_REG_SET);
7f48b21b	344
b5167159	345	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337	346	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
7f48b21b	347	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE \| pers0_clr,
24417829	348	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
a91d2bab	349
7e794cb7 WS	350	writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN \|
7e794cb7 WS	351	STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
24417829	352	rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
7e794cb7	353
0d823abd	354	rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
dfd2a178 JH	355	if (IS_ERR(rtc_data->rtc))
dfd2a178 JH	356	return PTR_ERR(rtc_data->rtc);
df17f631	357
87a81420 JH	358	err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
87a81420 JH	359	stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
df17f631	360	if (err) {
	361	dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
	362	rtc_data->irq_alarm);
dfd2a178	363	return err;
df17f631	364	}
df17f631	365
0d823abd AB	366	rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
	367	rtc_data->rtc->range_max = U32_MAX;
	368
	369	err = rtc_register_device(rtc_data->rtc);
	370	if (err)
	371	return err;
	372
1a71fb84	373	stmp3xxx_wdt_register(pdev);
df17f631	374	return 0;
df17f631	375	}
df17f631	376
ef69a7f0 JH	377	#ifdef CONFIG_PM_SLEEP
ef69a7f0 JH	378	static int stmp3xxx_rtc_suspend(struct device *dev)
df17f631	379	{
	380	return 0;
	381	}
	382
ef69a7f0	383	static int stmp3xxx_rtc_resume(struct device *dev)
df17f631	384	{
ef69a7f0	385	struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
df17f631	386
36d1da1d	387	stmp_reset_block(rtc_data->io);
b5167159	388	writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN \|
47eac337 WS	389	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN \|
47eac337 WS	390	STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
24417829	391	rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
df17f631	392	return 0;
df17f631	393	}
df17f631	394	#endif
df17f631	395
ef69a7f0 JH	396	static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
	397	stmp3xxx_rtc_resume);
	398
dd8d20a3 MV	399	static const struct of_device_id rtc_dt_ids[] = {
	400	{ .compatible = "fsl,stmp3xxx-rtc", },
	401	{ /* sentinel */ }
	402	};
	403	MODULE_DEVICE_TABLE(of, rtc_dt_ids);
	404
df17f631	405	static struct platform_driver stmp3xxx_rtcdrv = {
	406	.probe = stmp3xxx_rtc_probe,
	407	.remove = stmp3xxx_rtc_remove,
df17f631	408	.driver = {
df17f631	409	.name = "stmp3xxx-rtc",
ef69a7f0	410	.pm = &stmp3xxx_rtc_pm_ops,
462a465b	411	.of_match_table = rtc_dt_ids,
df17f631	412	},
	413	};
	414
0c4eae66	415	module_platform_driver(stmp3xxx_rtcdrv);
df17f631	416
df17f631	417	MODULE_DESCRIPTION("STMP3xxx RTC Driver");
7e794cb7 WS	418	MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
7e794cb7 WS	419	"Wolfram Sang <w.sang@pengutronix.de>");
df17f631	420	MODULE_LICENSE("GPL");