]>
Commit | Line | Data |
---|---|---|
1cb8e980 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * David Mueller, ELSOFT AG, d.mueller@elsoft.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* This code should work for both the S3C2400 and the S3C2410 | |
25 | * as they seem to have the same I2C controller inside. | |
26 | * The different address mapping is handled by the s3c24xx.h files below. | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | ||
31 | #ifdef CONFIG_DRIVER_S3C24X0_I2C | |
32 | ||
33 | #if defined(CONFIG_S3C2400) | |
34 | #include <s3c2400.h> | |
35 | #elif defined(CONFIG_S3C2410) | |
36 | #include <s3c2410.h> | |
37 | #endif | |
38 | #include <i2c.h> | |
39 | ||
40 | #ifdef CONFIG_HARD_I2C | |
41 | ||
48b42616 WD |
42 | #define I2C_WRITE 0 |
43 | #define I2C_READ 1 | |
1cb8e980 | 44 | |
48b42616 WD |
45 | #define I2C_OK 0 |
46 | #define I2C_NOK 1 | |
47 | #define I2C_NACK 2 | |
48 | #define I2C_NOK_LA 3 /* Lost arbitration */ | |
49 | #define I2C_NOK_TOUT 4 /* time out */ | |
1cb8e980 | 50 | |
48b42616 WD |
51 | #define I2CSTAT_BSY 0x20 /* Busy bit */ |
52 | #define I2CSTAT_NACK 0x01 /* Nack bit */ | |
53 | #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ | |
54 | #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ | |
55 | #define I2C_MODE_MR 0x80 /* Master Receive Mode */ | |
56 | #define I2C_START_STOP 0x20 /* START / STOP */ | |
57 | #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ | |
1cb8e980 | 58 | |
48b42616 | 59 | #define I2C_TIMEOUT 1 /* 1 seconde */ |
1cb8e980 WD |
60 | |
61 | ||
48b42616 | 62 | static int GetI2CSDA(void) |
1cb8e980 | 63 | { |
48b42616 WD |
64 | S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
65 | ||
66 | return (gpio->GPEDAT & 0x8000) >> 15; | |
1cb8e980 WD |
67 | } |
68 | ||
06d01dbe | 69 | #if 0 |
48b42616 | 70 | static void SetI2CSDA(int x) |
1cb8e980 WD |
71 | { |
72 | rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; | |
73 | } | |
06d01dbe | 74 | #endif |
1cb8e980 | 75 | |
48b42616 | 76 | static void SetI2CSCL(int x) |
1cb8e980 | 77 | { |
48b42616 WD |
78 | S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); |
79 | ||
80 | gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; | |
1cb8e980 WD |
81 | } |
82 | ||
83 | ||
84 | static int WaitForXfer(void) | |
85 | { | |
48b42616 | 86 | S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); |
1cb8e980 WD |
87 | int i, status; |
88 | ||
48b42616 WD |
89 | i = I2C_TIMEOUT * 1000; |
90 | status = i2c->IICCON; | |
91 | while ((i > 0) && !(status & I2CCON_IRPND)) { | |
8bde7f77 | 92 | udelay(1000); |
48b42616 | 93 | status = i2c->IICCON; |
1cb8e980 WD |
94 | i--; |
95 | } | |
96 | ||
48b42616 | 97 | return(status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; |
1cb8e980 WD |
98 | } |
99 | ||
100 | static int IsACK(void) | |
101 | { | |
48b42616 WD |
102 | S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); |
103 | ||
104 | return(!(i2c->IICSTAT & I2CSTAT_NACK)); | |
1cb8e980 WD |
105 | } |
106 | ||
107 | static void ReadWriteByte(void) | |
108 | { | |
48b42616 WD |
109 | S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); |
110 | ||
111 | i2c->IICCON &= ~I2CCON_IRPND; | |
1cb8e980 WD |
112 | } |
113 | ||
114 | void i2c_init (int speed, int slaveadd) | |
115 | { | |
48b42616 WD |
116 | S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); |
117 | S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); | |
1cb8e980 WD |
118 | ulong freq, pres = 16, div; |
119 | int i, status; | |
120 | ||
121 | /* wait for some time to give previous transfer a chance to finish */ | |
122 | ||
48b42616 WD |
123 | i = I2C_TIMEOUT * 1000; |
124 | status = i2c->IICSTAT; | |
125 | while ((i > 0) && (status & I2CSTAT_BSY)) { | |
1cb8e980 | 126 | udelay(1000); |
48b42616 | 127 | status = i2c->IICSTAT; |
1cb8e980 WD |
128 | i--; |
129 | } | |
130 | ||
48b42616 WD |
131 | if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) { |
132 | ulong old_gpecon = gpio->GPECON; | |
1cb8e980 WD |
133 | /* bus still busy probably by (most) previously interrupted transfer */ |
134 | ||
48b42616 WD |
135 | /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ |
136 | gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; | |
1cb8e980 | 137 | |
48b42616 WD |
138 | /* toggle I2CSCL until bus idle */ |
139 | SetI2CSCL(0); udelay(1000); | |
1cb8e980 | 140 | i = 10; |
48b42616 WD |
141 | while ((i > 0) && (GetI2CSDA() != 1)) { |
142 | SetI2CSCL(1); udelay(1000); | |
143 | SetI2CSCL(0); udelay(1000); | |
1cb8e980 WD |
144 | i--; |
145 | } | |
48b42616 | 146 | SetI2CSCL(1); udelay(1000); |
1cb8e980 WD |
147 | |
148 | /* restore pin functions */ | |
48b42616 | 149 | gpio->GPECON = old_gpecon; |
1cb8e980 WD |
150 | } |
151 | ||
152 | /* calculate prescaler and divisor values */ | |
153 | freq = get_PCLK(); | |
154 | if ((freq / pres / (16+1)) > speed) | |
155 | /* set prescaler to 512 */ | |
156 | pres = 512; | |
157 | ||
158 | div = 0; | |
159 | while ((freq / pres / (div+1)) > speed) | |
160 | div++; | |
161 | ||
162 | /* set prescaler, divisor according to freq, also set | |
163 | ACKGEN, IRQ */ | |
48b42616 | 164 | i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); |
1cb8e980 WD |
165 | |
166 | /* init to SLAVE REVEIVE and set slaveaddr */ | |
48b42616 WD |
167 | i2c->IICSTAT = 0; |
168 | i2c->IICADD = slaveadd; | |
1cb8e980 | 169 | /* program Master Transmit (and implicit STOP) */ |
48b42616 | 170 | i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; |
1cb8e980 WD |
171 | |
172 | } | |
173 | ||
174 | /* | |
175 | cmd_type is 0 for write 1 for read. | |
176 | ||
177 | addr_len can take any value from 0-255, it is only limited | |
178 | by the char, we could make it larger if needed. If it is | |
179 | 0 we skip the address write cycle. | |
180 | ||
181 | */ | |
182 | static | |
183 | int i2c_transfer(unsigned char cmd_type, | |
8bde7f77 WD |
184 | unsigned char chip, |
185 | unsigned char addr[], | |
186 | unsigned char addr_len, | |
187 | unsigned char data[], | |
1cb8e980 WD |
188 | unsigned short data_len) |
189 | { | |
48b42616 | 190 | S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); |
1cb8e980 WD |
191 | int i, status, result; |
192 | ||
193 | if (data == 0 || data_len == 0) { | |
194 | /*Don't support data transfer of no length or to address 0*/ | |
195 | printf( "i2c_transfer: bad call\n" ); | |
48b42616 | 196 | return I2C_NOK; |
1cb8e980 WD |
197 | } |
198 | ||
8bde7f77 | 199 | /*CheckDelay(); */ |
1cb8e980 WD |
200 | |
201 | /* Check I2C bus idle */ | |
48b42616 WD |
202 | i = I2C_TIMEOUT * 1000; |
203 | status = i2c->IICSTAT; | |
204 | while ((i > 0) && (status & I2CSTAT_BSY)) { | |
1cb8e980 | 205 | udelay(1000); |
48b42616 | 206 | status = i2c->IICSTAT; |
1cb8e980 WD |
207 | i--; |
208 | } | |
209 | ||
210 | ||
48b42616 WD |
211 | if (status & I2CSTAT_BSY) { |
212 | result = I2C_NOK_TOUT; | |
8bde7f77 | 213 | return(result); |
1cb8e980 WD |
214 | } |
215 | ||
48b42616 | 216 | i2c->IICCON |= 0x80; |
1cb8e980 | 217 | |
48b42616 | 218 | result = I2C_OK; |
1cb8e980 WD |
219 | |
220 | switch (cmd_type) { | |
48b42616 | 221 | case I2C_WRITE: |
1cb8e980 | 222 | if (addr && addr_len) { |
48b42616 | 223 | i2c->IICDS = chip; |
1cb8e980 | 224 | /* send START */ |
48b42616 | 225 | i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; |
1cb8e980 | 226 | i = 0; |
48b42616 | 227 | while ((i < addr_len) && (result == I2C_OK)) { |
1cb8e980 | 228 | result = WaitForXfer(); |
48b42616 | 229 | i2c->IICDS = addr[i]; |
1cb8e980 WD |
230 | ReadWriteByte(); |
231 | i++; | |
232 | } | |
233 | i = 0; | |
48b42616 | 234 | while ((i < data_len) && (result == I2C_OK)) { |
1cb8e980 | 235 | result = WaitForXfer(); |
48b42616 | 236 | i2c->IICDS = data[i]; |
1cb8e980 WD |
237 | ReadWriteByte(); |
238 | i++; | |
239 | } | |
240 | } else { | |
48b42616 | 241 | i2c->IICDS = chip; |
1cb8e980 | 242 | /* send START */ |
48b42616 | 243 | i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; |
1cb8e980 | 244 | i = 0; |
48b42616 | 245 | while ((i < data_len) && (result = I2C_OK)) { |
1cb8e980 | 246 | result = WaitForXfer(); |
48b42616 | 247 | i2c->IICDS = data[i]; |
1cb8e980 WD |
248 | ReadWriteByte(); |
249 | i++; | |
250 | } | |
251 | } | |
252 | ||
48b42616 | 253 | if (result == I2C_OK) |
8bde7f77 | 254 | result = WaitForXfer(); |
1cb8e980 WD |
255 | |
256 | /* send STOP */ | |
48b42616 | 257 | i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; |
1cb8e980 WD |
258 | ReadWriteByte(); |
259 | break; | |
260 | ||
48b42616 | 261 | case I2C_READ: |
1cb8e980 | 262 | if (addr && addr_len) { |
48b42616 WD |
263 | i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; |
264 | i2c->IICDS = chip; | |
1cb8e980 | 265 | /* send START */ |
48b42616 | 266 | i2c->IICSTAT |= I2C_START_STOP; |
1cb8e980 WD |
267 | result = WaitForXfer(); |
268 | if (IsACK()) { | |
269 | i = 0; | |
48b42616 WD |
270 | while ((i < addr_len) && (result == I2C_OK)) { |
271 | i2c->IICDS = addr[i]; | |
1cb8e980 WD |
272 | ReadWriteByte(); |
273 | result = WaitForXfer(); | |
274 | i++; | |
275 | } | |
276 | ||
48b42616 | 277 | i2c->IICDS = chip; |
1cb8e980 | 278 | /* resend START */ |
48b42616 | 279 | i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP; |
1cb8e980 WD |
280 | ReadWriteByte(); |
281 | result = WaitForXfer(); | |
282 | i = 0; | |
48b42616 | 283 | while ((i < data_len) && (result == I2C_OK)) { |
1cb8e980 WD |
284 | /* disable ACK for final READ */ |
285 | if (i == data_len - 1) | |
48b42616 | 286 | i2c->IICCON &= ~0x80; |
1cb8e980 WD |
287 | ReadWriteByte(); |
288 | result = WaitForXfer(); | |
48b42616 | 289 | data[i] = i2c->IICDS; |
1cb8e980 WD |
290 | i++; |
291 | } | |
292 | } else { | |
48b42616 | 293 | result = I2C_NACK; |
1cb8e980 WD |
294 | } |
295 | ||
296 | } else { | |
48b42616 WD |
297 | i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; |
298 | i2c->IICDS = chip; | |
1cb8e980 | 299 | /* send START */ |
48b42616 | 300 | i2c->IICSTAT |= I2C_START_STOP; |
1cb8e980 WD |
301 | result = WaitForXfer(); |
302 | ||
303 | if (IsACK()) { | |
304 | i = 0; | |
48b42616 | 305 | while ((i < data_len) && (result == I2C_OK)) { |
1cb8e980 WD |
306 | /* disable ACK for final READ */ |
307 | if (i == data_len - 1) | |
48b42616 | 308 | i2c->IICCON &= ~0x80; |
8bde7f77 | 309 | ReadWriteByte(); |
1cb8e980 | 310 | result = WaitForXfer(); |
48b42616 | 311 | data[i] = i2c->IICDS; |
1cb8e980 WD |
312 | i++; |
313 | } | |
314 | } else { | |
48b42616 | 315 | result = I2C_NACK; |
1cb8e980 WD |
316 | } |
317 | } | |
318 | ||
319 | /* send STOP */ | |
48b42616 | 320 | i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; |
1cb8e980 WD |
321 | ReadWriteByte(); |
322 | break; | |
323 | ||
324 | default: | |
325 | printf( "i2c_transfer: bad call\n" ); | |
8bde7f77 | 326 | result = I2C_NOK; |
1cb8e980 WD |
327 | break; |
328 | } | |
329 | ||
330 | return (result); | |
331 | } | |
332 | ||
333 | int i2c_probe (uchar chip) | |
334 | { | |
335 | uchar buf[1]; | |
336 | ||
337 | buf[0] = 0; | |
338 | ||
339 | /* | |
340 | * What is needed is to send the chip address and verify that the | |
341 | * address was <ACK>ed (i.e. there was a chip at that address which | |
342 | * drove the data line low). | |
343 | */ | |
48b42616 | 344 | return(i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); |
1cb8e980 WD |
345 | } |
346 | ||
347 | int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) | |
348 | { | |
349 | uchar xaddr[4]; | |
350 | int ret; | |
351 | ||
352 | if ( alen > 4 ) { | |
353 | printf ("I2C read: addr len %d not supported\n", alen); | |
354 | return 1; | |
355 | } | |
356 | ||
357 | if ( alen > 0 ) { | |
358 | xaddr[0] = (addr >> 24) & 0xFF; | |
8bde7f77 WD |
359 | xaddr[1] = (addr >> 16) & 0xFF; |
360 | xaddr[2] = (addr >> 8) & 0xFF; | |
361 | xaddr[3] = addr & 0xFF; | |
1cb8e980 WD |
362 | } |
363 | ||
364 | ||
365 | #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW | |
366 | /* | |
367 | * EEPROM chips that implement "address overflow" are ones | |
368 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
369 | * address and the extra bits end up in the "chip address" | |
370 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
371 | * four 256 byte chips. | |
372 | * | |
373 | * Note that we consider the length of the address field to | |
374 | * still be one byte because the extra address bits are | |
375 | * hidden in the chip address. | |
376 | */ | |
377 | if( alen > 0 ) | |
378 | chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); | |
379 | #endif | |
48b42616 | 380 | if( (ret = i2c_transfer(I2C_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { |
8bde7f77 WD |
381 | printf( "I2c read: failed %d\n", ret); |
382 | return 1; | |
1cb8e980 WD |
383 | } |
384 | return 0; | |
385 | } | |
386 | ||
387 | int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) | |
388 | { | |
389 | uchar xaddr[4]; | |
390 | ||
391 | if ( alen > 4 ) { | |
392 | printf ("I2C write: addr len %d not supported\n", alen); | |
393 | return 1; | |
394 | } | |
395 | ||
396 | if ( alen > 0 ) { | |
8bde7f77 WD |
397 | xaddr[0] = (addr >> 24) & 0xFF; |
398 | xaddr[1] = (addr >> 16) & 0xFF; | |
399 | xaddr[2] = (addr >> 8) & 0xFF; | |
400 | xaddr[3] = addr & 0xFF; | |
1cb8e980 WD |
401 | } |
402 | ||
403 | #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW | |
404 | /* | |
405 | * EEPROM chips that implement "address overflow" are ones | |
406 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
407 | * address and the extra bits end up in the "chip address" | |
408 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
409 | * four 256 byte chips. | |
410 | * | |
411 | * Note that we consider the length of the address field to | |
412 | * still be one byte because the extra address bits are | |
413 | * hidden in the chip address. | |
414 | */ | |
415 | if( alen > 0 ) | |
8bde7f77 | 416 | chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); |
1cb8e980 | 417 | #endif |
48b42616 | 418 | return (i2c_transfer(I2C_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); |
1cb8e980 WD |
419 | } |
420 | ||
421 | #endif /* CONFIG_HARD_I2C */ | |
422 | ||
423 | #endif /* CONFIG_DRIVER_S3C24X0_I2C */ |