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1 | #ifndef __S3C4510B_ETH_H |
2 | #define __S3C4510B_ETH_H | |
3 | /* | |
4 | * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) | |
5 | * Curt Brune <curt@cucy.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | * | |
25 | * MODULE: $Id:$ | |
26 | * Description: Ethernet interface | |
27 | * Runtime Env: ARM7TDMI | |
28 | * Change History: | |
29 | * 03-02-04 Create (Curt Brune) curt@cucy.com | |
30 | * | |
31 | */ | |
32 | ||
33 | #define __packed __attribute__ ((packed)) | |
34 | ||
35 | #define ETH_MAC_ADDR_SIZE (6) /* dst,src addr is 6bytes each */ | |
36 | #define ETH_MaxTxFrames (16) /* Max number of Tx Frames */ | |
37 | ||
38 | /* Buffered DMA Receiver Control Register */ | |
39 | #define ETH_BRxBRST 0x0000F /* BDMA Rx Burst Size * BRxBRST */ | |
40 | /* = Burst Data Size 16 */ | |
41 | #define ETH_BRxSTSKO 0x00020 /* BDMA Rx Stop/Skip Frame or Interrupt(=1) */ | |
42 | /* case of not OWNER the current Frame */ | |
43 | #define ETH_BRxMAINC 0x00040 /* BDMA Rx Memory Address Inc/Dec */ | |
44 | #define ETH_BRxDIE 0x00080 /* BDMA Rx Every Received Frame Interrupt Enable */ | |
45 | #define ETH_BRxNLIE 0x00100 /* BDMA Rx NULL List Interrupt Enable */ | |
46 | #define ETH_BRxNOIE 0x00200 /* BDMA Rx Not Owner Interrupt Enable */ | |
47 | #define ETH_BRxMSOIE 0x00400 /* BDMA Rx Maximum Size over Interrupr Enable */ | |
48 | #define ETH_BRxLittle 0x00800 /* BDMA Rx Big/Little Endian */ | |
49 | #define ETH_BRxBig 0x00000 /* BDMA Rx Big/Little Endian */ | |
50 | #define ETH_BRxWA01 0x01000 /* BDMA Rx Word Alignment- one invalid byte */ | |
51 | #define ETH_BRxWA10 0x02000 /* BDMA Rx Word Alignment- two invalid byte */ | |
52 | #define ETH_BRxWA11 0x03000 /* BDMA Rx Word Alignment- three invalid byte */ | |
53 | #define ETH_BRxEn 0x04000 /* BDMA Rx Enable */ | |
54 | #define ETH_BRxRS 0x08000 /* BDMA Rx Reset */ | |
55 | #define ETH_RxEmpty 0x10000 /* BDMA Rx Buffer empty interrupt */ | |
56 | #define ETH_BRxEarly 0x20000 /* BDMA Rx Early notify Interrupt */ | |
57 | ||
58 | /* Buffered DMA Trasmit Control Register(BDMATXCON) */ | |
59 | #define ETH_BTxBRST 0x0000F /* BDMA Tx Burst Size = 16 */ | |
60 | #define ETH_BTxSTSKO 0x00020 /* BDMA Tx Stop/Skip Frame or Interrupt in case */ | |
61 | /* of not Owner the current frame */ | |
62 | #define ETH_BTxCPIE 0x00080 /* BDMA Tx Complete to send control */ | |
63 | /* packet Enable */ | |
64 | #define ETH_BTxNOIE 0x00200 /* BDMA Tx Buffer Not Owner */ | |
65 | #define ETH_BTxEmpty 0x00400 /* BDMA Tx Buffer Empty Interrupt */ | |
66 | ||
67 | /* BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. */ | |
68 | #define ETH_BTxMSL000 0x00000 /* No wait to fill the BDMA */ | |
69 | #define ETH_BTxMSL001 0x00800 /* wait to fill 1/8 of the BDMA */ | |
70 | #define ETH_BTxMSL010 0x01000 /* wait to fill 2/8 of the BDMA */ | |
71 | #define ETH_BTxMSL011 0x01800 /* wait to fill 3/8 of the BDMA */ | |
72 | #define ETH_BTxMSL100 0x02000 /* wait to fill 4/8 of the BDMA */ | |
73 | #define ETH_BTxMSL101 0x02800 /* wait to fill 5/8 of the BDMA */ | |
74 | #define ETH_BTxMSL110 0x03000 /* wait to fill 6/8 of the BDMA */ | |
75 | #define ETH_BTxMSL111 0x03800 /* wait to fill 7/8 of the BDMA */ | |
76 | #define ETH_BTxEn 0x04000 /* BDMA Tx Enable */ | |
77 | #define ETH_BTxRS 0x08000 /* BDMA Tx Reset */ | |
78 | ||
79 | /* BDMA Status Register */ | |
80 | #define ETH_S_BRxRDF 0x00001 /* BDMA Rx Done Every Received Frame */ | |
81 | #define ETH_S_BRxNL 0x00002 /* BDMA Rx NULL List */ | |
82 | #define ETH_S_BRxNO 0x00004 /* BDMA Rx Not Owner */ | |
83 | #define ETH_S_BRxMSO 0x00008 /* BDMA Rx Maximum Size Over */ | |
84 | #define ETH_S_BRxEmpty 0x00010 /* BDMA Rx Buffer Empty */ | |
85 | #define ETH_S_BRxSEarly 0x00020 /* Early Notify */ | |
86 | #define ETH_S_BRxFRF 0x00080 /* One more frame data in BDMA receive buffer */ | |
87 | #define ETH_S_BTxCCP 0x10000 /* BDMA Tx Complete to send Control Packet */ | |
88 | #define ETH_S_BTxNL 0x20000 /* BDMA Tx Null List */ | |
89 | #define ETH_S_BTxNO 0x40000 /* BDMA Tx Not Owner */ | |
90 | #define ETH_S_BTxEmpty 0x100000 /* BDMA Tx Buffer Empty */ | |
91 | ||
92 | /* MAC Control Register */ | |
93 | #define ETH_HaltReg 0x0001 /* stop transmission and reception */ | |
94 | /* after completion of any current packets */ | |
95 | #define ETH_HaltImm 0x0002 /* Stop transmission and reception immediately */ | |
96 | #define ETH_SwReset 0x0004 /* reset all Ethernet controller state machines */ | |
97 | /* and FIFOs */ | |
98 | #define ETH_FullDup 0x0008 /* allow transmission to begin while reception */ | |
99 | /* is occurring */ | |
100 | #define ETH_MACLoop 0x0010 /* MAC loopback */ | |
101 | #define ETH_ConnM00 0x0000 /* Automatic-default */ | |
102 | #define ETH_ConnM01 0x0020 /* Force 10Mbits endec */ | |
103 | #define ETH_ConnM10 0x0040 /* Force MII (rate determined by MII clock */ | |
104 | #define ETH_MIIOFF 0x0040 /* Force MII (rate determined by MII clock */ | |
105 | #define ETH_Loop10 0x0080 /* Loop 10Mbps */ | |
106 | #define ETH_MissRoll 0x0400 /* Missed error counter rolled over */ | |
107 | #define ETH_MDCOFF 0x1000 /* MII Station Management Clock Off */ | |
108 | #define ETH_EnMissRoll 0x2000 /* Interrupt when missed error counter rolls */ | |
109 | /* over */ | |
110 | #define ETH_Link10 0x8000 /* Link status 10Mbps */ | |
111 | ||
112 | /* CAM control register(CAMCON) */ | |
113 | #define ETH_StationAcc 0x0001 /* Accept any packet with a unicast station */ | |
114 | /* address */ | |
115 | #define ETH_GroupAcc 0x0002 /* Accept any packet with multicast-group */ | |
116 | /* station address */ | |
117 | #define ETH_BroadAcc 0x0004 /* Accept any packet with a broadcast station */ | |
118 | /* address */ | |
119 | #define ETH_NegCAM 0x0008 /* 0: Accept packets CAM recognizes, */ | |
120 | /* reject others */ | |
121 | /* 1: reject packets CAM recognizes, */ | |
122 | /* accept others */ | |
123 | #define ETH_CompEn 0x0010 /* Compare Enable mode */ | |
124 | ||
125 | /* Transmit Control Register(MACTXCON) */ | |
126 | #define ETH_TxEn 0x0001 /* transmit Enable */ | |
127 | #define ETH_TxHalt 0x0002 /* Transmit Halt Request */ | |
128 | #define ETH_NoPad 0x0004 /* suppress Padding */ | |
129 | #define ETH_NoCRC 0x0008 /* Suppress CRC */ | |
130 | #define ETH_FBack 0x0010 /* Fast Back-off */ | |
131 | #define ETH_NoDef 0x0020 /* Disable the defer counter */ | |
132 | #define ETH_SdPause 0x0040 /* Send Pause */ | |
133 | #define ETH_MII10En 0x0080 /* MII 10Mbps mode enable */ | |
134 | #define ETH_EnUnder 0x0100 /* Enable Underrun */ | |
135 | #define ETH_EnDefer 0x0200 /* Enable Deferral */ | |
136 | #define ETH_EnNCarr 0x0400 /* Enable No Carrier */ | |
137 | #define ETH_EnExColl 0x0800 /* interrupt if 16 collision occur */ | |
138 | /* in the same packet */ | |
139 | #define ETH_EnLateColl 0x1000 /* interrupt if collision occurs after */ | |
140 | /* 512 bit times(64 bytes times) */ | |
141 | #define ETH_EnTxPar 0x2000 /* interrupt if the MAC transmit FIFO */ | |
142 | /* has a parity error */ | |
143 | #define ETH_EnComp 0x4000 /* interrupt when the MAC transmits or */ | |
144 | /* discards one packet */ | |
145 | ||
146 | /* Transmit Status Register(MACTXSTAT) */ | |
147 | #define ETH_ExColl 0x0010 /* Excessive collision */ | |
148 | #define ETH_TxDeffered 0x0020 /* set if 16 collisions occur for same packet */ | |
149 | #define ETH_Paused 0x0040 /* packet waited because of pause during */ | |
150 | /* transmission */ | |
151 | #define ETH_IntTx 0x0080 /* set if transmission of packet causes an */ | |
152 | /* interrupt condiftion */ | |
153 | #define ETH_Under 0x0100 /* MAC transmit FIFO becomes empty during */ | |
154 | /* transmission */ | |
155 | #define ETH_Defer 0x0200 /* MAC defers for MAC deferral */ | |
156 | #define ETH_NCarr 0x0400 /* No carrier sense detected during the */ | |
157 | /* transmission of a packet */ | |
158 | #define ETH_SQE 0x0800 /* Signal Quality Error */ | |
159 | #define ETH_LateColl 0x1000 /* a collision occures after 512 bit times */ | |
160 | #define ETH_TxPar 0x2000 /* MAC transmit FIFO has detected a parity error */ | |
161 | #define ETH_Comp 0x4000 /* MAC transmit or discards one packet */ | |
162 | #define ETH_TxHalted 0x8000 /* Transmission was halted by clearing */ | |
163 | /* TxEn or Halt immedite */ | |
164 | ||
165 | /* Receive Control Register (MACRXCON) */ | |
166 | #define ETH_RxEn 0x0001 | |
167 | #define ETH_RxHalt 0x0002 | |
168 | #define ETH_LongEn 0x0004 | |
169 | #define ETH_ShortEn 0x0008 | |
170 | #define ETH_StripCRC 0x0010 | |
171 | #define ETH_PassCtl 0x0020 | |
172 | #define ETH_IgnoreCRC 0x0040 | |
173 | #define ETH_EnAlign 0x0100 | |
174 | #define ETH_EnCRCErr 0x0200 | |
175 | #define ETH_EnOver 0x0400 | |
176 | #define ETH_EnLongErr 0x0800 | |
177 | #define ETH_EnRxPar 0x2000 | |
178 | #define ETH_EnGood 0x4000 | |
179 | ||
180 | /* Receive Status Register(MACRXSTAT) */ | |
181 | #define ETH_MCtlRecd 0x0020 | |
182 | #define ETH_MIntRx 0x0040 | |
183 | #define ETH_MRx10Stat 0x0080 | |
184 | #define ETH_MAllignErr 0x0100 | |
185 | #define ETH_MCRCErr 0x0200 | |
186 | #define ETH_MOverflow 0x0400 | |
187 | #define ETH_MLongErr 0x0800 | |
188 | #define ETH_MRxPar 0x2000 | |
189 | #define ETH_MRxGood 0x4000 | |
190 | #define ETH_MRxHalted 0x8000 | |
191 | ||
192 | /* type of ethernet packets */ | |
193 | #define ETH_TYPE_ARP (0x0806) | |
194 | #define ETH_TYPE_IP (0x0800) | |
195 | ||
196 | #define ETH_HDR_SIZE (14) | |
197 | ||
198 | /* bit field for frame data pointer word */ | |
199 | typedef struct __BF_FrameDataPtr { | |
200 | u32 dataPtr:31; | |
201 | u32 owner: 1; | |
202 | } BF_FrameDataPtr; | |
203 | ||
204 | typedef union _FrameDataPtr { | |
205 | u32 ui; | |
206 | BF_FrameDataPtr bf; | |
207 | } FrameDataPtr; | |
208 | ||
209 | typedef struct __BF_TX_Options { | |
210 | u32 no_padding: 1; | |
211 | u32 no_crc: 1; | |
212 | u32 macTxIrqEnbl: 1; | |
213 | u32 littleEndian: 1; | |
214 | u32 frameDataDir: 1; | |
215 | u32 widgetAlign: 2; | |
216 | u32 reserved:25; | |
217 | } BF_TX_Options; | |
218 | ||
219 | typedef union _TX_Options { | |
220 | u32 ui; | |
221 | BF_TX_Options bf; | |
222 | } TX_Options; | |
223 | ||
224 | typedef struct __BF_RX_Status { | |
225 | u32 len:16; /* frame length */ | |
226 | u32 reserved1: 3; | |
227 | u32 overMax: 1; | |
228 | u32 reserved2: 1; | |
229 | u32 ctrlRcv: 1; | |
230 | u32 intRx: 1; | |
231 | u32 rx10stat: 1; | |
232 | u32 alignErr: 1; | |
233 | u32 crcErr: 1; | |
234 | u32 overFlow: 1; | |
235 | u32 longErr: 1; | |
236 | u32 reserved3: 1; | |
237 | u32 parityErr: 1; | |
238 | u32 good: 1; | |
239 | u32 halted: 1; | |
240 | } BF_RX_Status; | |
241 | ||
242 | typedef union _RX_Status { | |
243 | u32 ui; | |
244 | BF_RX_Status bf; | |
245 | } RX_Status; | |
246 | ||
247 | typedef struct __BF_TX_Status { | |
248 | u32 len:16; /* frame length */ | |
249 | u32 txCollCnt: 4; | |
250 | u32 exColl: 1; | |
251 | u32 txDefer: 1; | |
252 | u32 paused: 1; | |
253 | u32 intTx: 1; | |
254 | u32 underRun: 1; | |
255 | u32 defer: 1; | |
256 | u32 noCarrier: 1; | |
257 | u32 SQErr: 1; | |
258 | u32 lateColl: 1; | |
259 | u32 parityErr: 1; | |
260 | u32 complete: 1; | |
261 | u32 halted: 1; | |
262 | } BF_TX_Status; | |
263 | ||
264 | typedef union _TX_Status { | |
265 | u32 ui; | |
266 | BF_TX_Status bf; | |
267 | } TX_Status; | |
268 | ||
269 | /* TX descriptor structure */ | |
270 | typedef struct __TX_FrameDescriptor { | |
271 | volatile FrameDataPtr m_frameDataPtr; | |
272 | TX_Options m_opt; | |
273 | volatile TX_Status m_status; | |
274 | struct __TX_FrameDescriptor *m_nextFD; | |
275 | } TX_FrameDescriptor; | |
276 | ||
277 | /* RX descriptor structure */ | |
278 | typedef struct __RX_FrameDescriptor { | |
279 | volatile FrameDataPtr m_frameDataPtr; | |
280 | u32 m_reserved; | |
281 | volatile RX_Status m_status; | |
282 | struct __RX_FrameDescriptor *m_nextFD; | |
283 | } RX_FrameDescriptor; | |
284 | ||
285 | /* MAC Frame Structure */ | |
286 | typedef struct __MACFrame { | |
287 | u8 m_dstAddr[6] __packed; | |
288 | u8 m_srcAddr[6] __packed; | |
289 | u16 m_lengthOrType __packed; | |
290 | u8 m_payload[1506] __packed; | |
291 | } MACFrame; | |
292 | ||
293 | /* Ethernet Control block */ | |
294 | typedef struct __ETH { | |
295 | TX_FrameDescriptor *m_curTX_FD; /* pointer to current TX frame descriptor */ | |
296 | TX_FrameDescriptor *m_baseTX_FD; /* pointer to base TX frame descriptor */ | |
297 | RX_FrameDescriptor *m_curRX_FD; /* pointer to current RX frame descriptor */ | |
298 | RX_FrameDescriptor *m_baseRX_FD; /* pointer to base RX frame descriptor */ | |
299 | u8 *m_mac; /* pointer to our MAC address */ | |
300 | } ETH; | |
301 | ||
302 | #endif |