projects / thirdparty / kernel / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| f92363d1 | 2 | /* |
| b130b0d5 | 3 | * Copyright 2000-2015 Avago Technologies. All rights reserved. |
| f92363d1 SR |
4 | * |
| 5 | * | |
| 6 | * Name: mpi2_ioc.h | |
| 7 | * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages | |
| 8 | * Creation Date: October 11, 2006 | |
| 9 | * | |
| 4fe6bc97 | 10 | * mpi2_ioc.h Version: 02.00.27 |
| f92363d1 SR |
11 | * |
| 12 | * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 | |
| 13 | * prefix are for use only on MPI v2.5 products, and must not be used | |
| 14 | * with MPI v2.0 products. Unless otherwise noted, names beginning with | |
| 15 | * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. | |
| 16 | * | |
| 17 | * Version History | |
| 18 | * --------------- | |
| 19 | * | |
| 20 | * Date Version Description | |
| 21 | * -------- -------- ------------------------------------------------------ | |
| 22 | * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. | |
| 23 | * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to | |
| 24 | * MaxTargets. | |
| 25 | * Added TotalImageSize field to FWDownload Request. | |
| 26 | * Added reserved words to FWUpload Request. | |
| 27 | * 06-26-07 02.00.02 Added IR Configuration Change List Event. | |
| 28 | * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit | |
| 29 | * request and replaced it with | |
| 30 | * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. | |
| 31 | * Replaced the MinReplyQueueDepth field of the IOCFacts | |
| 32 | * reply with MaxReplyDescriptorPostQueueDepth. | |
| 33 | * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum | |
| 34 | * depth for the Reply Descriptor Post Queue. | |
| 35 | * Added SASAddress field to Initiator Device Table | |
| 36 | * Overflow Event data. | |
| 37 | * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING | |
| 38 | * for SAS Initiator Device Status Change Event data. | |
| 39 | * Modified Reason Code defines for SAS Topology Change | |
| 40 | * List Event data, including adding a bit for PHY Vacant | |
| 41 | * status, and adding a mask for the Reason Code. | |
| 42 | * Added define for | |
| 43 | * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. | |
| 44 | * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. | |
| 45 | * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of | |
| 46 | * the IOCFacts Reply. | |
| 47 | * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. | |
| 48 | * Moved MPI2_VERSION_UNION to mpi2.h. | |
| 49 | * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks | |
| 50 | * instead of enables, and added SASBroadcastPrimitiveMasks | |
| 51 | * field. | |
| 52 | * Added Log Entry Added Event and related structure. | |
| 53 | * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. | |
| 54 | * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. | |
| 55 | * Added MaxVolumes and MaxPersistentEntries fields to | |
| 56 | * IOCFacts reply. | |
| 57 | * Added ProtocalFlags and IOCCapabilities fields to | |
| 58 | * MPI2_FW_IMAGE_HEADER. | |
| 59 | * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. | |
| 60 | * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to | |
| 61 | * a U16 (from a U32). | |
| 62 | * Removed extra 's' from EventMasks name. | |
| 63 | * 06-27-08 02.00.08 Fixed an offset in a comment. | |
| 64 | * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. | |
| 65 | * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and | |
| 66 | * renamed MinReplyFrameSize to ReplyFrameSize. | |
| 67 | * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. | |
| 68 | * Added two new RAIDOperation values for Integrated RAID | |
| 69 | * Operations Status Event data. | |
| 70 | * Added four new IR Configuration Change List Event data | |
| 71 | * ReasonCode values. | |
| 72 | * Added two new ReasonCode defines for SAS Device Status | |
| 73 | * Change Event data. | |
| 74 | * Added three new DiscoveryStatus bits for the SAS | |
| 75 | * Discovery event data. | |
| 76 | * Added Multiplexing Status Change bit to the PhyStatus | |
| 77 | * field of the SAS Topology Change List event data. | |
| 78 | * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. | |
| 79 | * BootFlags are now product-specific. | |
| 80 | * Added defines for the indivdual signature bytes | |
| 81 | * for MPI2_INIT_IMAGE_FOOTER. | |
| 82 | * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. | |
| 83 | * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR | |
| 84 | * define. | |
| 85 | * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE | |
| 86 | * define. | |
| 87 | * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. | |
| 88 | * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. | |
| 89 | * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. | |
| 90 | * Added two new reason codes for SAS Device Status Change | |
| 91 | * Event. | |
| 92 | * Added new event: SAS PHY Counter. | |
| 93 | * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. | |
| 94 | * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. | |
| 95 | * Added new product id family for 2208. | |
| 96 | * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. | |
| 97 | * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. | |
| 98 | * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. | |
| 99 | * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. | |
| 100 | * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. | |
| 101 | * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. | |
| 102 | * Added Host Based Discovery Phy Event data. | |
| 103 | * Added defines for ProductID Product field | |
| 104 | * (MPI2_FW_HEADER_PID_). | |
| 105 | * Modified values for SAS ProductID Family | |
| 106 | * (MPI2_FW_HEADER_PID_FAMILY_). | |
| 107 | * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. | |
| 108 | * Added PowerManagementControl Request structures and | |
| 109 | * defines. | |
| 110 | * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. | |
| 111 | * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. | |
| 112 | * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. | |
| 113 | * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added | |
| 114 | * SASNotifyPrimitiveMasks field to | |
| 115 | * MPI2_EVENT_NOTIFICATION_REQUEST. | |
| 116 | * Added Temperature Threshold Event. | |
| 117 | * Added Host Message Event. | |
| 118 | * Added Send Host Message request and reply. | |
| 119 | * 05-25-11 02.00.18 For Extended Image Header, added | |
| 120 | * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and | |
| 121 | * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines. | |
| 122 | * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define. | |
| 123 | * 08-24-11 02.00.19 Added PhysicalPort field to | |
| 124 | * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure. | |
| 125 | * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete. | |
| 126 | * 11-18-11 02.00.20 Incorporating additions for MPI v2.5. | |
| 127 | * 03-29-12 02.00.21 Added a product specific range to event values. | |
| 17263e75 SR |
128 | * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE. |
| 129 | * Added ElapsedSeconds field to | |
| 130 | * MPI2_EVENT_DATA_IR_OPERATION_STATUS. | |
| 4c8bab4d SR |
131 | * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE |
| 132 | * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY. | |
| 133 | * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE. | |
| 134 | * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. | |
| 135 | * Added Encrypted Hash Extended Image. | |
| a94bea34 | 136 | * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. |
| b130b0d5 | 137 | * 11-18-14 02.00.25 Updated copyright information. |
| 4fe6bc97 C |
138 | * 03-16-15 02.00.26 Updated for MPI v2.6. |
| 139 | * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and | |
| 140 | * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. | |
| 141 | * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and | |
| b130b0d5 SS |
142 | * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. |
| 143 | * Added MPI26_CTRL_OP_SHUTDOWN. | |
| 4fe6bc97 | 144 | * 08-25-15 02.00.27 Added IC ARCH Class based signature defines |
| f92363d1 SR |
145 | * -------------------------------------------------------------------------- |
| 146 | */ | |
| 147 | ||
| 148 | #ifndef MPI2_IOC_H | |
| 149 | #define MPI2_IOC_H | |
| 150 | ||
| 151 | /***************************************************************************** | |
| 152 | * | |
| 153 | * IOC Messages | |
| 154 | * | |
| 155 | *****************************************************************************/ | |
| 156 | ||
| 157 | /**************************************************************************** | |
| 158 | * IOCInit message | |
| 159 | ****************************************************************************/ | |
| 160 | ||
| 161 | /*IOCInit Request message */ | |
| 162 | typedef struct _MPI2_IOC_INIT_REQUEST { | |
| 163 | U8 WhoInit; /*0x00 */ | |
| 164 | U8 Reserved1; /*0x01 */ | |
| 165 | U8 ChainOffset; /*0x02 */ | |
| 166 | U8 Function; /*0x03 */ | |
| 167 | U16 Reserved2; /*0x04 */ | |
| 168 | U8 Reserved3; /*0x06 */ | |
| 169 | U8 MsgFlags; /*0x07 */ | |
| 170 | U8 VP_ID; /*0x08 */ | |
| 171 | U8 VF_ID; /*0x09 */ | |
| 172 | U16 Reserved4; /*0x0A */ | |
| 173 | U16 MsgVersion; /*0x0C */ | |
| 174 | U16 HeaderVersion; /*0x0E */ | |
| 175 | U32 Reserved5; /*0x10 */ | |
| 4fe6bc97 | 176 | U16 ConfigurationFlags; /* 0x14 */ |
| b130b0d5 | 177 | U8 HostPageSize; /*0x16 */ |
| f92363d1 SR |
178 | U8 HostMSIxVectors; /*0x17 */ |
| 179 | U16 Reserved8; /*0x18 */ | |
| 180 | U16 SystemRequestFrameSize; /*0x1A */ | |
| 181 | U16 ReplyDescriptorPostQueueDepth; /*0x1C */ | |
| 182 | U16 ReplyFreeQueueDepth; /*0x1E */ | |
| 183 | U32 SenseBufferAddressHigh; /*0x20 */ | |
| 184 | U32 SystemReplyAddressHigh; /*0x24 */ | |
| 185 | U64 SystemRequestFrameBaseAddress; /*0x28 */ | |
| 186 | U64 ReplyDescriptorPostQueueAddress; /*0x30 */ | |
| 187 | U64 ReplyFreeQueueAddress; /*0x38 */ | |
| 188 | U64 TimeStamp; /*0x40 */ | |
| 189 | } MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST, | |
| 190 | Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t; | |
| 191 | ||
| 192 | /*WhoInit values */ | |
| 193 | #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) | |
| 194 | #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) | |
| 195 | #define MPI2_WHOINIT_ROM_BIOS (0x02) | |
| 196 | #define MPI2_WHOINIT_PCI_PEER (0x03) | |
| 197 | #define MPI2_WHOINIT_HOST_DRIVER (0x04) | |
| 198 | #define MPI2_WHOINIT_MANUFACTURER (0x05) | |
| 199 | ||
| 4c8bab4d SR |
200 | /* MsgFlags */ |
| 201 | #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01) | |
| 202 | ||
| 203 | ||
| f92363d1 SR |
204 | /*MsgVersion */ |
| 205 | #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) | |
| 206 | #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) | |
| 207 | #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) | |
| 208 | #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) | |
| 209 | ||
| 210 | /*HeaderVersion */ | |
| 211 | #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) | |
| 212 | #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) | |
| 213 | #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) | |
| 214 | #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) | |
| 215 | ||
| 4c8bab4d | 216 | /*minimum depth for a Reply Descriptor Post Queue */ |
| f92363d1 SR |
217 | #define MPI2_RDPQ_DEPTH_MIN (16) |
| 218 | ||
| 4c8bab4d SR |
219 | /* Reply Descriptor Post Queue Array Entry */ |
| 220 | typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY { | |
| 221 | U64 RDPQBaseAddress; /* 0x00 */ | |
| 222 | U32 Reserved1; /* 0x08 */ | |
| 223 | U32 Reserved2; /* 0x0C */ | |
| 224 | } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, | |
| 225 | *PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY, | |
| 226 | Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry; | |
| 227 | ||
| 228 | ||
| f92363d1 SR |
229 | /*IOCInit Reply message */ |
| 230 | typedef struct _MPI2_IOC_INIT_REPLY { | |
| 231 | U8 WhoInit; /*0x00 */ | |
| 232 | U8 Reserved1; /*0x01 */ | |
| 233 | U8 MsgLength; /*0x02 */ | |
| 234 | U8 Function; /*0x03 */ | |
| 235 | U16 Reserved2; /*0x04 */ | |
| 236 | U8 Reserved3; /*0x06 */ | |
| 237 | U8 MsgFlags; /*0x07 */ | |
| 238 | U8 VP_ID; /*0x08 */ | |
| 239 | U8 VF_ID; /*0x09 */ | |
| 240 | U16 Reserved4; /*0x0A */ | |
| 241 | U16 Reserved5; /*0x0C */ | |
| 242 | U16 IOCStatus; /*0x0E */ | |
| 243 | U32 IOCLogInfo; /*0x10 */ | |
| 244 | } MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY, | |
| 245 | Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t; | |
| 246 | ||
| 247 | /**************************************************************************** | |
| 248 | * IOCFacts message | |
| 249 | ****************************************************************************/ | |
| 250 | ||
| 251 | /*IOCFacts Request message */ | |
| 252 | typedef struct _MPI2_IOC_FACTS_REQUEST { | |
| 253 | U16 Reserved1; /*0x00 */ | |
| 254 | U8 ChainOffset; /*0x02 */ | |
| 255 | U8 Function; /*0x03 */ | |
| 256 | U16 Reserved2; /*0x04 */ | |
| 257 | U8 Reserved3; /*0x06 */ | |
| 258 | U8 MsgFlags; /*0x07 */ | |
| 259 | U8 VP_ID; /*0x08 */ | |
| 260 | U8 VF_ID; /*0x09 */ | |
| 261 | U16 Reserved4; /*0x0A */ | |
| 262 | } MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST, | |
| 263 | Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t; | |
| 264 | ||
| 265 | /*IOCFacts Reply message */ | |
| 266 | typedef struct _MPI2_IOC_FACTS_REPLY { | |
| 267 | U16 MsgVersion; /*0x00 */ | |
| 268 | U8 MsgLength; /*0x02 */ | |
| 269 | U8 Function; /*0x03 */ | |
| 270 | U16 HeaderVersion; /*0x04 */ | |
| 271 | U8 IOCNumber; /*0x06 */ | |
| 272 | U8 MsgFlags; /*0x07 */ | |
| 273 | U8 VP_ID; /*0x08 */ | |
| 274 | U8 VF_ID; /*0x09 */ | |
| 275 | U16 Reserved1; /*0x0A */ | |
| 276 | U16 IOCExceptions; /*0x0C */ | |
| 277 | U16 IOCStatus; /*0x0E */ | |
| 278 | U32 IOCLogInfo; /*0x10 */ | |
| 279 | U8 MaxChainDepth; /*0x14 */ | |
| 280 | U8 WhoInit; /*0x15 */ | |
| 281 | U8 NumberOfPorts; /*0x16 */ | |
| 282 | U8 MaxMSIxVectors; /*0x17 */ | |
| 283 | U16 RequestCredit; /*0x18 */ | |
| 284 | U16 ProductID; /*0x1A */ | |
| 285 | U32 IOCCapabilities; /*0x1C */ | |
| 286 | MPI2_VERSION_UNION FWVersion; /*0x20 */ | |
| 287 | U16 IOCRequestFrameSize; /*0x24 */ | |
| 288 | U16 IOCMaxChainSegmentSize; /*0x26 */ | |
| 289 | U16 MaxInitiators; /*0x28 */ | |
| 290 | U16 MaxTargets; /*0x2A */ | |
| 291 | U16 MaxSasExpanders; /*0x2C */ | |
| 292 | U16 MaxEnclosures; /*0x2E */ | |
| 293 | U16 ProtocolFlags; /*0x30 */ | |
| 294 | U16 HighPriorityCredit; /*0x32 */ | |
| 295 | U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */ | |
| 296 | U8 ReplyFrameSize; /*0x36 */ | |
| 297 | U8 MaxVolumes; /*0x37 */ | |
| 298 | U16 MaxDevHandle; /*0x38 */ | |
| 299 | U16 MaxPersistentEntries; /*0x3A */ | |
| 300 | U16 MinDevHandle; /*0x3C */ | |
| b130b0d5 SS |
301 | U8 CurrentHostPageSize; /* 0x3E */ |
| 302 | U8 Reserved4; /* 0x3F */ | |
| f92363d1 SR |
303 | } MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY, |
| 304 | Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t; | |
| 305 | ||
| 306 | /*MsgVersion */ | |
| 307 | #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) | |
| 308 | #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) | |
| 309 | #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) | |
| 310 | #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) | |
| 311 | ||
| 312 | /*HeaderVersion */ | |
| 313 | #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) | |
| 314 | #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) | |
| 315 | #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) | |
| 316 | #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) | |
| 317 | ||
| 318 | /*IOCExceptions */ | |
| 17263e75 | 319 | #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) |
| f92363d1 SR |
320 | #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) |
| 321 | ||
| 322 | #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) | |
| 323 | #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) | |
| 324 | #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) | |
| 325 | #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) | |
| 326 | #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) | |
| 327 | ||
| 328 | #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) | |
| 329 | #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) | |
| 330 | #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) | |
| 331 | #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) | |
| 332 | #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) | |
| 333 | ||
| 334 | /*defines for WhoInit field are after the IOCInit Request */ | |
| 335 | ||
| 336 | /*ProductID field uses MPI2_FW_HEADER_PID_ */ | |
| 337 | ||
| 338 | /*IOCCapabilities */ | |
| b130b0d5 | 339 | #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) |
| 4c8bab4d | 340 | #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) |
| f92363d1 SR |
341 | #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) |
| 342 | #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) | |
| 343 | #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) | |
| 344 | #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) | |
| 345 | #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) | |
| 346 | #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) | |
| 347 | #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) | |
| 348 | #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) | |
| 349 | #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) | |
| 350 | #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) | |
| 351 | #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) | |
| 352 | #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) | |
| 353 | #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) | |
| 354 | #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) | |
| 355 | ||
| 356 | /*ProtocolFlags */ | |
| f92363d1 | 357 | #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) |
| b130b0d5 | 358 | #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) |
| f92363d1 SR |
359 | |
| 360 | /**************************************************************************** | |
| 361 | * PortFacts message | |
| 362 | ****************************************************************************/ | |
| 363 | ||
| 364 | /*PortFacts Request message */ | |
| 365 | typedef struct _MPI2_PORT_FACTS_REQUEST { | |
| 366 | U16 Reserved1; /*0x00 */ | |
| 367 | U8 ChainOffset; /*0x02 */ | |
| 368 | U8 Function; /*0x03 */ | |
| 369 | U16 Reserved2; /*0x04 */ | |
| 370 | U8 PortNumber; /*0x06 */ | |
| 371 | U8 MsgFlags; /*0x07 */ | |
| 372 | U8 VP_ID; /*0x08 */ | |
| 373 | U8 VF_ID; /*0x09 */ | |
| 374 | U16 Reserved3; /*0x0A */ | |
| 375 | } MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST, | |
| 376 | Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t; | |
| 377 | ||
| 378 | /*PortFacts Reply message */ | |
| 379 | typedef struct _MPI2_PORT_FACTS_REPLY { | |
| 380 | U16 Reserved1; /*0x00 */ | |
| 381 | U8 MsgLength; /*0x02 */ | |
| 382 | U8 Function; /*0x03 */ | |
| 383 | U16 Reserved2; /*0x04 */ | |
| 384 | U8 PortNumber; /*0x06 */ | |
| 385 | U8 MsgFlags; /*0x07 */ | |
| 386 | U8 VP_ID; /*0x08 */ | |
| 387 | U8 VF_ID; /*0x09 */ | |
| 388 | U16 Reserved3; /*0x0A */ | |
| 389 | U16 Reserved4; /*0x0C */ | |
| 390 | U16 IOCStatus; /*0x0E */ | |
| 391 | U32 IOCLogInfo; /*0x10 */ | |
| 392 | U8 Reserved5; /*0x14 */ | |
| 393 | U8 PortType; /*0x15 */ | |
| 394 | U16 Reserved6; /*0x16 */ | |
| 395 | U16 MaxPostedCmdBuffers; /*0x18 */ | |
| 396 | U16 Reserved7; /*0x1A */ | |
| 397 | } MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY, | |
| 398 | Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t; | |
| 399 | ||
| 400 | /*PortType values */ | |
| 401 | #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) | |
| 402 | #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) | |
| 403 | #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) | |
| 404 | #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) | |
| 405 | #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) | |
| 406 | ||
| 407 | /**************************************************************************** | |
| 408 | * PortEnable message | |
| 409 | ****************************************************************************/ | |
| 410 | ||
| 411 | /*PortEnable Request message */ | |
| 412 | typedef struct _MPI2_PORT_ENABLE_REQUEST { | |
| 413 | U16 Reserved1; /*0x00 */ | |
| 414 | U8 ChainOffset; /*0x02 */ | |
| 415 | U8 Function; /*0x03 */ | |
| 416 | U8 Reserved2; /*0x04 */ | |
| 417 | U8 PortFlags; /*0x05 */ | |
| 418 | U8 Reserved3; /*0x06 */ | |
| 419 | U8 MsgFlags; /*0x07 */ | |
| 420 | U8 VP_ID; /*0x08 */ | |
| 421 | U8 VF_ID; /*0x09 */ | |
| 422 | U16 Reserved4; /*0x0A */ | |
| 423 | } MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST, | |
| 424 | Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t; | |
| 425 | ||
| 426 | /*PortEnable Reply message */ | |
| 427 | typedef struct _MPI2_PORT_ENABLE_REPLY { | |
| 428 | U16 Reserved1; /*0x00 */ | |
| 429 | U8 MsgLength; /*0x02 */ | |
| 430 | U8 Function; /*0x03 */ | |
| 431 | U8 Reserved2; /*0x04 */ | |
| 432 | U8 PortFlags; /*0x05 */ | |
| 433 | U8 Reserved3; /*0x06 */ | |
| 434 | U8 MsgFlags; /*0x07 */ | |
| 435 | U8 VP_ID; /*0x08 */ | |
| 436 | U8 VF_ID; /*0x09 */ | |
| 437 | U16 Reserved4; /*0x0A */ | |
| 438 | U16 Reserved5; /*0x0C */ | |
| 439 | U16 IOCStatus; /*0x0E */ | |
| 440 | U32 IOCLogInfo; /*0x10 */ | |
| 441 | } MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY, | |
| 442 | Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t; | |
| 443 | ||
| 444 | /**************************************************************************** | |
| 445 | * EventNotification message | |
| 446 | ****************************************************************************/ | |
| 447 | ||
| 448 | /*EventNotification Request message */ | |
| 449 | #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) | |
| 450 | ||
| 451 | typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST { | |
| 452 | U16 Reserved1; /*0x00 */ | |
| 453 | U8 ChainOffset; /*0x02 */ | |
| 454 | U8 Function; /*0x03 */ | |
| 455 | U16 Reserved2; /*0x04 */ | |
| 456 | U8 Reserved3; /*0x06 */ | |
| 457 | U8 MsgFlags; /*0x07 */ | |
| 458 | U8 VP_ID; /*0x08 */ | |
| 459 | U8 VF_ID; /*0x09 */ | |
| 460 | U16 Reserved4; /*0x0A */ | |
| 461 | U32 Reserved5; /*0x0C */ | |
| 462 | U32 Reserved6; /*0x10 */ | |
| 463 | U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */ | |
| 464 | U16 SASBroadcastPrimitiveMasks; /*0x24 */ | |
| 465 | U16 SASNotifyPrimitiveMasks; /*0x26 */ | |
| 466 | U32 Reserved8; /*0x28 */ | |
| 467 | } MPI2_EVENT_NOTIFICATION_REQUEST, | |
| 468 | *PTR_MPI2_EVENT_NOTIFICATION_REQUEST, | |
| 469 | Mpi2EventNotificationRequest_t, | |
| 470 | *pMpi2EventNotificationRequest_t; | |
| 471 | ||
| 472 | /*EventNotification Reply message */ | |
| 473 | typedef struct _MPI2_EVENT_NOTIFICATION_REPLY { | |
| 474 | U16 EventDataLength; /*0x00 */ | |
| 475 | U8 MsgLength; /*0x02 */ | |
| 476 | U8 Function; /*0x03 */ | |
| 477 | U16 Reserved1; /*0x04 */ | |
| 478 | U8 AckRequired; /*0x06 */ | |
| 479 | U8 MsgFlags; /*0x07 */ | |
| 480 | U8 VP_ID; /*0x08 */ | |
| 481 | U8 VF_ID; /*0x09 */ | |
| 482 | U16 Reserved2; /*0x0A */ | |
| 483 | U16 Reserved3; /*0x0C */ | |
| 484 | U16 IOCStatus; /*0x0E */ | |
| 485 | U32 IOCLogInfo; /*0x10 */ | |
| 486 | U16 Event; /*0x14 */ | |
| 487 | U16 Reserved4; /*0x16 */ | |
| 488 | U32 EventContext; /*0x18 */ | |
| 489 | U32 EventData[1]; /*0x1C */ | |
| 490 | } MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY, | |
| 491 | Mpi2EventNotificationReply_t, | |
| 492 | *pMpi2EventNotificationReply_t; | |
| 493 | ||
| 494 | /*AckRequired */ | |
| 495 | #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) | |
| 496 | #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) | |
| 497 | ||
| 498 | /*Event */ | |
| 499 | #define MPI2_EVENT_LOG_DATA (0x0001) | |
| 500 | #define MPI2_EVENT_STATE_CHANGE (0x0002) | |
| 501 | #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) | |
| 502 | #define MPI2_EVENT_EVENT_CHANGE (0x000A) | |
| 503 | #define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */ | |
| 504 | #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) | |
| 505 | #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) | |
| 506 | #define MPI2_EVENT_SAS_DISCOVERY (0x0016) | |
| 507 | #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) | |
| 508 | #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) | |
| 509 | #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) | |
| 510 | #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) | |
| 511 | #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) | |
| 512 | #define MPI2_EVENT_IR_VOLUME (0x001E) | |
| 513 | #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) | |
| 514 | #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) | |
| 515 | #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) | |
| 516 | #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) | |
| 517 | #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) | |
| 518 | #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) | |
| 519 | #define MPI2_EVENT_SAS_QUIESCE (0x0025) | |
| 520 | #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026) | |
| 521 | #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) | |
| 522 | #define MPI2_EVENT_HOST_MESSAGE (0x0028) | |
| 523 | #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) | |
| 4fe6bc97 | 524 | #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) |
| f92363d1 SR |
525 | #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) |
| 526 | #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) | |
| 527 | ||
| 528 | /*Log Entry Added Event data */ | |
| 529 | ||
| 530 | /*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ | |
| 531 | #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) | |
| 532 | ||
| 533 | typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED { | |
| 534 | U64 TimeStamp; /*0x00 */ | |
| 535 | U32 Reserved1; /*0x08 */ | |
| 536 | U16 LogSequence; /*0x0C */ | |
| 537 | U16 LogEntryQualifier; /*0x0E */ | |
| 538 | U8 VP_ID; /*0x10 */ | |
| 539 | U8 VF_ID; /*0x11 */ | |
| 540 | U16 Reserved2; /*0x12 */ | |
| 541 | U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */ | |
| 542 | } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, | |
| 543 | *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, | |
| 544 | Mpi2EventDataLogEntryAdded_t, | |
| 545 | *pMpi2EventDataLogEntryAdded_t; | |
| 546 | ||
| 547 | /*GPIO Interrupt Event data */ | |
| 548 | ||
| 549 | typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT { | |
| 550 | U8 GPIONum; /*0x00 */ | |
| 551 | U8 Reserved1; /*0x01 */ | |
| 552 | U16 Reserved2; /*0x02 */ | |
| 553 | } MPI2_EVENT_DATA_GPIO_INTERRUPT, | |
| 554 | *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, | |
| 555 | Mpi2EventDataGpioInterrupt_t, | |
| 556 | *pMpi2EventDataGpioInterrupt_t; | |
| 557 | ||
| 558 | /*Temperature Threshold Event data */ | |
| 559 | ||
| 560 | typedef struct _MPI2_EVENT_DATA_TEMPERATURE { | |
| 561 | U16 Status; /*0x00 */ | |
| 562 | U8 SensorNum; /*0x02 */ | |
| 563 | U8 Reserved1; /*0x03 */ | |
| 564 | U16 CurrentTemperature; /*0x04 */ | |
| 565 | U16 Reserved2; /*0x06 */ | |
| 566 | U32 Reserved3; /*0x08 */ | |
| 567 | U32 Reserved4; /*0x0C */ | |
| 568 | } MPI2_EVENT_DATA_TEMPERATURE, | |
| 569 | *PTR_MPI2_EVENT_DATA_TEMPERATURE, | |
| 570 | Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t; | |
| 571 | ||
| 572 | /*Temperature Threshold Event data Status bits */ | |
| 573 | #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008) | |
| 574 | #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004) | |
| 575 | #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002) | |
| 576 | #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001) | |
| 577 | ||
| 578 | /*Host Message Event data */ | |
| 579 | ||
| 580 | typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE { | |
| 581 | U8 SourceVF_ID; /*0x00 */ | |
| 582 | U8 Reserved1; /*0x01 */ | |
| 583 | U16 Reserved2; /*0x02 */ | |
| 584 | U32 Reserved3; /*0x04 */ | |
| 585 | U32 HostData[1]; /*0x08 */ | |
| 586 | } MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE, | |
| 587 | Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t; | |
| 588 | ||
| 4fe6bc97 | 589 | /*Power Performance Change Event data */ |
| f92363d1 SR |
590 | |
| 591 | typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE { | |
| 592 | U8 CurrentPowerMode; /*0x00 */ | |
| 593 | U8 PreviousPowerMode; /*0x01 */ | |
| 594 | U16 Reserved1; /*0x02 */ | |
| 595 | } MPI2_EVENT_DATA_POWER_PERF_CHANGE, | |
| 596 | *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE, | |
| 597 | Mpi2EventDataPowerPerfChange_t, | |
| 598 | *pMpi2EventDataPowerPerfChange_t; | |
| 599 | ||
| 600 | /*defines for CurrentPowerMode and PreviousPowerMode fields */ | |
| 601 | #define MPI2_EVENT_PM_INIT_MASK (0xC0) | |
| 602 | #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00) | |
| 603 | #define MPI2_EVENT_PM_INIT_HOST (0x40) | |
| 604 | #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80) | |
| 605 | #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0) | |
| 606 | ||
| 607 | #define MPI2_EVENT_PM_MODE_MASK (0x07) | |
| 608 | #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00) | |
| 609 | #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01) | |
| 610 | #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04) | |
| 611 | #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05) | |
| 612 | #define MPI2_EVENT_PM_MODE_STANDBY (0x06) | |
| 613 | ||
| 4fe6bc97 C |
614 | /* Active Cable Exception Event data */ |
| 615 | ||
| 616 | typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT { | |
| 617 | U32 ActiveCablePowerRequirement; /* 0x00 */ | |
| 618 | U8 ReasonCode; /* 0x04 */ | |
| 619 | U8 ReceptacleID; /* 0x05 */ | |
| 620 | U16 Reserved1; /* 0x06 */ | |
| 621 | } MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, | |
| 622 | *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, | |
| 623 | Mpi26EventDataActiveCableExcept_t, | |
| 624 | *pMpi26EventDataActiveCableExcept_t; | |
| 625 | ||
| 626 | /* defines for ReasonCode field */ | |
| 627 | #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) | |
| 6c44c0fe C |
628 | #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) |
| 629 | #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) | |
| 4fe6bc97 | 630 | |
| f92363d1 SR |
631 | /*Hard Reset Received Event data */ |
| 632 | ||
| 633 | typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED { | |
| 634 | U8 Reserved1; /*0x00 */ | |
| 635 | U8 Port; /*0x01 */ | |
| 636 | U16 Reserved2; /*0x02 */ | |
| 637 | } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, | |
| 638 | *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, | |
| 639 | Mpi2EventDataHardResetReceived_t, | |
| 640 | *pMpi2EventDataHardResetReceived_t; | |
| 641 | ||
| 642 | /*Task Set Full Event data */ | |
| 643 | /* this event is obsolete */ | |
| 644 | ||
| 645 | typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL { | |
| 646 | U16 DevHandle; /*0x00 */ | |
| 647 | U16 CurrentDepth; /*0x02 */ | |
| 648 | } MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL, | |
| 649 | Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t; | |
| 650 | ||
| 651 | /*SAS Device Status Change Event data */ | |
| 652 | ||
| 653 | typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE { | |
| 654 | U16 TaskTag; /*0x00 */ | |
| 655 | U8 ReasonCode; /*0x02 */ | |
| 656 | U8 PhysicalPort; /*0x03 */ | |
| 657 | U8 ASC; /*0x04 */ | |
| 658 | U8 ASCQ; /*0x05 */ | |
| 659 | U16 DevHandle; /*0x06 */ | |
| 660 | U32 Reserved2; /*0x08 */ | |
| 661 | U64 SASAddress; /*0x0C */ | |
| 662 | U8 LUN[8]; /*0x14 */ | |
| 663 | } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, | |
| 664 | *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, | |
| 665 | Mpi2EventDataSasDeviceStatusChange_t, | |
| 666 | *pMpi2EventDataSasDeviceStatusChange_t; | |
| 667 | ||
| 668 | /*SAS Device Status Change Event data ReasonCode values */ | |
| 669 | #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) | |
| 670 | #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) | |
| 671 | #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) | |
| 672 | #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) | |
| 673 | #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) | |
| 674 | #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) | |
| 675 | #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) | |
| 676 | #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) | |
| 677 | #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) | |
| 678 | #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) | |
| 679 | #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) | |
| 680 | #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) | |
| 681 | #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) | |
| 682 | ||
| 683 | /*Integrated RAID Operation Status Event data */ | |
| 684 | ||
| 685 | typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS { | |
| 686 | U16 VolDevHandle; /*0x00 */ | |
| 687 | U16 Reserved1; /*0x02 */ | |
| 688 | U8 RAIDOperation; /*0x04 */ | |
| 689 | U8 PercentComplete; /*0x05 */ | |
| 690 | U16 Reserved2; /*0x06 */ | |
| 17263e75 | 691 | U32 ElapsedSeconds; /*0x08 */ |
| f92363d1 SR |
692 | } MPI2_EVENT_DATA_IR_OPERATION_STATUS, |
| 693 | *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, | |
| 694 | Mpi2EventDataIrOperationStatus_t, | |
| 695 | *pMpi2EventDataIrOperationStatus_t; | |
| 696 | ||
| 697 | /*Integrated RAID Operation Status Event data RAIDOperation values */ | |
| 698 | #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) | |
| 699 | #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) | |
| 700 | #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) | |
| 701 | #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) | |
| 702 | #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) | |
| 703 | ||
| 704 | /*Integrated RAID Volume Event data */ | |
| 705 | ||
| 706 | typedef struct _MPI2_EVENT_DATA_IR_VOLUME { | |
| 707 | U16 VolDevHandle; /*0x00 */ | |
| 708 | U8 ReasonCode; /*0x02 */ | |
| 709 | U8 Reserved1; /*0x03 */ | |
| 710 | U32 NewValue; /*0x04 */ | |
| 711 | U32 PreviousValue; /*0x08 */ | |
| 712 | } MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME, | |
| 713 | Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t; | |
| 714 | ||
| 715 | /*Integrated RAID Volume Event data ReasonCode values */ | |
| 716 | #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) | |
| 717 | #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) | |
| 718 | #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) | |
| 719 | ||
| 720 | /*Integrated RAID Physical Disk Event data */ | |
| 721 | ||
| 722 | typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK { | |
| 723 | U16 Reserved1; /*0x00 */ | |
| 724 | U8 ReasonCode; /*0x02 */ | |
| 725 | U8 PhysDiskNum; /*0x03 */ | |
| 726 | U16 PhysDiskDevHandle; /*0x04 */ | |
| 727 | U16 Reserved2; /*0x06 */ | |
| 728 | U16 Slot; /*0x08 */ | |
| 729 | U16 EnclosureHandle; /*0x0A */ | |
| 730 | U32 NewValue; /*0x0C */ | |
| 731 | U32 PreviousValue; /*0x10 */ | |
| 732 | } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, | |
| 733 | *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, | |
| 734 | Mpi2EventDataIrPhysicalDisk_t, | |
| 735 | *pMpi2EventDataIrPhysicalDisk_t; | |
| 736 | ||
| 737 | /*Integrated RAID Physical Disk Event data ReasonCode values */ | |
| 738 | #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) | |
| 739 | #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) | |
| 740 | #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) | |
| 741 | ||
| 742 | /*Integrated RAID Configuration Change List Event data */ | |
| 743 | ||
| 744 | /* | |
| 745 | *Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |
| 746 | *one and check NumElements at runtime. | |
| 747 | */ | |
| 748 | #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT | |
| 749 | #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) | |
| 750 | #endif | |
| 751 | ||
| 752 | typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT { | |
| 753 | U16 ElementFlags; /*0x00 */ | |
| 754 | U16 VolDevHandle; /*0x02 */ | |
| 755 | U8 ReasonCode; /*0x04 */ | |
| 756 | U8 PhysDiskNum; /*0x05 */ | |
| 757 | U16 PhysDiskDevHandle; /*0x06 */ | |
| 758 | } MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, | |
| 759 | Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t; | |
| 760 | ||
| 761 | /*IR Configuration Change List Event data ElementFlags values */ | |
| 762 | #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) | |
| 763 | #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) | |
| 764 | #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) | |
| 765 | #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) | |
| 766 | ||
| 767 | /*IR Configuration Change List Event data ReasonCode values */ | |
| 768 | #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) | |
| 769 | #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) | |
| 770 | #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) | |
| 771 | #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) | |
| 772 | #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) | |
| 773 | #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) | |
| 774 | #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) | |
| 775 | #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) | |
| 776 | #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) | |
| 777 | ||
| 778 | typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST { | |
| 779 | U8 NumElements; /*0x00 */ | |
| 780 | U8 Reserved1; /*0x01 */ | |
| 781 | U8 Reserved2; /*0x02 */ | |
| 782 | U8 ConfigNum; /*0x03 */ | |
| 783 | U32 Flags; /*0x04 */ | |
| 784 | MPI2_EVENT_IR_CONFIG_ELEMENT | |
| 785 | ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */ | |
| 786 | } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, | |
| 787 | *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, | |
| 788 | Mpi2EventDataIrConfigChangeList_t, | |
| 789 | *pMpi2EventDataIrConfigChangeList_t; | |
| 790 | ||
| 791 | /*IR Configuration Change List Event data Flags values */ | |
| 792 | #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) | |
| 793 | ||
| 794 | /*SAS Discovery Event data */ | |
| 795 | ||
| 796 | typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY { | |
| 797 | U8 Flags; /*0x00 */ | |
| 798 | U8 ReasonCode; /*0x01 */ | |
| 799 | U8 PhysicalPort; /*0x02 */ | |
| 800 | U8 Reserved1; /*0x03 */ | |
| 801 | U32 DiscoveryStatus; /*0x04 */ | |
| 802 | } MPI2_EVENT_DATA_SAS_DISCOVERY, | |
| 803 | *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, | |
| 804 | Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t; | |
| 805 | ||
| 806 | /*SAS Discovery Event data Flags values */ | |
| 807 | #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) | |
| 808 | #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) | |
| 809 | ||
| 810 | /*SAS Discovery Event data ReasonCode values */ | |
| 811 | #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) | |
| 812 | #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) | |
| 813 | ||
| 814 | /*SAS Discovery Event data DiscoveryStatus values */ | |
| 815 | #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) | |
| 816 | #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) | |
| 817 | #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) | |
| 818 | #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) | |
| 819 | #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) | |
| 820 | #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) | |
| 821 | #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) | |
| 822 | #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) | |
| 823 | #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) | |
| 824 | #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) | |
| 825 | #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) | |
| 826 | #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) | |
| 827 | #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) | |
| 828 | #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) | |
| 829 | #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) | |
| 830 | #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) | |
| 831 | #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) | |
| 832 | #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) | |
| 833 | #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) | |
| 834 | #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) | |
| 835 | ||
| 836 | /*SAS Broadcast Primitive Event data */ | |
| 837 | ||
| 838 | typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE { | |
| 839 | U8 PhyNum; /*0x00 */ | |
| 840 | U8 Port; /*0x01 */ | |
| 841 | U8 PortWidth; /*0x02 */ | |
| 842 | U8 Primitive; /*0x03 */ | |
| 843 | } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, | |
| 844 | *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, | |
| 845 | Mpi2EventDataSasBroadcastPrimitive_t, | |
| 846 | *pMpi2EventDataSasBroadcastPrimitive_t; | |
| 847 | ||
| 848 | /*defines for the Primitive field */ | |
| 849 | #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) | |
| 850 | #define MPI2_EVENT_PRIMITIVE_SES (0x02) | |
| 851 | #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) | |
| 852 | #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) | |
| 853 | #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) | |
| 854 | #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) | |
| 855 | #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) | |
| 856 | #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) | |
| 857 | ||
| 858 | /*SAS Notify Primitive Event data */ | |
| 859 | ||
| 860 | typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE { | |
| 861 | U8 PhyNum; /*0x00 */ | |
| 862 | U8 Port; /*0x01 */ | |
| 863 | U8 Reserved1; /*0x02 */ | |
| 864 | U8 Primitive; /*0x03 */ | |
| 865 | } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, | |
| 866 | *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE, | |
| 867 | Mpi2EventDataSasNotifyPrimitive_t, | |
| 868 | *pMpi2EventDataSasNotifyPrimitive_t; | |
| 869 | ||
| 870 | /*defines for the Primitive field */ | |
| 871 | #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01) | |
| 872 | #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02) | |
| 873 | #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03) | |
| 874 | #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04) | |
| 875 | ||
| 876 | /*SAS Initiator Device Status Change Event data */ | |
| 877 | ||
| 878 | typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE { | |
| 879 | U8 ReasonCode; /*0x00 */ | |
| 880 | U8 PhysicalPort; /*0x01 */ | |
| 881 | U16 DevHandle; /*0x02 */ | |
| 882 | U64 SASAddress; /*0x04 */ | |
| 883 | } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, | |
| 884 | *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, | |
| 885 | Mpi2EventDataSasInitDevStatusChange_t, | |
| 886 | *pMpi2EventDataSasInitDevStatusChange_t; | |
| 887 | ||
| 888 | /*SAS Initiator Device Status Change event ReasonCode values */ | |
| 889 | #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) | |
| 890 | #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) | |
| 891 | ||
| 892 | /*SAS Initiator Device Table Overflow Event data */ | |
| 893 | ||
| 894 | typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW { | |
| 895 | U16 MaxInit; /*0x00 */ | |
| 896 | U16 CurrentInit; /*0x02 */ | |
| 897 | U64 SASAddress; /*0x04 */ | |
| 898 | } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, | |
| 899 | *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, | |
| 900 | Mpi2EventDataSasInitTableOverflow_t, | |
| 901 | *pMpi2EventDataSasInitTableOverflow_t; | |
| 902 | ||
| 903 | /*SAS Topology Change List Event data */ | |
| 904 | ||
| 905 | /* | |
| 906 | *Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |
| 907 | *one and check NumEntries at runtime. | |
| 908 | */ | |
| 909 | #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT | |
| 910 | #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) | |
| 911 | #endif | |
| 912 | ||
| 913 | typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY { | |
| 914 | U16 AttachedDevHandle; /*0x00 */ | |
| 915 | U8 LinkRate; /*0x02 */ | |
| 916 | U8 PhyStatus; /*0x03 */ | |
| 917 | } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, | |
| 918 | Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t; | |
| 919 | ||
| 920 | typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST { | |
| 921 | U16 EnclosureHandle; /*0x00 */ | |
| 922 | U16 ExpanderDevHandle; /*0x02 */ | |
| 923 | U8 NumPhys; /*0x04 */ | |
| 924 | U8 Reserved1; /*0x05 */ | |
| 925 | U16 Reserved2; /*0x06 */ | |
| 926 | U8 NumEntries; /*0x08 */ | |
| 927 | U8 StartPhyNum; /*0x09 */ | |
| 928 | U8 ExpStatus; /*0x0A */ | |
| 929 | U8 PhysicalPort; /*0x0B */ | |
| 930 | MPI2_EVENT_SAS_TOPO_PHY_ENTRY | |
| 931 | PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */ | |
| 932 | } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, | |
| 933 | *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, | |
| 934 | Mpi2EventDataSasTopologyChangeList_t, | |
| 935 | *pMpi2EventDataSasTopologyChangeList_t; | |
| 936 | ||
| 937 | /*values for the ExpStatus field */ | |
| 938 | #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) | |
| 939 | #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) | |
| 940 | #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) | |
| 941 | #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) | |
| 942 | #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) | |
| 943 | ||
| 944 | /*defines for the LinkRate field */ | |
| 945 | #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) | |
| 946 | #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) | |
| 947 | #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) | |
| 948 | #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) | |
| 949 | ||
| 950 | #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) | |
| 951 | #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) | |
| 952 | #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) | |
| 953 | #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) | |
| 954 | #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) | |
| 955 | #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) | |
| 956 | #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) | |
| 957 | #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) | |
| 958 | #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) | |
| 959 | #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) | |
| 960 | #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) | |
| 961 | ||
| 962 | /*values for the PhyStatus field */ | |
| 963 | #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) | |
| 964 | #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) | |
| 965 | /*values for the PhyStatus ReasonCode sub-field */ | |
| 966 | #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) | |
| 967 | #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) | |
| 968 | #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) | |
| 969 | #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) | |
| 970 | #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) | |
| 971 | #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) | |
| 972 | ||
| 973 | /*SAS Enclosure Device Status Change Event data */ | |
| 974 | ||
| 975 | typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE { | |
| 976 | U16 EnclosureHandle; /*0x00 */ | |
| 977 | U8 ReasonCode; /*0x02 */ | |
| 978 | U8 PhysicalPort; /*0x03 */ | |
| 979 | U64 EnclosureLogicalID; /*0x04 */ | |
| 980 | U16 NumSlots; /*0x0C */ | |
| 981 | U16 StartSlot; /*0x0E */ | |
| 982 | U32 PhyBits; /*0x10 */ | |
| 983 | } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, | |
| 984 | *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, | |
| 985 | Mpi2EventDataSasEnclDevStatusChange_t, | |
| 986 | *pMpi2EventDataSasEnclDevStatusChange_t; | |
| 987 | ||
| 988 | /*SAS Enclosure Device Status Change event ReasonCode values */ | |
| 989 | #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) | |
| 990 | #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) | |
| 991 | ||
| 992 | /*SAS PHY Counter Event data */ | |
| 993 | ||
| 994 | typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER { | |
| 995 | U64 TimeStamp; /*0x00 */ | |
| 996 | U32 Reserved1; /*0x08 */ | |
| 997 | U8 PhyEventCode; /*0x0C */ | |
| 998 | U8 PhyNum; /*0x0D */ | |
| 999 | U16 Reserved2; /*0x0E */ | |
| 1000 | U32 PhyEventInfo; /*0x10 */ | |
| 1001 | U8 CounterType; /*0x14 */ | |
| 1002 | U8 ThresholdWindow; /*0x15 */ | |
| 1003 | U8 TimeUnits; /*0x16 */ | |
| 1004 | U8 Reserved3; /*0x17 */ | |
| 1005 | U32 EventThreshold; /*0x18 */ | |
| 1006 | U16 ThresholdFlags; /*0x1C */ | |
| 1007 | U16 Reserved4; /*0x1E */ | |
| 1008 | } MPI2_EVENT_DATA_SAS_PHY_COUNTER, | |
| 1009 | *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, | |
| 1010 | Mpi2EventDataSasPhyCounter_t, | |
| 1011 | *pMpi2EventDataSasPhyCounter_t; | |
| 1012 | ||
| 1013 | /*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h | |
| 1014 | *for the PhyEventCode field */ | |
| 1015 | ||
| 1016 | /*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h | |
| 1017 | *for the CounterType field */ | |
| 1018 | ||
| 1019 | /*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h | |
| 1020 | *for the TimeUnits field */ | |
| 1021 | ||
| 1022 | /*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h | |
| 1023 | *for the ThresholdFlags field */ | |
| 1024 | ||
| 1025 | /*SAS Quiesce Event data */ | |
| 1026 | ||
| 1027 | typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE { | |
| 1028 | U8 ReasonCode; /*0x00 */ | |
| 1029 | U8 Reserved1; /*0x01 */ | |
| 1030 | U16 Reserved2; /*0x02 */ | |
| 1031 | U32 Reserved3; /*0x04 */ | |
| 1032 | } MPI2_EVENT_DATA_SAS_QUIESCE, | |
| 1033 | *PTR_MPI2_EVENT_DATA_SAS_QUIESCE, | |
| 1034 | Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t; | |
| 1035 | ||
| 1036 | /*SAS Quiesce Event data ReasonCode values */ | |
| 1037 | #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) | |
| 1038 | #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) | |
| 1039 | ||
| 1040 | /*Host Based Discovery Phy Event data */ | |
| 1041 | ||
| 1042 | typedef struct _MPI2_EVENT_HBD_PHY_SAS { | |
| 1043 | U8 Flags; /*0x00 */ | |
| 1044 | U8 NegotiatedLinkRate; /*0x01 */ | |
| 1045 | U8 PhyNum; /*0x02 */ | |
| 1046 | U8 PhysicalPort; /*0x03 */ | |
| 1047 | U32 Reserved1; /*0x04 */ | |
| 1048 | U8 InitialFrame[28]; /*0x08 */ | |
| 1049 | } MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS, | |
| 1050 | Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t; | |
| 1051 | ||
| 1052 | /*values for the Flags field */ | |
| 1053 | #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) | |
| 1054 | #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) | |
| 1055 | ||
| 1056 | /*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h | |
| 1057 | *for the NegotiatedLinkRate field */ | |
| 1058 | ||
| 1059 | typedef union _MPI2_EVENT_HBD_DESCRIPTOR { | |
| 1060 | MPI2_EVENT_HBD_PHY_SAS Sas; | |
| 1061 | } MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR, | |
| 1062 | Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t; | |
| 1063 | ||
| 1064 | typedef struct _MPI2_EVENT_DATA_HBD_PHY { | |
| 1065 | U8 DescriptorType; /*0x00 */ | |
| 1066 | U8 Reserved1; /*0x01 */ | |
| 1067 | U16 Reserved2; /*0x02 */ | |
| 1068 | U32 Reserved3; /*0x04 */ | |
| 1069 | MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */ | |
| 1070 | } MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY, | |
| 1071 | Mpi2EventDataHbdPhy_t, | |
| 1072 | *pMpi2EventDataMpi2EventDataHbdPhy_t; | |
| 1073 | ||
| 1074 | /*values for the DescriptorType field */ | |
| 1075 | #define MPI2_EVENT_HBD_DT_SAS (0x01) | |
| 1076 | ||
| 1077 | /**************************************************************************** | |
| 1078 | * EventAck message | |
| 1079 | ****************************************************************************/ | |
| 1080 | ||
| 1081 | /*EventAck Request message */ | |
| 1082 | typedef struct _MPI2_EVENT_ACK_REQUEST { | |
| 1083 | U16 Reserved1; /*0x00 */ | |
| 1084 | U8 ChainOffset; /*0x02 */ | |
| 1085 | U8 Function; /*0x03 */ | |
| 1086 | U16 Reserved2; /*0x04 */ | |
| 1087 | U8 Reserved3; /*0x06 */ | |
| 1088 | U8 MsgFlags; /*0x07 */ | |
| 1089 | U8 VP_ID; /*0x08 */ | |
| 1090 | U8 VF_ID; /*0x09 */ | |
| 1091 | U16 Reserved4; /*0x0A */ | |
| 1092 | U16 Event; /*0x0C */ | |
| 1093 | U16 Reserved5; /*0x0E */ | |
| 1094 | U32 EventContext; /*0x10 */ | |
| 1095 | } MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST, | |
| 1096 | Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t; | |
| 1097 | ||
| 1098 | /*EventAck Reply message */ | |
| 1099 | typedef struct _MPI2_EVENT_ACK_REPLY { | |
| 1100 | U16 Reserved1; /*0x00 */ | |
| 1101 | U8 MsgLength; /*0x02 */ | |
| 1102 | U8 Function; /*0x03 */ | |
| 1103 | U16 Reserved2; /*0x04 */ | |
| 1104 | U8 Reserved3; /*0x06 */ | |
| 1105 | U8 MsgFlags; /*0x07 */ | |
| 1106 | U8 VP_ID; /*0x08 */ | |
| 1107 | U8 VF_ID; /*0x09 */ | |
| 1108 | U16 Reserved4; /*0x0A */ | |
| 1109 | U16 Reserved5; /*0x0C */ | |
| 1110 | U16 IOCStatus; /*0x0E */ | |
| 1111 | U32 IOCLogInfo; /*0x10 */ | |
| 1112 | } MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY, | |
| 1113 | Mpi2EventAckReply_t, *pMpi2EventAckReply_t; | |
| 1114 | ||
| 1115 | /**************************************************************************** | |
| 1116 | * SendHostMessage message | |
| 1117 | ****************************************************************************/ | |
| 1118 | ||
| 1119 | /*SendHostMessage Request message */ | |
| 1120 | typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST { | |
| 1121 | U16 HostDataLength; /*0x00 */ | |
| 1122 | U8 ChainOffset; /*0x02 */ | |
| 1123 | U8 Function; /*0x03 */ | |
| 1124 | U16 Reserved1; /*0x04 */ | |
| 1125 | U8 Reserved2; /*0x06 */ | |
| 1126 | U8 MsgFlags; /*0x07 */ | |
| 1127 | U8 VP_ID; /*0x08 */ | |
| 1128 | U8 VF_ID; /*0x09 */ | |
| 1129 | U16 Reserved3; /*0x0A */ | |
| 1130 | U8 Reserved4; /*0x0C */ | |
| 1131 | U8 DestVF_ID; /*0x0D */ | |
| 1132 | U16 Reserved5; /*0x0E */ | |
| 1133 | U32 Reserved6; /*0x10 */ | |
| 1134 | U32 Reserved7; /*0x14 */ | |
| 1135 | U32 Reserved8; /*0x18 */ | |
| 1136 | U32 Reserved9; /*0x1C */ | |
| 1137 | U32 Reserved10; /*0x20 */ | |
| 1138 | U32 HostData[1]; /*0x24 */ | |
| 1139 | } MPI2_SEND_HOST_MESSAGE_REQUEST, | |
| 1140 | *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST, | |
| 1141 | Mpi2SendHostMessageRequest_t, | |
| 1142 | *pMpi2SendHostMessageRequest_t; | |
| 1143 | ||
| 1144 | /*SendHostMessage Reply message */ | |
| 1145 | typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY { | |
| 1146 | U16 HostDataLength; /*0x00 */ | |
| 1147 | U8 MsgLength; /*0x02 */ | |
| 1148 | U8 Function; /*0x03 */ | |
| 1149 | U16 Reserved1; /*0x04 */ | |
| 1150 | U8 Reserved2; /*0x06 */ | |
| 1151 | U8 MsgFlags; /*0x07 */ | |
| 1152 | U8 VP_ID; /*0x08 */ | |
| 1153 | U8 VF_ID; /*0x09 */ | |
| 1154 | U16 Reserved3; /*0x0A */ | |
| 1155 | U16 Reserved4; /*0x0C */ | |
| 1156 | U16 IOCStatus; /*0x0E */ | |
| 1157 | U32 IOCLogInfo; /*0x10 */ | |
| 1158 | } MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY, | |
| 1159 | Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t; | |
| 1160 | ||
| 1161 | /**************************************************************************** | |
| 1162 | * FWDownload message | |
| 1163 | ****************************************************************************/ | |
| 1164 | ||
| 1165 | /*MPI v2.0 FWDownload Request message */ | |
| 1166 | typedef struct _MPI2_FW_DOWNLOAD_REQUEST { | |
| 1167 | U8 ImageType; /*0x00 */ | |
| 1168 | U8 Reserved1; /*0x01 */ | |
| 1169 | U8 ChainOffset; /*0x02 */ | |
| 1170 | U8 Function; /*0x03 */ | |
| 1171 | U16 Reserved2; /*0x04 */ | |
| 1172 | U8 Reserved3; /*0x06 */ | |
| 1173 | U8 MsgFlags; /*0x07 */ | |
| 1174 | U8 VP_ID; /*0x08 */ | |
| 1175 | U8 VF_ID; /*0x09 */ | |
| 1176 | U16 Reserved4; /*0x0A */ | |
| 1177 | U32 TotalImageSize; /*0x0C */ | |
| 1178 | U32 Reserved5; /*0x10 */ | |
| 1179 | MPI2_MPI_SGE_UNION SGL; /*0x14 */ | |
| 1180 | } MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST, | |
| 1181 | Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest; | |
| 1182 | ||
| 1183 | #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) | |
| 1184 | ||
| 1185 | #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) | |
| 1186 | #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) | |
| 1187 | #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) | |
| 1188 | #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) | |
| 1189 | #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) | |
| 1190 | #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) | |
| 1191 | #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) | |
| 1192 | #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) | |
| 4c8bab4d | 1193 | #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) |
| f92363d1 SR |
1194 | #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) |
| 1195 | ||
| 1196 | /*MPI v2.0 FWDownload TransactionContext Element */ | |
| 1197 | typedef struct _MPI2_FW_DOWNLOAD_TCSGE { | |
| 1198 | U8 Reserved1; /*0x00 */ | |
| 1199 | U8 ContextSize; /*0x01 */ | |
| 1200 | U8 DetailsLength; /*0x02 */ | |
| 1201 | U8 Flags; /*0x03 */ | |
| 1202 | U32 Reserved2; /*0x04 */ | |
| 1203 | U32 ImageOffset; /*0x08 */ | |
| 1204 | U32 ImageSize; /*0x0C */ | |
| 1205 | } MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE, | |
| 1206 | Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t; | |
| 1207 | ||
| 1208 | /*MPI v2.5 FWDownload Request message */ | |
| 1209 | typedef struct _MPI25_FW_DOWNLOAD_REQUEST { | |
| 1210 | U8 ImageType; /*0x00 */ | |
| 1211 | U8 Reserved1; /*0x01 */ | |
| 1212 | U8 ChainOffset; /*0x02 */ | |
| 1213 | U8 Function; /*0x03 */ | |
| 1214 | U16 Reserved2; /*0x04 */ | |
| 1215 | U8 Reserved3; /*0x06 */ | |
| 1216 | U8 MsgFlags; /*0x07 */ | |
| 1217 | U8 VP_ID; /*0x08 */ | |
| 1218 | U8 VF_ID; /*0x09 */ | |
| 1219 | U16 Reserved4; /*0x0A */ | |
| 1220 | U32 TotalImageSize; /*0x0C */ | |
| 1221 | U32 Reserved5; /*0x10 */ | |
| 1222 | U32 Reserved6; /*0x14 */ | |
| 1223 | U32 ImageOffset; /*0x18 */ | |
| 1224 | U32 ImageSize; /*0x1C */ | |
| 1225 | MPI25_SGE_IO_UNION SGL; /*0x20 */ | |
| 1226 | } MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST, | |
| 1227 | Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest; | |
| 1228 | ||
| 1229 | /*FWDownload Reply message */ | |
| 1230 | typedef struct _MPI2_FW_DOWNLOAD_REPLY { | |
| 1231 | U8 ImageType; /*0x00 */ | |
| 1232 | U8 Reserved1; /*0x01 */ | |
| 1233 | U8 MsgLength; /*0x02 */ | |
| 1234 | U8 Function; /*0x03 */ | |
| 1235 | U16 Reserved2; /*0x04 */ | |
| 1236 | U8 Reserved3; /*0x06 */ | |
| 1237 | U8 MsgFlags; /*0x07 */ | |
| 1238 | U8 VP_ID; /*0x08 */ | |
| 1239 | U8 VF_ID; /*0x09 */ | |
| 1240 | U16 Reserved4; /*0x0A */ | |
| 1241 | U16 Reserved5; /*0x0C */ | |
| 1242 | U16 IOCStatus; /*0x0E */ | |
| 1243 | U32 IOCLogInfo; /*0x10 */ | |
| 1244 | } MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY, | |
| 1245 | Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t; | |
| 1246 | ||
| 1247 | /**************************************************************************** | |
| 1248 | * FWUpload message | |
| 1249 | ****************************************************************************/ | |
| 1250 | ||
| 1251 | /*MPI v2.0 FWUpload Request message */ | |
| 1252 | typedef struct _MPI2_FW_UPLOAD_REQUEST { | |
| 1253 | U8 ImageType; /*0x00 */ | |
| 1254 | U8 Reserved1; /*0x01 */ | |
| 1255 | U8 ChainOffset; /*0x02 */ | |
| 1256 | U8 Function; /*0x03 */ | |
| 1257 | U16 Reserved2; /*0x04 */ | |
| 1258 | U8 Reserved3; /*0x06 */ | |
| 1259 | U8 MsgFlags; /*0x07 */ | |
| 1260 | U8 VP_ID; /*0x08 */ | |
| 1261 | U8 VF_ID; /*0x09 */ | |
| 1262 | U16 Reserved4; /*0x0A */ | |
| 1263 | U32 Reserved5; /*0x0C */ | |
| 1264 | U32 Reserved6; /*0x10 */ | |
| 1265 | MPI2_MPI_SGE_UNION SGL; /*0x14 */ | |
| 1266 | } MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST, | |
| 1267 | Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t; | |
| 1268 | ||
| 1269 | #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) | |
| 1270 | #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) | |
| 1271 | #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) | |
| 1272 | #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) | |
| 1273 | #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) | |
| 1274 | #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) | |
| 1275 | #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) | |
| 1276 | #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) | |
| 1277 | #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) | |
| 1278 | #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) | |
| b130b0d5 | 1279 | #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) |
| f92363d1 SR |
1280 | |
| 1281 | /*MPI v2.0 FWUpload TransactionContext Element */ | |
| 1282 | typedef struct _MPI2_FW_UPLOAD_TCSGE { | |
| 1283 | U8 Reserved1; /*0x00 */ | |
| 1284 | U8 ContextSize; /*0x01 */ | |
| 1285 | U8 DetailsLength; /*0x02 */ | |
| 1286 | U8 Flags; /*0x03 */ | |
| 1287 | U32 Reserved2; /*0x04 */ | |
| 1288 | U32 ImageOffset; /*0x08 */ | |
| 1289 | U32 ImageSize; /*0x0C */ | |
| 1290 | } MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE, | |
| 1291 | Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t; | |
| 1292 | ||
| 1293 | /*MPI v2.5 FWUpload Request message */ | |
| 1294 | typedef struct _MPI25_FW_UPLOAD_REQUEST { | |
| 1295 | U8 ImageType; /*0x00 */ | |
| 1296 | U8 Reserved1; /*0x01 */ | |
| 1297 | U8 ChainOffset; /*0x02 */ | |
| 1298 | U8 Function; /*0x03 */ | |
| 1299 | U16 Reserved2; /*0x04 */ | |
| 1300 | U8 Reserved3; /*0x06 */ | |
| 1301 | U8 MsgFlags; /*0x07 */ | |
| 1302 | U8 VP_ID; /*0x08 */ | |
| 1303 | U8 VF_ID; /*0x09 */ | |
| 1304 | U16 Reserved4; /*0x0A */ | |
| 1305 | U32 Reserved5; /*0x0C */ | |
| 1306 | U32 Reserved6; /*0x10 */ | |
| 1307 | U32 Reserved7; /*0x14 */ | |
| 1308 | U32 ImageOffset; /*0x18 */ | |
| 1309 | U32 ImageSize; /*0x1C */ | |
| 1310 | MPI25_SGE_IO_UNION SGL; /*0x20 */ | |
| 1311 | } MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST, | |
| 1312 | Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t; | |
| 1313 | ||
| 1314 | /*FWUpload Reply message */ | |
| 1315 | typedef struct _MPI2_FW_UPLOAD_REPLY { | |
| 1316 | U8 ImageType; /*0x00 */ | |
| 1317 | U8 Reserved1; /*0x01 */ | |
| 1318 | U8 MsgLength; /*0x02 */ | |
| 1319 | U8 Function; /*0x03 */ | |
| 1320 | U16 Reserved2; /*0x04 */ | |
| 1321 | U8 Reserved3; /*0x06 */ | |
| 1322 | U8 MsgFlags; /*0x07 */ | |
| 1323 | U8 VP_ID; /*0x08 */ | |
| 1324 | U8 VF_ID; /*0x09 */ | |
| 1325 | U16 Reserved4; /*0x0A */ | |
| 1326 | U16 Reserved5; /*0x0C */ | |
| 1327 | U16 IOCStatus; /*0x0E */ | |
| 1328 | U32 IOCLogInfo; /*0x10 */ | |
| 1329 | U32 ActualImageSize; /*0x14 */ | |
| 1330 | } MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY, | |
| 1331 | Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t; | |
| 1332 | ||
| 1333 | /*FW Image Header */ | |
| 1334 | typedef struct _MPI2_FW_IMAGE_HEADER { | |
| 1335 | U32 Signature; /*0x00 */ | |
| 1336 | U32 Signature0; /*0x04 */ | |
| 1337 | U32 Signature1; /*0x08 */ | |
| 1338 | U32 Signature2; /*0x0C */ | |
| 1339 | MPI2_VERSION_UNION MPIVersion; /*0x10 */ | |
| 1340 | MPI2_VERSION_UNION FWVersion; /*0x14 */ | |
| 1341 | MPI2_VERSION_UNION NVDATAVersion; /*0x18 */ | |
| 1342 | MPI2_VERSION_UNION PackageVersion; /*0x1C */ | |
| 1343 | U16 VendorID; /*0x20 */ | |
| 1344 | U16 ProductID; /*0x22 */ | |
| 1345 | U16 ProtocolFlags; /*0x24 */ | |
| 1346 | U16 Reserved26; /*0x26 */ | |
| 1347 | U32 IOCCapabilities; /*0x28 */ | |
| 1348 | U32 ImageSize; /*0x2C */ | |
| 1349 | U32 NextImageHeaderOffset; /*0x30 */ | |
| 1350 | U32 Checksum; /*0x34 */ | |
| 1351 | U32 Reserved38; /*0x38 */ | |
| 1352 | U32 Reserved3C; /*0x3C */ | |
| 1353 | U32 Reserved40; /*0x40 */ | |
| 1354 | U32 Reserved44; /*0x44 */ | |
| 1355 | U32 Reserved48; /*0x48 */ | |
| 1356 | U32 Reserved4C; /*0x4C */ | |
| 1357 | U32 Reserved50; /*0x50 */ | |
| 1358 | U32 Reserved54; /*0x54 */ | |
| 1359 | U32 Reserved58; /*0x58 */ | |
| 1360 | U32 Reserved5C; /*0x5C */ | |
| b130b0d5 | 1361 | U32 BootFlags; /*0x60 */ |
| f92363d1 SR |
1362 | U32 FirmwareVersionNameWhat; /*0x64 */ |
| 1363 | U8 FirmwareVersionName[32]; /*0x68 */ | |
| 1364 | U32 VendorNameWhat; /*0x88 */ | |
| 1365 | U8 VendorName[32]; /*0x8C */ | |
| 1366 | U32 PackageNameWhat; /*0x88 */ | |
| 1367 | U8 PackageName[32]; /*0x8C */ | |
| 1368 | U32 ReservedD0; /*0xD0 */ | |
| 1369 | U32 ReservedD4; /*0xD4 */ | |
| 1370 | U32 ReservedD8; /*0xD8 */ | |
| 1371 | U32 ReservedDC; /*0xDC */ | |
| 1372 | U32 ReservedE0; /*0xE0 */ | |
| 1373 | U32 ReservedE4; /*0xE4 */ | |
| 1374 | U32 ReservedE8; /*0xE8 */ | |
| 1375 | U32 ReservedEC; /*0xEC */ | |
| 1376 | U32 ReservedF0; /*0xF0 */ | |
| 1377 | U32 ReservedF4; /*0xF4 */ | |
| 1378 | U32 ReservedF8; /*0xF8 */ | |
| 1379 | U32 ReservedFC; /*0xFC */ | |
| 1380 | } MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER, | |
| 1381 | Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t; | |
| 1382 | ||
| 1383 | /*Signature field */ | |
| 1384 | #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) | |
| 1385 | #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) | |
| 1386 | #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) | |
| b130b0d5 | 1387 | #define MPI26_FW_HEADER_SIGNATURE (0xEB000000) |
| f92363d1 SR |
1388 | |
| 1389 | /*Signature0 field */ | |
| 1390 | #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) | |
| 1391 | #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) | |
| 4fe6bc97 C |
1392 | /* Last byte is defined by architecture */ |
| 1393 | #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) | |
| 1394 | #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) | |
| 1395 | #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) | |
| 1396 | #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) | |
| 1397 | /* legacy (0x5AEAA55A) */ | |
| 1398 | #define MPI26_FW_HEADER_SIGNATURE0 \ | |
| 1399 | (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) | |
| 1400 | #define MPI26_FW_HEADER_SIGNATURE0_3516 \ | |
| 1401 | (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) | |
| f92363d1 SR |
1402 | |
| 1403 | /*Signature1 field */ | |
| 1404 | #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) | |
| 1405 | #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) | |
| b130b0d5 | 1406 | #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) |
| f92363d1 SR |
1407 | |
| 1408 | /*Signature2 field */ | |
| 1409 | #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) | |
| 1410 | #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) | |
| b130b0d5 | 1411 | #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) |
| f92363d1 SR |
1412 | |
| 1413 | /*defines for using the ProductID field */ | |
| 1414 | #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) | |
| 1415 | #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) | |
| 1416 | ||
| 1417 | #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) | |
| 1418 | #define MPI2_FW_HEADER_PID_PROD_A (0x0000) | |
| 1419 | #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) | |
| 1420 | #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) | |
| 1421 | ||
| 1422 | #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) | |
| 1423 | /*SAS ProductID Family bits */ | |
| 1424 | #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) | |
| 1425 | #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) | |
| 1426 | #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) | |
| b130b0d5 SS |
1427 | #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) |
| 1428 | #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) | |
| f92363d1 SR |
1429 | |
| 1430 | /*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ | |
| 1431 | ||
| 1432 | /*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ | |
| 1433 | ||
| 1434 | #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) | |
| 1435 | #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) | |
| b130b0d5 | 1436 | #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) |
| f92363d1 SR |
1437 | #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) |
| 1438 | ||
| 1439 | #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) | |
| 1440 | ||
| 1441 | #define MPI2_FW_HEADER_SIZE (0x100) | |
| 1442 | ||
| 1443 | /*Extended Image Header */ | |
| 1444 | typedef struct _MPI2_EXT_IMAGE_HEADER { | |
| 1445 | U8 ImageType; /*0x00 */ | |
| 1446 | U8 Reserved1; /*0x01 */ | |
| 1447 | U16 Reserved2; /*0x02 */ | |
| 1448 | U32 Checksum; /*0x04 */ | |
| 1449 | U32 ImageSize; /*0x08 */ | |
| 1450 | U32 NextImageHeaderOffset; /*0x0C */ | |
| 1451 | U32 PackageVersion; /*0x10 */ | |
| 1452 | U32 Reserved3; /*0x14 */ | |
| 1453 | U32 Reserved4; /*0x18 */ | |
| 1454 | U32 Reserved5; /*0x1C */ | |
| 1455 | U8 IdentifyString[32]; /*0x20 */ | |
| 1456 | } MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER, | |
| 1457 | Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t; | |
| 1458 | ||
| 1459 | /*useful offsets */ | |
| 1460 | #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) | |
| 1461 | #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) | |
| 1462 | #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) | |
| 1463 | ||
| 1464 | #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) | |
| 1465 | ||
| 1466 | /*defines for the ImageType field */ | |
| 1467 | #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) | |
| 1468 | #define MPI2_EXT_IMAGE_TYPE_FW (0x01) | |
| 1469 | #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) | |
| 1470 | #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) | |
| 1471 | #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) | |
| 1472 | #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) | |
| 1473 | #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) | |
| 1474 | #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) | |
| 4c8bab4d | 1475 | #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) |
| f92363d1 SR |
1476 | #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80) |
| 1477 | #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF) | |
| 1478 | ||
| 1479 | #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) | |
| 1480 | ||
| 1481 | /*FLASH Layout Extended Image Data */ | |
| 1482 | ||
| 1483 | /* | |
| 1484 | *Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |
| 1485 | *one and check RegionsPerLayout at runtime. | |
| 1486 | */ | |
| 1487 | #ifndef MPI2_FLASH_NUMBER_OF_REGIONS | |
| 1488 | #define MPI2_FLASH_NUMBER_OF_REGIONS (1) | |
| 1489 | #endif | |
| 1490 | ||
| 1491 | /* | |
| 1492 | *Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |
| 1493 | *one and check NumberOfLayouts at runtime. | |
| 1494 | */ | |
| 1495 | #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS | |
| 1496 | #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) | |
| 1497 | #endif | |
| 1498 | ||
| 1499 | typedef struct _MPI2_FLASH_REGION { | |
| 1500 | U8 RegionType; /*0x00 */ | |
| 1501 | U8 Reserved1; /*0x01 */ | |
| 1502 | U16 Reserved2; /*0x02 */ | |
| 1503 | U32 RegionOffset; /*0x04 */ | |
| 1504 | U32 RegionSize; /*0x08 */ | |
| 1505 | U32 Reserved3; /*0x0C */ | |
| 1506 | } MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION, | |
| 1507 | Mpi2FlashRegion_t, *pMpi2FlashRegion_t; | |
| 1508 | ||
| 1509 | typedef struct _MPI2_FLASH_LAYOUT { | |
| 1510 | U32 FlashSize; /*0x00 */ | |
| 1511 | U32 Reserved1; /*0x04 */ | |
| 1512 | U32 Reserved2; /*0x08 */ | |
| 1513 | U32 Reserved3; /*0x0C */ | |
| 1514 | MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */ | |
| 1515 | } MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT, | |
| 1516 | Mpi2FlashLayout_t, *pMpi2FlashLayout_t; | |
| 1517 | ||
| 1518 | typedef struct _MPI2_FLASH_LAYOUT_DATA { | |
| 1519 | U8 ImageRevision; /*0x00 */ | |
| 1520 | U8 Reserved1; /*0x01 */ | |
| 1521 | U8 SizeOfRegion; /*0x02 */ | |
| 1522 | U8 Reserved2; /*0x03 */ | |
| 1523 | U16 NumberOfLayouts; /*0x04 */ | |
| 1524 | U16 RegionsPerLayout; /*0x06 */ | |
| 1525 | U16 MinimumSectorAlignment; /*0x08 */ | |
| 1526 | U16 Reserved3; /*0x0A */ | |
| 1527 | U32 Reserved4; /*0x0C */ | |
| 1528 | MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */ | |
| 1529 | } MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA, | |
| 1530 | Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t; | |
| 1531 | ||
| 1532 | /*defines for the RegionType field */ | |
| 1533 | #define MPI2_FLASH_REGION_UNUSED (0x00) | |
| 1534 | #define MPI2_FLASH_REGION_FIRMWARE (0x01) | |
| 1535 | #define MPI2_FLASH_REGION_BIOS (0x02) | |
| 1536 | #define MPI2_FLASH_REGION_NVDATA (0x03) | |
| 1537 | #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) | |
| 1538 | #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) | |
| 1539 | #define MPI2_FLASH_REGION_CONFIG_1 (0x07) | |
| 1540 | #define MPI2_FLASH_REGION_CONFIG_2 (0x08) | |
| 1541 | #define MPI2_FLASH_REGION_MEGARAID (0x09) | |
| b130b0d5 SS |
1542 | #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) |
| 1543 | #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) | |
| 1544 | #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) | |
| f92363d1 SR |
1545 | |
| 1546 | /*ImageRevision */ | |
| 1547 | #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) | |
| 1548 | ||
| 1549 | /*Supported Devices Extended Image Data */ | |
| 1550 | ||
| 1551 | /* | |
| 1552 | *Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |
| 1553 | *one and check NumberOfDevices at runtime. | |
| 1554 | */ | |
| 1555 | #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES | |
| 1556 | #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) | |
| 1557 | #endif | |
| 1558 | ||
| 1559 | typedef struct _MPI2_SUPPORTED_DEVICE { | |
| 1560 | U16 DeviceID; /*0x00 */ | |
| 1561 | U16 VendorID; /*0x02 */ | |
| 1562 | U16 DeviceIDMask; /*0x04 */ | |
| 1563 | U16 Reserved1; /*0x06 */ | |
| 1564 | U8 LowPCIRev; /*0x08 */ | |
| 1565 | U8 HighPCIRev; /*0x09 */ | |
| 1566 | U16 Reserved2; /*0x0A */ | |
| 1567 | U32 Reserved3; /*0x0C */ | |
| 1568 | } MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE, | |
| 1569 | Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t; | |
| 1570 | ||
| 1571 | typedef struct _MPI2_SUPPORTED_DEVICES_DATA { | |
| 1572 | U8 ImageRevision; /*0x00 */ | |
| 1573 | U8 Reserved1; /*0x01 */ | |
| 1574 | U8 NumberOfDevices; /*0x02 */ | |
| 1575 | U8 Reserved2; /*0x03 */ | |
| 1576 | U32 Reserved3; /*0x04 */ | |
| 1577 | MPI2_SUPPORTED_DEVICE | |
| 1578 | SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */ | |
| 1579 | } MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA, | |
| 1580 | Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t; | |
| 1581 | ||
| 1582 | /*ImageRevision */ | |
| 1583 | #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) | |
| 1584 | ||
| 1585 | /*Init Extended Image Data */ | |
| 1586 | ||
| 1587 | typedef struct _MPI2_INIT_IMAGE_FOOTER { | |
| 1588 | U32 BootFlags; /*0x00 */ | |
| 1589 | U32 ImageSize; /*0x04 */ | |
| 1590 | U32 Signature0; /*0x08 */ | |
| 1591 | U32 Signature1; /*0x0C */ | |
| 1592 | U32 Signature2; /*0x10 */ | |
| 1593 | U32 ResetVector; /*0x14 */ | |
| 1594 | } MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER, | |
| 1595 | Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t; | |
| 1596 | ||
| 1597 | /*defines for the BootFlags field */ | |
| 1598 | #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) | |
| 1599 | ||
| 1600 | /*defines for the ImageSize field */ | |
| 1601 | #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) | |
| 1602 | ||
| 1603 | /*defines for the Signature0 field */ | |
| 1604 | #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) | |
| 1605 | #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) | |
| 1606 | ||
| 1607 | /*defines for the Signature1 field */ | |
| 1608 | #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) | |
| 1609 | #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) | |
| 1610 | ||
| 1611 | /*defines for the Signature2 field */ | |
| 1612 | #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) | |
| 1613 | #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) | |
| 1614 | ||
| 1615 | /*Signature fields as individual bytes */ | |
| 1616 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) | |
| 1617 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) | |
| 1618 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) | |
| 1619 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) | |
| 1620 | ||
| 1621 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) | |
| 1622 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) | |
| 1623 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) | |
| 1624 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) | |
| 1625 | ||
| 1626 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) | |
| 1627 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) | |
| 1628 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) | |
| 1629 | #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) | |
| 1630 | ||
| 1631 | /*defines for the ResetVector field */ | |
| 1632 | #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) | |
| 1633 | ||
| 4c8bab4d SR |
1634 | |
| 1635 | /* Encrypted Hash Extended Image Data */ | |
| 1636 | ||
| 1637 | typedef struct _MPI25_ENCRYPTED_HASH_ENTRY { | |
| 1638 | U8 HashImageType; /* 0x00 */ | |
| 1639 | U8 HashAlgorithm; /* 0x01 */ | |
| 1640 | U8 EncryptionAlgorithm; /* 0x02 */ | |
| 1641 | U8 Reserved1; /* 0x03 */ | |
| 1642 | U32 Reserved2; /* 0x04 */ | |
| 1643 | U32 EncryptedHash[1]; /* 0x08 */ /* variable length */ | |
| 1644 | } MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY, | |
| 1645 | Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t; | |
| 1646 | ||
| 1647 | /* values for HashImageType */ | |
| 1648 | #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00) | |
| 1649 | #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01) | |
| a94bea34 | 1650 | #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02) |
| 4c8bab4d SR |
1651 | |
| 1652 | /* values for HashAlgorithm */ | |
| 1653 | #define MPI25_HASH_ALGORITHM_UNUSED (0x00) | |
| 1654 | #define MPI25_HASH_ALGORITHM_SHA256 (0x01) | |
| 1655 | ||
| 1656 | /* values for EncryptionAlgorithm */ | |
| 1657 | #define MPI25_ENCRYPTION_ALG_UNUSED (0x00) | |
| 1658 | #define MPI25_ENCRYPTION_ALG_RSA256 (0x01) | |
| 1659 | ||
| 1660 | typedef struct _MPI25_ENCRYPTED_HASH_DATA { | |
| 1661 | U8 ImageVersion; /* 0x00 */ | |
| 1662 | U8 NumHash; /* 0x01 */ | |
| 1663 | U16 Reserved1; /* 0x02 */ | |
| 1664 | U32 Reserved2; /* 0x04 */ | |
| 1665 | MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ | |
| 1666 | } MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA, | |
| 1667 | Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t; | |
| 1668 | ||
| 1669 | ||
| f92363d1 SR |
1670 | /**************************************************************************** |
| 1671 | * PowerManagementControl message | |
| 1672 | ****************************************************************************/ | |
| 1673 | ||
| 1674 | /*PowerManagementControl Request message */ | |
| 1675 | typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST { | |
| 1676 | U8 Feature; /*0x00 */ | |
| 1677 | U8 Reserved1; /*0x01 */ | |
| 1678 | U8 ChainOffset; /*0x02 */ | |
| 1679 | U8 Function; /*0x03 */ | |
| 1680 | U16 Reserved2; /*0x04 */ | |
| 1681 | U8 Reserved3; /*0x06 */ | |
| 1682 | U8 MsgFlags; /*0x07 */ | |
| 1683 | U8 VP_ID; /*0x08 */ | |
| 1684 | U8 VF_ID; /*0x09 */ | |
| 1685 | U16 Reserved4; /*0x0A */ | |
| 1686 | U8 Parameter1; /*0x0C */ | |
| 1687 | U8 Parameter2; /*0x0D */ | |
| 1688 | U8 Parameter3; /*0x0E */ | |
| 1689 | U8 Parameter4; /*0x0F */ | |
| 1690 | U32 Reserved5; /*0x10 */ | |
| 1691 | U32 Reserved6; /*0x14 */ | |
| 1692 | } MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, | |
| 1693 | Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t; | |
| 1694 | ||
| 1695 | /*defines for the Feature field */ | |
| 1696 | #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) | |
| 1697 | #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) | |
| 1698 | #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */ | |
| 1699 | #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) | |
| 1700 | #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) | |
| 1701 | #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) | |
| 1702 | #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) | |
| 1703 | ||
| 1704 | /*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ | |
| 1705 | /*Parameter1 contains a PHY number */ | |
| 1706 | /*Parameter2 indicates power condition action using these defines */ | |
| 1707 | #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) | |
| 1708 | #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) | |
| 1709 | #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) | |
| 1710 | /*Parameter3 and Parameter4 are reserved */ | |
| 1711 | ||
| 1712 | /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION | |
| 1713 | * Feature */ | |
| 1714 | /*Parameter1 contains SAS port width modulation group number */ | |
| 1715 | /*Parameter2 indicates IOC action using these defines */ | |
| 1716 | #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) | |
| 1717 | #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) | |
| 1718 | #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) | |
| 1719 | /*Parameter3 indicates desired modulation level using these defines */ | |
| 1720 | #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) | |
| 1721 | #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) | |
| 1722 | #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) | |
| 1723 | #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) | |
| 1724 | /*Parameter4 is reserved */ | |
| 1725 | ||
| 1726 | /*this next set (_PCIE_LINK) is obsolete */ | |
| 1727 | /*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ | |
| 1728 | /*Parameter1 indicates desired PCIe link speed using these defines */ | |
| 1729 | #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */ | |
| 1730 | #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */ | |
| 1731 | #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */ | |
| 1732 | /*Parameter2 indicates desired PCIe link width using these defines */ | |
| 1733 | #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */ | |
| 1734 | #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */ | |
| 1735 | #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */ | |
| 1736 | #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */ | |
| 1737 | /*Parameter3 and Parameter4 are reserved */ | |
| 1738 | ||
| 1739 | /*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ | |
| 1740 | /*Parameter1 indicates desired IOC hardware clock speed using these defines */ | |
| 1741 | #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) | |
| 1742 | #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) | |
| 1743 | #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) | |
| 1744 | #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) | |
| 1745 | /*Parameter2, Parameter3, and Parameter4 are reserved */ | |
| 1746 | ||
| 1747 | /*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/ | |
| 1748 | /*Parameter1 indicates host action regarding global power management mode */ | |
| 1749 | #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01) | |
| 1750 | #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02) | |
| 1751 | #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03) | |
| 1752 | /*Parameter2 indicates the requested global power management mode */ | |
| 1753 | #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01) | |
| 1754 | #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08) | |
| 1755 | #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40) | |
| 1756 | /*Parameter3 and Parameter4 are reserved */ | |
| 1757 | ||
| 1758 | /*PowerManagementControl Reply message */ | |
| 1759 | typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY { | |
| 1760 | U8 Feature; /*0x00 */ | |
| 1761 | U8 Reserved1; /*0x01 */ | |
| 1762 | U8 MsgLength; /*0x02 */ | |
| 1763 | U8 Function; /*0x03 */ | |
| 1764 | U16 Reserved2; /*0x04 */ | |
| 1765 | U8 Reserved3; /*0x06 */ | |
| 1766 | U8 MsgFlags; /*0x07 */ | |
| 1767 | U8 VP_ID; /*0x08 */ | |
| 1768 | U8 VF_ID; /*0x09 */ | |
| 1769 | U16 Reserved4; /*0x0A */ | |
| 1770 | U16 Reserved5; /*0x0C */ | |
| 1771 | U16 IOCStatus; /*0x0E */ | |
| 1772 | U32 IOCLogInfo; /*0x10 */ | |
| 1773 | } MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY, | |
| 1774 | Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t; | |
| 1775 | ||
| b130b0d5 SS |
1776 | /**************************************************************************** |
| 1777 | * IO Unit Control messages (MPI v2.6 and later only.) | |
| 1778 | ****************************************************************************/ | |
| 1779 | ||
| 1780 | /* IO Unit Control Request Message */ | |
| 1781 | typedef struct _MPI26_IOUNIT_CONTROL_REQUEST { | |
| 1782 | U8 Operation; /* 0x00 */ | |
| 1783 | U8 Reserved1; /* 0x01 */ | |
| 1784 | U8 ChainOffset; /* 0x02 */ | |
| 1785 | U8 Function; /* 0x03 */ | |
| 1786 | U16 DevHandle; /* 0x04 */ | |
| 1787 | U8 IOCParameter; /* 0x06 */ | |
| 1788 | U8 MsgFlags; /* 0x07 */ | |
| 1789 | U8 VP_ID; /* 0x08 */ | |
| 1790 | U8 VF_ID; /* 0x09 */ | |
| 1791 | U16 Reserved3; /* 0x0A */ | |
| 1792 | U16 Reserved4; /* 0x0C */ | |
| 1793 | U8 PhyNum; /* 0x0E */ | |
| 1794 | U8 PrimFlags; /* 0x0F */ | |
| 1795 | U32 Primitive; /* 0x10 */ | |
| 1796 | U8 LookupMethod; /* 0x14 */ | |
| 1797 | U8 Reserved5; /* 0x15 */ | |
| 1798 | U16 SlotNumber; /* 0x16 */ | |
| 1799 | U64 LookupAddress; /* 0x18 */ | |
| 1800 | U32 IOCParameterValue; /* 0x20 */ | |
| 1801 | U32 Reserved7; /* 0x24 */ | |
| 1802 | U32 Reserved8; /* 0x28 */ | |
| 1803 | } MPI26_IOUNIT_CONTROL_REQUEST, | |
| 1804 | *PTR_MPI26_IOUNIT_CONTROL_REQUEST, | |
| 1805 | Mpi26IoUnitControlRequest_t, | |
| 1806 | *pMpi26IoUnitControlRequest_t; | |
| 1807 | ||
| 1808 | /* values for the Operation field */ | |
| 1809 | #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) | |
| 1810 | #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) | |
| 1811 | #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) | |
| 1812 | #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) | |
| 4fe6bc97 | 1813 | #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) |
| b130b0d5 SS |
1814 | #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) |
| 1815 | #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) | |
| 1816 | #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) | |
| 1817 | #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) | |
| 1818 | #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) | |
| 1819 | #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) | |
| 1820 | #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) | |
| 1821 | #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) | |
| 1822 | #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) | |
| 1823 | #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) | |
| 1824 | #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) | |
| 1825 | #define MPI26_CTRL_OP_SHUTDOWN (0x16) | |
| 1826 | #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) | |
| 1827 | #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) | |
| 1828 | #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) | |
| 1829 | #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) | |
| 1830 | ||
| 1831 | /* values for the PrimFlags field */ | |
| 1832 | #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) | |
| 1833 | #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) | |
| 1834 | #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) | |
| 1835 | ||
| 1836 | /* values for the LookupMethod field */ | |
| 1837 | #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) | |
| 1838 | #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) | |
| 1839 | #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) | |
| 1840 | ||
| 1841 | ||
| 1842 | /* IO Unit Control Reply Message */ | |
| 1843 | typedef struct _MPI26_IOUNIT_CONTROL_REPLY { | |
| 1844 | U8 Operation; /* 0x00 */ | |
| 1845 | U8 Reserved1; /* 0x01 */ | |
| 1846 | U8 MsgLength; /* 0x02 */ | |
| 1847 | U8 Function; /* 0x03 */ | |
| 1848 | U16 DevHandle; /* 0x04 */ | |
| 1849 | U8 IOCParameter; /* 0x06 */ | |
| 1850 | U8 MsgFlags; /* 0x07 */ | |
| 1851 | U8 VP_ID; /* 0x08 */ | |
| 1852 | U8 VF_ID; /* 0x09 */ | |
| 1853 | U16 Reserved3; /* 0x0A */ | |
| 1854 | U16 Reserved4; /* 0x0C */ | |
| 1855 | U16 IOCStatus; /* 0x0E */ | |
| 1856 | U32 IOCLogInfo; /* 0x10 */ | |
| 1857 | } MPI26_IOUNIT_CONTROL_REPLY, | |
| 1858 | *PTR_MPI26_IOUNIT_CONTROL_REPLY, | |
| 1859 | Mpi26IoUnitControlReply_t, | |
| 1860 | *pMpi26IoUnitControlReply_t; | |
| 1861 | ||
| 1862 | ||
| f92363d1 | 1863 | #endif |