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dbf9bfe6 | 1 | /* |
f5860992 | 2 | * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver |
dbf9bfe6 | 3 | * |
4 | * Copyright (c) 2008-2009 USI Co., Ltd. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions, and the following disclaimer, | |
12 | * without modification. | |
13 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
14 | * substantially similar to the "NO WARRANTY" disclaimer below | |
15 | * ("Disclaimer") and any redistribution must be conditioned upon | |
16 | * including a substantially similar Disclaimer requirement for further | |
17 | * binary redistribution. | |
18 | * 3. Neither the names of the above-listed copyright holders nor the names | |
19 | * of any contributors may be used to endorse or promote products derived | |
20 | * from this software without specific prior written permission. | |
21 | * | |
22 | * Alternatively, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2 as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * NO WARRANTY | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
30 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
31 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
32 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
33 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
34 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
35 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
36 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
37 | * POSSIBILITY OF SUCH DAMAGES. | |
38 | * | |
39 | */ | |
40 | ||
41 | #ifndef _PM8001_SAS_H_ | |
42 | #define _PM8001_SAS_H_ | |
43 | ||
44 | #include <linux/kernel.h> | |
45 | #include <linux/module.h> | |
46 | #include <linux/spinlock.h> | |
47 | #include <linux/delay.h> | |
48 | #include <linux/types.h> | |
49 | #include <linux/ctype.h> | |
50 | #include <linux/dma-mapping.h> | |
51 | #include <linux/pci.h> | |
52 | #include <linux/interrupt.h> | |
429305e4 | 53 | #include <linux/workqueue.h> |
dbf9bfe6 | 54 | #include <scsi/libsas.h> |
55 | #include <scsi/scsi_tcq.h> | |
56 | #include <scsi/sas_ata.h> | |
60063497 | 57 | #include <linux/atomic.h> |
42f22fe3 JG |
58 | #include <linux/blk-mq.h> |
59 | #include <linux/blk-mq-pci.h> | |
dbf9bfe6 | 60 | #include "pm8001_defs.h" |
61 | ||
a70b8fc3 | 62 | #define DRV_NAME "pm80xx" |
39a45d53 | 63 | #define DRV_VERSION "0.1.40" |
83e73329 | 64 | #define PM8001_FAIL_LOGGING 0x01 /* Error message logging */ |
dbf9bfe6 | 65 | #define PM8001_INIT_LOGGING 0x02 /* driver init logging */ |
66 | #define PM8001_DISC_LOGGING 0x04 /* discovery layer logging */ | |
67 | #define PM8001_IO_LOGGING 0x08 /* I/O path logging */ | |
83e73329 | 68 | #define PM8001_EH_LOGGING 0x10 /* libsas EH function logging*/ |
dbf9bfe6 | 69 | #define PM8001_IOCTL_LOGGING 0x20 /* IOCTL message logging */ |
70 | #define PM8001_MSG_LOGGING 0x40 /* misc message logging */ | |
7370672d | 71 | #define PM8001_DEV_LOGGING 0x80 /* development message logging */ |
72 | #define PM8001_DEVIO_LOGGING 0x100 /* development io message logging */ | |
73 | #define PM8001_IOERR_LOGGING 0x200 /* development io err message logging */ | |
b7d26c1d | 74 | #define PM8001_EVENT_LOGGING 0x400 /* HW event logging */ |
dbf9bfe6 | 75 | |
2ce6e200 | 76 | #define pm8001_info(HBA, fmt, ...) \ |
b709a4ca | 77 | pr_info("%s:: %s %d: " fmt, \ |
89eddb40 | 78 | (HBA)->name, __func__, __LINE__, ##__VA_ARGS__) |
dbf9bfe6 | 79 | |
1b5d2793 JP |
80 | #define pm8001_dbg(HBA, level, fmt, ...) \ |
81 | do { \ | |
82 | if (unlikely((HBA)->logging_level & PM8001_##level##_LOGGING)) \ | |
2ce6e200 | 83 | pm8001_info(HBA, fmt, ##__VA_ARGS__); \ |
1b5d2793 | 84 | } while (0) |
dbf9bfe6 | 85 | |
efa1fca4 DLM |
86 | extern bool pm8001_use_msix; |
87 | ||
a9a923e5 AKS |
88 | #define IS_SPCV_12G(dev) ((dev->device == 0X8074) \ |
89 | || (dev->device == 0X8076) \ | |
db9d4034 BR |
90 | || (dev->device == 0X8077) \ |
91 | || (dev->device == 0X8070) \ | |
92 | || (dev->device == 0X8072)) | |
dbf9bfe6 | 93 | |
94 | #define PM8001_NAME_LENGTH 32/* generic length of strings */ | |
95 | extern struct list_head hba_list; | |
96 | extern const struct pm8001_dispatch pm8001_8001_dispatch; | |
f5860992 | 97 | extern const struct pm8001_dispatch pm8001_80xx_dispatch; |
dbf9bfe6 | 98 | |
99 | struct pm8001_hba_info; | |
100 | struct pm8001_ccb_info; | |
101 | struct pm8001_device; | |
bbfe82cd | 102 | |
7c8356d9 | 103 | struct pm8001_ioctl_payload { |
104 | u32 signature; | |
105 | u16 major_function; | |
106 | u16 minor_function; | |
7c8356d9 | 107 | u16 status; |
108 | u16 offset; | |
109 | u16 id; | |
9b889846 V |
110 | u32 wr_length; |
111 | u32 rd_length; | |
7c8356d9 | 112 | u8 *func_specific; |
113 | }; | |
114 | ||
d078b511 AKS |
115 | #define MPI_FATAL_ERROR_TABLE_OFFSET_MASK 0xFFFFFF |
116 | #define MPI_FATAL_ERROR_TABLE_SIZE(value) ((0xFF000000 & value) >> SHIFT24) | |
117 | #define MPI_FATAL_EDUMP_TABLE_LO_OFFSET 0x00 /* HNFBUFL */ | |
118 | #define MPI_FATAL_EDUMP_TABLE_HI_OFFSET 0x04 /* HNFBUFH */ | |
119 | #define MPI_FATAL_EDUMP_TABLE_LENGTH 0x08 /* HNFBLEN */ | |
120 | #define MPI_FATAL_EDUMP_TABLE_HANDSHAKE 0x0C /* FDDHSHK */ | |
121 | #define MPI_FATAL_EDUMP_TABLE_STATUS 0x10 /* FDDTSTAT */ | |
122 | #define MPI_FATAL_EDUMP_TABLE_ACCUM_LEN 0x14 /* ACCDDLEN */ | |
044f59de DU |
123 | #define MPI_FATAL_EDUMP_TABLE_TOTAL_LEN 0x18 /* TOTALLEN */ |
124 | #define MPI_FATAL_EDUMP_TABLE_SIGNATURE 0x1C /* SIGNITURE */ | |
d078b511 AKS |
125 | #define MPI_FATAL_EDUMP_HANDSHAKE_RDY 0x1 |
126 | #define MPI_FATAL_EDUMP_HANDSHAKE_BUSY 0x0 | |
127 | #define MPI_FATAL_EDUMP_TABLE_STAT_RSVD 0x0 | |
128 | #define MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED 0x1 | |
129 | #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA 0x2 | |
130 | #define MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE 0x3 | |
131 | #define TYPE_GSM_SPACE 1 | |
132 | #define TYPE_QUEUE 2 | |
133 | #define TYPE_FATAL 3 | |
134 | #define TYPE_NON_FATAL 4 | |
135 | #define TYPE_INBOUND 1 | |
136 | #define TYPE_OUTBOUND 2 | |
137 | struct forensic_data { | |
138 | u32 data_type; | |
139 | union { | |
140 | struct { | |
141 | u32 direct_len; | |
142 | u32 direct_offset; | |
143 | void *direct_data; | |
144 | } gsm_buf; | |
145 | struct { | |
146 | u16 queue_type; | |
147 | u16 queue_index; | |
148 | u32 direct_len; | |
149 | void *direct_data; | |
150 | } queue_buf; | |
151 | struct { | |
152 | u32 direct_len; | |
153 | u32 direct_offset; | |
154 | u32 read_len; | |
155 | void *direct_data; | |
156 | } data_buf; | |
157 | }; | |
158 | }; | |
159 | ||
160 | /* bit31-26 - mask bar */ | |
161 | #define SCRATCH_PAD0_BAR_MASK 0xFC000000 | |
162 | /* bit25-0 - offset mask */ | |
163 | #define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF | |
164 | /* if AAP error state */ | |
165 | #define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF | |
166 | /* Inbound doorbell bit7 */ | |
167 | #define SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP 0x80 | |
168 | /* Inbound doorbell bit7 SPCV */ | |
169 | #define SPCV_MSGU_CFG_TABLE_TRANSFER_DEBUG_INFO 0x80 | |
170 | #define MAIN_MERRDCTO_MERRDCES 0xA0/* DWORD 0x28) */ | |
171 | ||
dbf9bfe6 | 172 | struct pm8001_dispatch { |
173 | char *name; | |
174 | int (*chip_init)(struct pm8001_hba_info *pm8001_ha); | |
98132d84 | 175 | void (*chip_post_init)(struct pm8001_hba_info *pm8001_ha); |
f5860992 | 176 | int (*chip_soft_rst)(struct pm8001_hba_info *pm8001_ha); |
dbf9bfe6 | 177 | void (*chip_rst)(struct pm8001_hba_info *pm8001_ha); |
178 | int (*chip_ioremap)(struct pm8001_hba_info *pm8001_ha); | |
179 | void (*chip_iounmap)(struct pm8001_hba_info *pm8001_ha); | |
f74cf271 | 180 | irqreturn_t (*isr)(struct pm8001_hba_info *pm8001_ha, u8 vec); |
f310a4ea | 181 | u32 (*is_our_interrupt)(struct pm8001_hba_info *pm8001_ha); |
f74cf271 S |
182 | int (*isr_process_oq)(struct pm8001_hba_info *pm8001_ha, u8 vec); |
183 | void (*interrupt_enable)(struct pm8001_hba_info *pm8001_ha, u8 vec); | |
184 | void (*interrupt_disable)(struct pm8001_hba_info *pm8001_ha, u8 vec); | |
dbf9bfe6 | 185 | void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); |
186 | int (*smp_req)(struct pm8001_hba_info *pm8001_ha, | |
187 | struct pm8001_ccb_info *ccb); | |
188 | int (*ssp_io_req)(struct pm8001_hba_info *pm8001_ha, | |
189 | struct pm8001_ccb_info *ccb); | |
190 | int (*sata_req)(struct pm8001_hba_info *pm8001_ha, | |
191 | struct pm8001_ccb_info *ccb); | |
192 | int (*phy_start_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); | |
193 | int (*phy_stop_req)(struct pm8001_hba_info *pm8001_ha, u8 phy_id); | |
194 | int (*reg_dev_req)(struct pm8001_hba_info *pm8001_ha, | |
195 | struct pm8001_device *pm8001_dev, u32 flag); | |
196 | int (*dereg_dev_req)(struct pm8001_hba_info *pm8001_ha, u32 device_id); | |
197 | int (*phy_ctl_req)(struct pm8001_hba_info *pm8001_ha, | |
198 | u32 phy_id, u32 phy_op); | |
199 | int (*task_abort)(struct pm8001_hba_info *pm8001_ha, | |
2cbbf489 | 200 | struct pm8001_ccb_info *ccb); |
dbf9bfe6 | 201 | int (*ssp_tm_req)(struct pm8001_hba_info *pm8001_ha, |
bbfe82cd | 202 | struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf); |
dbf9bfe6 | 203 | int (*get_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); |
204 | int (*set_nvmd_req)(struct pm8001_hba_info *pm8001_ha, void *payload); | |
205 | int (*fw_flash_update_req)(struct pm8001_hba_info *pm8001_ha, | |
206 | void *payload); | |
207 | int (*set_dev_state_req)(struct pm8001_hba_info *pm8001_ha, | |
208 | struct pm8001_device *pm8001_dev, u32 state); | |
209 | int (*sas_diag_start_end_req)(struct pm8001_hba_info *pm8001_ha, | |
210 | u32 state); | |
211 | int (*sas_diag_execute_req)(struct pm8001_hba_info *pm8001_ha, | |
212 | u32 state); | |
d0b68041 | 213 | int (*sas_re_init_req)(struct pm8001_hba_info *pm8001_ha); |
a961ea0a | 214 | int (*fatal_errors)(struct pm8001_hba_info *pm8001_ha); |
ee05cb71 AK |
215 | void (*hw_event_ack_req)(struct pm8001_hba_info *pm8001_ha, |
216 | u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, | |
217 | u32 param1); | |
dbf9bfe6 | 218 | }; |
219 | ||
220 | struct pm8001_chip_info { | |
e5742101 | 221 | u32 encrypt; |
dbf9bfe6 | 222 | u32 n_phy; |
223 | const struct pm8001_dispatch *dispatch; | |
224 | }; | |
225 | #define PM8001_CHIP_DISP (pm8001_ha->chip->dispatch) | |
226 | ||
227 | struct pm8001_port { | |
228 | struct asd_sas_port sas_port; | |
1cc943ae | 229 | u8 port_attached; |
8414cd80 | 230 | u16 wide_port_phymap; |
1cc943ae | 231 | u8 port_state; |
08d0a992 | 232 | u8 port_id; |
1cc943ae | 233 | struct list_head list; |
dbf9bfe6 | 234 | }; |
235 | ||
236 | struct pm8001_phy { | |
237 | struct pm8001_hba_info *pm8001_ha; | |
238 | struct pm8001_port *port; | |
239 | struct asd_sas_phy sas_phy; | |
240 | struct sas_identify identify; | |
241 | struct scsi_device *sdev; | |
242 | u64 dev_sas_addr; | |
243 | u32 phy_type; | |
244 | struct completion *enable_completion; | |
245 | u32 frame_rcvd_size; | |
246 | u8 frame_rcvd[32]; | |
247 | u8 phy_attached; | |
248 | u8 phy_state; | |
249 | enum sas_linkrate minimum_linkrate; | |
250 | enum sas_linkrate maximum_linkrate; | |
869ddbdc V |
251 | struct completion *reset_completion; |
252 | bool port_reset_status; | |
253 | bool reset_success; | |
dbf9bfe6 | 254 | }; |
255 | ||
869ddbdc V |
256 | /* port reset status */ |
257 | #define PORT_RESET_SUCCESS 0x00 | |
258 | #define PORT_RESET_TMO 0x01 | |
259 | ||
dbf9bfe6 | 260 | struct pm8001_device { |
aa9f8328 | 261 | enum sas_device_type dev_type; |
dbf9bfe6 | 262 | struct domain_device *sas_device; |
263 | u32 attached_phy; | |
264 | u32 id; | |
265 | struct completion *dcompletion; | |
266 | struct completion *setds_completion; | |
267 | u32 device_id; | |
4a2efd4b | 268 | atomic_t running_req; |
dbf9bfe6 | 269 | }; |
270 | ||
271 | struct pm8001_prd_imt { | |
272 | __le32 len; | |
273 | __le32 e; | |
274 | }; | |
275 | ||
276 | struct pm8001_prd { | |
277 | __le64 addr; /* 64-bit buffer address */ | |
278 | struct pm8001_prd_imt im_len; /* 64-bit length */ | |
279 | } __attribute__ ((packed)); | |
280 | /* | |
281 | * CCB(Command Control Block) | |
282 | */ | |
283 | struct pm8001_ccb_info { | |
dbf9bfe6 | 284 | struct sas_task *task; |
285 | u32 n_elem; | |
286 | u32 ccb_tag; | |
287 | dma_addr_t ccb_dma_handle; | |
288 | struct pm8001_device *device; | |
5a141315 | 289 | struct pm8001_prd *buf_prd; |
dbf9bfe6 | 290 | struct fw_control_ex *fw_control_context; |
5954d738 | 291 | u8 open_retry; |
dbf9bfe6 | 292 | }; |
293 | ||
294 | struct mpi_mem { | |
295 | void *virt_ptr; | |
296 | dma_addr_t phys_addr; | |
297 | u32 phys_addr_hi; | |
298 | u32 phys_addr_lo; | |
299 | u32 total_len; | |
300 | u32 num_elements; | |
301 | u32 element_size; | |
302 | u32 alignment; | |
303 | }; | |
304 | ||
305 | struct mpi_mem_req { | |
306 | /* The number of element in the mpiMemory array */ | |
307 | u32 count; | |
308 | /* The array of structures that define memroy regions*/ | |
309 | struct mpi_mem region[USI_MAX_MEMCNT]; | |
310 | }; | |
311 | ||
e5742101 S |
312 | struct encrypt { |
313 | u32 cipher_mode; | |
314 | u32 sec_mode; | |
315 | u32 status; | |
316 | u32 flag; | |
317 | }; | |
318 | ||
319 | struct sas_phy_attribute_table { | |
320 | u32 phystart1_16[16]; | |
321 | u32 outbound_hw_event_pid1_16[16]; | |
322 | }; | |
323 | ||
324 | union main_cfg_table { | |
325 | struct { | |
dbf9bfe6 | 326 | u32 signature; |
327 | u32 interface_rev; | |
328 | u32 firmware_rev; | |
329 | u32 max_out_io; | |
330 | u32 max_sgl; | |
331 | u32 ctrl_cap_flag; | |
332 | u32 gst_offset; | |
333 | u32 inbound_queue_offset; | |
334 | u32 outbound_queue_offset; | |
335 | u32 inbound_q_nppd_hppd; | |
336 | u32 outbound_hw_event_pid0_3; | |
337 | u32 outbound_hw_event_pid4_7; | |
338 | u32 outbound_ncq_event_pid0_3; | |
339 | u32 outbound_ncq_event_pid4_7; | |
340 | u32 outbound_tgt_ITNexus_event_pid0_3; | |
341 | u32 outbound_tgt_ITNexus_event_pid4_7; | |
342 | u32 outbound_tgt_ssp_event_pid0_3; | |
343 | u32 outbound_tgt_ssp_event_pid4_7; | |
344 | u32 outbound_tgt_smp_event_pid0_3; | |
345 | u32 outbound_tgt_smp_event_pid4_7; | |
346 | u32 upper_event_log_addr; | |
347 | u32 lower_event_log_addr; | |
348 | u32 event_log_size; | |
349 | u32 event_log_option; | |
350 | u32 upper_iop_event_log_addr; | |
351 | u32 lower_iop_event_log_addr; | |
352 | u32 iop_event_log_size; | |
353 | u32 iop_event_log_option; | |
354 | u32 fatal_err_interrupt; | |
355 | u32 fatal_err_dump_offset0; | |
356 | u32 fatal_err_dump_length0; | |
357 | u32 fatal_err_dump_offset1; | |
358 | u32 fatal_err_dump_length1; | |
359 | u32 hda_mode_flag; | |
360 | u32 anolog_setup_table_offset; | |
e5742101 S |
361 | u32 rsvd[4]; |
362 | } pm8001_tbl; | |
363 | ||
364 | struct { | |
365 | u32 signature; | |
366 | u32 interface_rev; | |
367 | u32 firmware_rev; | |
368 | u32 max_out_io; | |
369 | u32 max_sgl; | |
370 | u32 ctrl_cap_flag; | |
371 | u32 gst_offset; | |
372 | u32 inbound_queue_offset; | |
373 | u32 outbound_queue_offset; | |
374 | u32 inbound_q_nppd_hppd; | |
c6b9ef57 S |
375 | u32 rsvd[8]; |
376 | u32 crc_core_dump; | |
377 | u32 rsvd1; | |
e5742101 S |
378 | u32 upper_event_log_addr; |
379 | u32 lower_event_log_addr; | |
380 | u32 event_log_size; | |
381 | u32 event_log_severity; | |
382 | u32 upper_pcs_event_log_addr; | |
383 | u32 lower_pcs_event_log_addr; | |
384 | u32 pcs_event_log_size; | |
385 | u32 pcs_event_log_severity; | |
386 | u32 fatal_err_interrupt; | |
387 | u32 fatal_err_dump_offset0; | |
388 | u32 fatal_err_dump_length0; | |
389 | u32 fatal_err_dump_offset1; | |
390 | u32 fatal_err_dump_length1; | |
391 | u32 gpio_led_mapping; | |
392 | u32 analog_setup_table_offset; | |
393 | u32 int_vec_table_offset; | |
394 | u32 phy_attr_table_offset; | |
395 | u32 port_recovery_timer; | |
396 | u32 interrupt_reassertion_delay; | |
d078b511 | 397 | u32 fatal_n_non_fatal_dump; /* 0x28 */ |
24fff017 V |
398 | u32 ila_version; |
399 | u32 inc_fw_version; | |
e5742101 | 400 | } pm80xx_tbl; |
dbf9bfe6 | 401 | }; |
e5742101 S |
402 | |
403 | union general_status_table { | |
404 | struct { | |
dbf9bfe6 | 405 | u32 gst_len_mpistate; |
406 | u32 iq_freeze_state0; | |
407 | u32 iq_freeze_state1; | |
408 | u32 msgu_tcnt; | |
409 | u32 iop_tcnt; | |
e5742101 | 410 | u32 rsvd; |
dbf9bfe6 | 411 | u32 phy_state[8]; |
e5742101 S |
412 | u32 gpio_input_val; |
413 | u32 rsvd1[2]; | |
414 | u32 recover_err_info[8]; | |
415 | } pm8001_tbl; | |
416 | struct { | |
417 | u32 gst_len_mpistate; | |
418 | u32 iq_freeze_state0; | |
419 | u32 iq_freeze_state1; | |
420 | u32 msgu_tcnt; | |
421 | u32 iop_tcnt; | |
422 | u32 rsvd[9]; | |
423 | u32 gpio_input_val; | |
424 | u32 rsvd1[2]; | |
dbf9bfe6 | 425 | u32 recover_err_info[8]; |
e5742101 | 426 | } pm80xx_tbl; |
dbf9bfe6 | 427 | }; |
428 | struct inbound_queue_table { | |
429 | u32 element_pri_size_cnt; | |
430 | u32 upper_base_addr; | |
431 | u32 lower_base_addr; | |
432 | u32 ci_upper_base_addr; | |
433 | u32 ci_lower_base_addr; | |
434 | u32 pi_pci_bar; | |
435 | u32 pi_offset; | |
436 | u32 total_length; | |
437 | void *base_virt; | |
438 | void *ci_virt; | |
439 | u32 reserved; | |
440 | __le32 consumer_index; | |
441 | u32 producer_idx; | |
05c6c029 | 442 | spinlock_t iq_lock; |
dbf9bfe6 | 443 | }; |
444 | struct outbound_queue_table { | |
445 | u32 element_size_cnt; | |
446 | u32 upper_base_addr; | |
447 | u32 lower_base_addr; | |
448 | void *base_virt; | |
449 | u32 pi_upper_base_addr; | |
450 | u32 pi_lower_base_addr; | |
451 | u32 ci_pci_bar; | |
452 | u32 ci_offset; | |
453 | u32 total_length; | |
454 | void *pi_virt; | |
455 | u32 interrup_vec_cnt_delay; | |
456 | u32 dinterrup_to_pci_offset; | |
457 | __le32 producer_index; | |
458 | u32 consumer_idx; | |
1f02beff | 459 | spinlock_t oq_lock; |
b27a4053 | 460 | unsigned long lock_flags; |
dbf9bfe6 | 461 | }; |
462 | struct pm8001_hba_memspace { | |
463 | void __iomem *memvirtaddr; | |
464 | u64 membase; | |
465 | u32 memsize; | |
466 | }; | |
6cd60b37 NG |
467 | struct isr_param { |
468 | struct pm8001_hba_info *drv_inst; | |
469 | u32 irq_id; | |
470 | }; | |
dbf9bfe6 | 471 | struct pm8001_hba_info { |
472 | char name[PM8001_NAME_LENGTH]; | |
473 | struct list_head list; | |
474 | unsigned long flags; | |
475 | spinlock_t lock;/* host-wide lock */ | |
646cdf00 | 476 | spinlock_t bitmap_lock; |
dbf9bfe6 | 477 | struct pci_dev *pdev;/* our device */ |
478 | struct device *dev; | |
479 | struct pm8001_hba_memspace io_mem[6]; | |
480 | struct mpi_mem_req memoryMap; | |
e5742101 | 481 | struct encrypt encrypt_info; /* support encryption */ |
d078b511 AKS |
482 | struct forensic_data forensic_info; |
483 | u32 fatal_bar_loc; | |
484 | u32 forensic_last_offset; | |
485 | u32 fatal_forensic_shift_offset; | |
486 | u32 forensic_fatal_step; | |
044f59de | 487 | u32 forensic_preserved_accumulated_transfer; |
d078b511 AKS |
488 | u32 evtlog_ib_offset; |
489 | u32 evtlog_ob_offset; | |
dbf9bfe6 | 490 | void __iomem *msg_unit_tbl_addr;/*Message Unit Table Addr*/ |
491 | void __iomem *main_cfg_tbl_addr;/*Main Config Table Addr*/ | |
492 | void __iomem *general_stat_tbl_addr;/*General Status Table Addr*/ | |
493 | void __iomem *inbnd_q_tbl_addr;/*Inbound Queue Config Table Addr*/ | |
494 | void __iomem *outbnd_q_tbl_addr;/*Outbound Queue Config Table Addr*/ | |
e5742101 S |
495 | void __iomem *pspa_q_tbl_addr; |
496 | /*MPI SAS PHY attributes Queue Config Table Addr*/ | |
497 | void __iomem *ivt_tbl_addr; /*MPI IVT Table Addr */ | |
d078b511 | 498 | void __iomem *fatal_tbl_addr; /*MPI IVT Table Addr */ |
e5742101 S |
499 | union main_cfg_table main_cfg_tbl; |
500 | union general_status_table gs_tbl; | |
05c6c029 V |
501 | struct inbound_queue_table inbnd_q_tbl[PM8001_MAX_INB_NUM]; |
502 | struct outbound_queue_table outbnd_q_tbl[PM8001_MAX_OUTB_NUM]; | |
e5742101 S |
503 | struct sas_phy_attribute_table phy_attr_table; |
504 | /* MPI SAS PHY attributes */ | |
dbf9bfe6 | 505 | u8 sas_addr[SAS_ADDR_SIZE]; |
506 | struct sas_ha_struct *sas;/* SCSI/SAS glue */ | |
507 | struct Scsi_Host *shost; | |
508 | u32 chip_id; | |
509 | const struct pm8001_chip_info *chip; | |
510 | struct completion *nvmd_completion; | |
6472cfb4 | 511 | unsigned long *rsvd_tags; |
dbf9bfe6 | 512 | struct pm8001_phy phy[PM8001_MAX_PHYS]; |
513 | struct pm8001_port port[PM8001_MAX_PHYS]; | |
514 | u32 id; | |
515 | u32 irq; | |
e5742101 | 516 | u32 iomb_size; /* SPC and SPCV IOMB size */ |
dbf9bfe6 | 517 | struct pm8001_device *devices; |
518 | struct pm8001_ccb_info *ccb_info; | |
51e6ed83 | 519 | u32 ccb_count; |
efa1fca4 DLM |
520 | |
521 | bool use_msix; | |
dbf9bfe6 | 522 | int number_of_intr;/*will be used in remove()*/ |
72954936 VA |
523 | char intr_drvname[PM8001_MAX_MSIX_VEC] |
524 | [PM8001_NAME_LENGTH+1+3+1]; | |
6cd60b37 | 525 | struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC]; |
dbf9bfe6 | 526 | u32 logging_level; |
3e253d96 | 527 | u32 link_rate; |
dbf9bfe6 | 528 | u32 fw_status; |
f5860992 | 529 | u32 smp_exp_mode; |
72349b62 | 530 | bool controller_fatal_error; |
dbf9bfe6 | 531 | const struct firmware *fw_image; |
6cd60b37 | 532 | struct isr_param irq_vector[PM8001_MAX_MSIX_VEC]; |
dba2cc03 DU |
533 | u32 non_fatal_count; |
534 | u32 non_fatal_read_length; | |
05c6c029 V |
535 | u32 max_q_num; |
536 | u32 ib_offset; | |
537 | u32 ob_offset; | |
538 | u32 ci_offset; | |
539 | u32 pi_offset; | |
540 | u32 max_memcnt; | |
dbf9bfe6 | 541 | }; |
542 | ||
429305e4 TH |
543 | struct pm8001_work { |
544 | struct work_struct work; | |
dbf9bfe6 | 545 | struct pm8001_hba_info *pm8001_ha; |
546 | void *data; | |
547 | int handler; | |
dbf9bfe6 | 548 | }; |
549 | ||
550 | struct pm8001_fw_image_header { | |
551 | u8 vender_id[8]; | |
552 | u8 product_id; | |
553 | u8 hardware_rev; | |
554 | u8 dest_partition; | |
555 | u8 reserved; | |
556 | u8 fw_rev[4]; | |
557 | __be32 image_length; | |
558 | __be32 image_crc; | |
559 | __be32 startup_entry; | |
560 | } __attribute__((packed, aligned(4))); | |
561 | ||
7c8356d9 | 562 | |
dbf9bfe6 | 563 | /** |
564 | * FW Flash Update status values | |
565 | */ | |
566 | #define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 | |
567 | #define FLASH_UPDATE_IN_PROGRESS 0x01 | |
568 | #define FLASH_UPDATE_HDR_ERR 0x02 | |
569 | #define FLASH_UPDATE_OFFSET_ERR 0x03 | |
570 | #define FLASH_UPDATE_CRC_ERR 0x04 | |
571 | #define FLASH_UPDATE_LENGTH_ERR 0x05 | |
572 | #define FLASH_UPDATE_HW_ERR 0x06 | |
573 | #define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 | |
574 | #define FLASH_UPDATE_DISABLED 0x11 | |
575 | ||
3a1ae967 V |
576 | /* Device states */ |
577 | #define DS_OPERATIONAL 0x01 | |
578 | #define DS_PORT_IN_RESET 0x02 | |
579 | #define DS_IN_RECOVERY 0x03 | |
580 | #define DS_IN_ERROR 0x04 | |
581 | #define DS_NON_OPERATIONAL 0x07 | |
582 | ||
dbf9bfe6 | 583 | /** |
584 | * brief param structure for firmware flash update. | |
585 | */ | |
586 | struct fw_flash_updata_info { | |
587 | u32 cur_image_offset; | |
588 | u32 cur_image_len; | |
589 | u32 total_image_len; | |
590 | struct pm8001_prd sgl; | |
591 | }; | |
592 | ||
593 | struct fw_control_info { | |
594 | u32 retcode;/*ret code (status)*/ | |
595 | u32 phase;/*ret code phase*/ | |
596 | u32 phaseCmplt;/*percent complete for the current | |
597 | update phase */ | |
598 | u32 version;/*Hex encoded firmware version number*/ | |
599 | u32 offset;/*Used for downloading firmware */ | |
600 | u32 len; /*len of buffer*/ | |
601 | u32 size;/* Used in OS VPD and Trace get size | |
602 | operations.*/ | |
603 | u32 reserved;/* padding required for 64 bit | |
604 | alignment */ | |
fd2f0452 | 605 | u8 buffer[];/* Start of buffer */ |
dbf9bfe6 | 606 | }; |
607 | struct fw_control_ex { | |
608 | struct fw_control_info *fw_control; | |
609 | void *buffer;/* keep buffer pointer to be | |
25985edc | 610 | freed when the response comes*/ |
dbf9bfe6 | 611 | void *virtAddr;/* keep virtual address of the data */ |
612 | void *usrAddr;/* keep virtual address of the | |
613 | user data */ | |
614 | dma_addr_t phys_addr; | |
615 | u32 len; /* len of buffer */ | |
616 | void *payload; /* pointer to IOCTL Payload */ | |
617 | u8 inProgress;/*if 1 - the IOCTL request is in | |
618 | progress */ | |
619 | void *param1; | |
620 | void *param2; | |
621 | void *param3; | |
622 | }; | |
623 | ||
429305e4 TH |
624 | /* pm8001 workqueue */ |
625 | extern struct workqueue_struct *pm8001_wq; | |
626 | ||
dbf9bfe6 | 627 | /******************** function prototype *********************/ |
628 | int pm8001_tag_alloc(struct pm8001_hba_info *pm8001_ha, u32 *tag_out); | |
dbf9bfe6 | 629 | u32 pm8001_get_ncq_tag(struct sas_task *task, u32 *tag); |
dbf9bfe6 | 630 | void pm8001_ccb_task_free(struct pm8001_hba_info *pm8001_ha, |
304fe11b | 631 | struct pm8001_ccb_info *ccb); |
dbf9bfe6 | 632 | int pm8001_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, |
633 | void *funcdata); | |
dbf9bfe6 | 634 | void pm8001_scan_start(struct Scsi_Host *shost); |
635 | int pm8001_scan_finished(struct Scsi_Host *shost, unsigned long time); | |
79855d17 | 636 | int pm8001_queue_command(struct sas_task *task, gfp_t gfp_flags); |
dbf9bfe6 | 637 | int pm8001_abort_task(struct sas_task *task); |
dbf9bfe6 | 638 | int pm8001_clear_task_set(struct domain_device *dev, u8 *lun); |
639 | int pm8001_dev_found(struct domain_device *dev); | |
640 | void pm8001_dev_gone(struct domain_device *dev); | |
641 | int pm8001_lu_reset(struct domain_device *dev, u8 *lun); | |
642 | int pm8001_I_T_nexus_reset(struct domain_device *dev); | |
a6cb3d01 | 643 | int pm8001_I_T_nexus_event_handler(struct domain_device *dev); |
dbf9bfe6 | 644 | int pm8001_query_task(struct sas_task *task); |
08d0a992 | 645 | void pm8001_port_formed(struct asd_sas_phy *sas_phy); |
5954d738 MS |
646 | void pm8001_open_reject_retry( |
647 | struct pm8001_hba_info *pm8001_ha, | |
648 | struct sas_task *task_to_close, | |
649 | struct pm8001_device *device_to_close); | |
dbf9bfe6 | 650 | int pm8001_mem_alloc(struct pci_dev *pdev, void **virt_addr, |
651 | dma_addr_t *pphys_addr, u32 *pphys_addr_hi, u32 *pphys_addr_lo, | |
652 | u32 mem_size, u32 align); | |
653 | ||
f74cf271 S |
654 | void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha); |
655 | int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, | |
f91767a3 | 656 | u32 q_index, u32 opCode, void *payload, size_t nb, |
91a43fa6 | 657 | u32 responseQueue); |
f74cf271 S |
658 | int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ, |
659 | u16 messageSize, void **messagePtr); | |
660 | u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, | |
661 | struct outbound_queue_table *circularQ, u8 bc); | |
662 | u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, | |
663 | struct outbound_queue_table *circularQ, | |
664 | void **messagePtr1, u8 *pBC); | |
665 | int pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, | |
666 | struct pm8001_device *pm8001_dev, u32 state); | |
667 | int pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, | |
668 | void *payload); | |
669 | int pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, | |
670 | void *fw_flash_updata_info, u32 tag); | |
671 | int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); | |
672 | int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, void *payload); | |
673 | int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, | |
674 | struct pm8001_ccb_info *ccb, | |
bbfe82cd | 675 | struct sas_tmf_task *tmf); |
f74cf271 | 676 | int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, |
2cbbf489 | 677 | struct pm8001_ccb_info *ccb); |
f74cf271 S |
678 | int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, u32 device_id); |
679 | void pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd); | |
680 | void pm8001_work_fn(struct work_struct *work); | |
681 | int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, | |
682 | void *data, int handler); | |
683 | void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, | |
684 | void *piomb); | |
685 | void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, | |
686 | void *piomb); | |
687 | void pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, | |
688 | void *piomb); | |
689 | int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, | |
690 | void *piomb); | |
691 | void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate); | |
692 | void pm8001_get_attached_sas_addr(struct pm8001_phy *phy, u8 *sas_addr); | |
693 | void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i); | |
694 | int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); | |
695 | int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); | |
696 | int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, | |
697 | void *piomb); | |
8a23dbc6 | 698 | int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb); |
f74cf271 | 699 | int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb); |
c6b9ef57 S |
700 | void pm8001_tag_free(struct pm8001_hba_info *pm8001_ha, u32 tag); |
701 | struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha, | |
702 | u32 device_id); | |
a6cb3d01 | 703 | int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha); |
f74cf271 | 704 | |
d95d0001 | 705 | int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); |
27909407 AKS |
706 | void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha, |
707 | u32 length, u8 *buf); | |
c5614df7 BR |
708 | void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha, |
709 | u32 phy, u32 length, u32 *buf); | |
d078b511 AKS |
710 | int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue); |
711 | ssize_t pm80xx_get_fatal_dump(struct device *cdev, | |
712 | struct device_attribute *attr, char *buf); | |
dba2cc03 DU |
713 | ssize_t pm80xx_get_non_fatal_dump(struct device *cdev, |
714 | struct device_attribute *attr, char *buf); | |
d078b511 | 715 | ssize_t pm8001_get_gsm_dump(struct device *cdev, u32, char *buf); |
a961ea0a | 716 | int pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha); |
4f5deeb4 | 717 | void pm8001_free_dev(struct pm8001_device *pm8001_dev); |
dbf9bfe6 | 718 | /* ctl shared API */ |
c03b72b8 | 719 | extern const struct attribute_group *pm8001_host_groups[]; |
dbf9bfe6 | 720 | |
7fb23a78 DLM |
721 | #define PM8001_INVALID_TAG ((u32)-1) |
722 | ||
99df0edb DLM |
723 | /* |
724 | * Allocate a new tag and return the corresponding ccb after initializing it. | |
725 | */ | |
726 | static inline struct pm8001_ccb_info * | |
727 | pm8001_ccb_alloc(struct pm8001_hba_info *pm8001_ha, | |
728 | struct pm8001_device *dev, struct sas_task *task) | |
729 | { | |
730 | struct pm8001_ccb_info *ccb; | |
6472cfb4 | 731 | struct request *rq = NULL; |
99df0edb DLM |
732 | u32 tag; |
733 | ||
6472cfb4 JG |
734 | if (task) |
735 | rq = sas_task_find_rq(task); | |
736 | ||
737 | if (rq) { | |
738 | tag = rq->tag + PM8001_RESERVE_SLOT; | |
739 | } else if (pm8001_tag_alloc(pm8001_ha, &tag)) { | |
99df0edb DLM |
740 | pm8001_dbg(pm8001_ha, FAIL, "Failed to allocate a tag\n"); |
741 | return NULL; | |
742 | } | |
743 | ||
744 | ccb = &pm8001_ha->ccb_info[tag]; | |
745 | ccb->task = task; | |
746 | ccb->n_elem = 0; | |
747 | ccb->ccb_tag = tag; | |
748 | ccb->device = dev; | |
749 | ccb->fw_control_context = NULL; | |
750 | ccb->open_retry = 0; | |
751 | ||
752 | return ccb; | |
753 | } | |
754 | ||
755 | /* | |
756 | * Free the tag of an initialized ccb. | |
757 | */ | |
758 | static inline void pm8001_ccb_free(struct pm8001_hba_info *pm8001_ha, | |
759 | struct pm8001_ccb_info *ccb) | |
760 | { | |
761 | u32 tag = ccb->ccb_tag; | |
762 | ||
763 | /* | |
764 | * Cleanup the ccb to make sure that a manual scan of the adapter | |
765 | * ccb_info array can detect ccb's that are in use. | |
766 | * C.f. pm8001_open_reject_retry() | |
767 | */ | |
768 | ccb->task = NULL; | |
769 | ccb->ccb_tag = PM8001_INVALID_TAG; | |
770 | ccb->device = NULL; | |
771 | ccb->fw_control_context = NULL; | |
772 | ||
773 | pm8001_tag_free(pm8001_ha, tag); | |
774 | } | |
775 | ||
304fe11b DLM |
776 | static inline void pm8001_ccb_task_free_done(struct pm8001_hba_info *pm8001_ha, |
777 | struct pm8001_ccb_info *ccb) | |
2b01d816 | 778 | { |
304fe11b DLM |
779 | struct sas_task *task = ccb->task; |
780 | ||
781 | pm8001_ccb_task_free(pm8001_ha, ccb); | |
2b01d816 | 782 | smp_mb(); /*in order to force CPU ordering*/ |
2b01d816 | 783 | task->task_done(task); |
2b01d816 | 784 | } |
2037a340 | 785 | void pm8001_setds_completion(struct domain_device *dev); |
693e66a0 | 786 | void pm8001_tmf_aborted(struct sas_task *task); |
2b01d816 | 787 | |
dbf9bfe6 | 788 | #endif |
789 |