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[SCSI] qla2xxx: Do not restrict the number of NPIV ports for ISP83xx.
[people/ms/linux.git] / drivers / scsi / qla2xxx / qla_nx.c
CommitLineData
a9083016
GM		 1/*
2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
a9083016
GM		 4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/pci.h>
08de2844
GM		 10#include <linux/ratelimit.h>
11#include <linux/vmalloc.h>
ff2fc42e 12#include <scsi/scsi_tcq.h>
a9083016
GM		 13
14#define MASK(n) ((1ULL<<(n))-1)
15#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19#define MS_WIN(addr) (addr & 0x0ffc0000)
20#define QLA82XX_PCI_MN_2M (0)
21#define QLA82XX_PCI_MS_2M (0x80000)
22#define QLA82XX_PCI_OCM0_2M (0xc0000)
23#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
0547fb37 25#define BLOCK_PROTECT_BITS 0x0F
a9083016
GM		 26
27/* CRB window related */
28#define CRB_BLK(off) ((off >> 20) & 0x3f)
29#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30#define CRB_WINDOW_2M (0x130060)
31#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35#define CRB_INDIRECT_2M (0x1e0000UL)
36
a9083016
GM		 37#define MAX_CRB_XFORM 60
38static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39int qla82xx_crb_table_initialized;
40
41#define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45static void qla82xx_crb_addr_transform_setup(void)
46{
47 qla82xx_crb_addr_transform(XDMA);
48 qla82xx_crb_addr_transform(TIMR);
49 qla82xx_crb_addr_transform(SRE);
50 qla82xx_crb_addr_transform(SQN3);
51 qla82xx_crb_addr_transform(SQN2);
52 qla82xx_crb_addr_transform(SQN1);
53 qla82xx_crb_addr_transform(SQN0);
54 qla82xx_crb_addr_transform(SQS3);
55 qla82xx_crb_addr_transform(SQS2);
56 qla82xx_crb_addr_transform(SQS1);
57 qla82xx_crb_addr_transform(SQS0);
58 qla82xx_crb_addr_transform(RPMX7);
59 qla82xx_crb_addr_transform(RPMX6);
60 qla82xx_crb_addr_transform(RPMX5);
61 qla82xx_crb_addr_transform(RPMX4);
62 qla82xx_crb_addr_transform(RPMX3);
63 qla82xx_crb_addr_transform(RPMX2);
64 qla82xx_crb_addr_transform(RPMX1);
65 qla82xx_crb_addr_transform(RPMX0);
66 qla82xx_crb_addr_transform(ROMUSB);
67 qla82xx_crb_addr_transform(SN);
68 qla82xx_crb_addr_transform(QMN);
69 qla82xx_crb_addr_transform(QMS);
70 qla82xx_crb_addr_transform(PGNI);
71 qla82xx_crb_addr_transform(PGND);
72 qla82xx_crb_addr_transform(PGN3);
73 qla82xx_crb_addr_transform(PGN2);
74 qla82xx_crb_addr_transform(PGN1);
75 qla82xx_crb_addr_transform(PGN0);
76 qla82xx_crb_addr_transform(PGSI);
77 qla82xx_crb_addr_transform(PGSD);
78 qla82xx_crb_addr_transform(PGS3);
79 qla82xx_crb_addr_transform(PGS2);
80 qla82xx_crb_addr_transform(PGS1);
81 qla82xx_crb_addr_transform(PGS0);
82 qla82xx_crb_addr_transform(PS);
83 qla82xx_crb_addr_transform(PH);
84 qla82xx_crb_addr_transform(NIU);
85 qla82xx_crb_addr_transform(I2Q);
86 qla82xx_crb_addr_transform(EG);
87 qla82xx_crb_addr_transform(MN);
88 qla82xx_crb_addr_transform(MS);
89 qla82xx_crb_addr_transform(CAS2);
90 qla82xx_crb_addr_transform(CAS1);
91 qla82xx_crb_addr_transform(CAS0);
92 qla82xx_crb_addr_transform(CAM);
93 qla82xx_crb_addr_transform(C2C1);
94 qla82xx_crb_addr_transform(C2C0);
95 qla82xx_crb_addr_transform(SMB);
96 qla82xx_crb_addr_transform(OCM0);
97 /*
98 * Used only in P3 just define it for P2 also.
99 */
100 qla82xx_crb_addr_transform(I2C0);
101
102 qla82xx_crb_table_initialized = 1;
103}
104
105struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
106 {{{0, 0, 0, 0} } },
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
124 {{{0, 0, 0, 0} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{0, 0, 0, 0} } },
209 {{{0, 0, 0, 0} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
213 {{{0} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
231 {{{0} } },
232 {{{0} } },
233 {{{0} } },
234 {{{0} } },
235 {{{0} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
248 {{{0} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
255 {{{0} } },
256 {{{0} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
260};
261
262/*
263 * top 12 bits of crb internal address (hub, agent)
264 */
265unsigned qla82xx_crb_hub_agt[64] = {
266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
270 0,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
293 0,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
301 0,
302 0,
303 0,
304 0,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
307 0,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
318 0,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
327 0,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
329 0,
330};
331
f1af6208 332/* Device states */
08de2844 333char *q_dev_state[] = {
f1af6208
GM		 334 "Unknown",
335 "Cold",
336 "Initializing",
337 "Ready",
338 "Need Reset",
339 "Need Quiescent",
340 "Failed",
341 "Quiescent",
342};
343
08de2844
GM		 344char *qdev_state(uint32_t dev_state)
345{
346 return q_dev_state[dev_state];
347}
348
a9083016
GM		 349/*
350 * In: 'off' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr
352 * side effect: lock crb window
353 */
354static void
355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
356{
357 u32 win_read;
7c3df132 358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
362 (void *)(CRB_WINDOW_2M + ha->nx_pcibase));
363
364 /* Read back value to make sure write has gone through before trying
365 * to use it.
366 */
367 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
368 if (win_read != ha->crb_win) {
7c3df132
SK		 369 ql_dbg(ql_dbg_p3p, vha, 0xb000,
370 "%s: Written crbwin (0x%x) "
371 "!= Read crbwin (0x%x), off=0x%lx.\n",
d8424f68 372 __func__, ha->crb_win, win_read, *off);
a9083016
GM		 373 }
374 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
375}
376
377static inline unsigned long
378qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
379{
7c3df132 380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 381 /* See if we are currently pointing to the region we want to use next */
382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
383 /* No need to change window. PCIX and PCIEregs are in both
384 * regs are in both windows.
385 */
386 return off;
387 }
388
389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
390 /* We are in first CRB window */
391 if (ha->curr_window != 0)
392 WARN_ON(1);
393 return off;
394 }
395
396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
397 /* We are in second CRB window */
398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
399
400 if (ha->curr_window != 1)
401 return off;
402
403 /* We are in the QM or direct access
404 * register region - do nothing
405 */
406 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
407 (off < QLA82XX_PCI_CAMQM_MAX))
408 return off;
409 }
410 /* strange address given */
7c3df132 411 ql_dbg(ql_dbg_p3p, vha, 0xb001,
d8424f68 412 "%s: Warning: unm_nic_pci_set_crbwindow "
7c3df132
SK		 413 "called with an unknown address(%llx).\n",
414 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 415 return off;
416}
417
77e334d2
GM		 418static int
419qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
420{
421 struct crb_128M_2M_sub_block_map *m;
422
423 if (*off >= QLA82XX_CRB_MAX)
424 return -1;
425
426 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
427 *off = (*off - QLA82XX_PCI_CAMQM) +
428 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
429 return 0;
430 }
431
432 if (*off < QLA82XX_PCI_CRBSPACE)
433 return -1;
434
435 *off -= QLA82XX_PCI_CRBSPACE;
436
437 /* Try direct map */
438 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
439
440 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
441 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
442 return 0;
443 }
444 /* Not in direct map, use crb window */
445 return 1;
446}
447
448#define CRB_WIN_LOCK_TIMEOUT 100000000
449static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
450{
451 int done = 0, timeout = 0;
452
453 while (!done) {
454 /* acquire semaphore3 from PCI HW block */
455 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
456 if (done == 1)
457 break;
458 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
459 return -1;
460 timeout++;
461 }
462 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
463 return 0;
464}
465
a9083016
GM		 466int
467qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
468{
469 unsigned long flags = 0;
470 int rv;
471
472 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
473
474 BUG_ON(rv == -1);
475
476 if (rv == 1) {
477 write_lock_irqsave(&ha->hw_lock, flags);
478 qla82xx_crb_win_lock(ha);
479 qla82xx_pci_set_crbwindow_2M(ha, &off);
480 }
481
482 writel(data, (void __iomem *)off);
483
484 if (rv == 1) {
485 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
486 write_unlock_irqrestore(&ha->hw_lock, flags);
487 }
488 return 0;
489}
490
491int
492qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
493{
494 unsigned long flags = 0;
495 int rv;
496 u32 data;
497
498 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
499
500 BUG_ON(rv == -1);
501
502 if (rv == 1) {
503 write_lock_irqsave(&ha->hw_lock, flags);
504 qla82xx_crb_win_lock(ha);
505 qla82xx_pci_set_crbwindow_2M(ha, &off);
506 }
507 data = RD_REG_DWORD((void __iomem *)off);
508
509 if (rv == 1) {
510 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
511 write_unlock_irqrestore(&ha->hw_lock, flags);
512 }
513 return data;
514}
515
a9083016
GM		 516#define IDC_LOCK_TIMEOUT 100000000
517int qla82xx_idc_lock(struct qla_hw_data *ha)
518{
519 int i;
520 int done = 0, timeout = 0;
521
522 while (!done) {
523 /* acquire semaphore5 from PCI HW block */
524 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
525 if (done == 1)
526 break;
527 if (timeout >= IDC_LOCK_TIMEOUT)
528 return -1;
529
530 timeout++;
531
532 /* Yield CPU */
533 if (!in_interrupt())
534 schedule();
535 else {
536 for (i = 0; i < 20; i++)
537 cpu_relax();
538 }
539 }
540
541 return 0;
542}
543
544void qla82xx_idc_unlock(struct qla_hw_data *ha)
545{
546 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
547}
548
a9083016
GM		 549/* PCI Windowing for DDR regions. */
550#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
551 (((addr) <= (high)) && ((addr) >= (low)))
552/*
553 * check memory access boundary.
554 * used by test agent. support ddr access only for now
555 */
556static unsigned long
557qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
558 unsigned long long addr, int size)
559{
560 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
561 QLA82XX_ADDR_DDR_NET_MAX) ||
562 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
563 QLA82XX_ADDR_DDR_NET_MAX) ||
564 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
565 return 0;
566 else
567 return 1;
568}
569
570int qla82xx_pci_set_window_warning_count;
571
77e334d2 572static unsigned long
a9083016
GM		 573qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
574{
575 int window;
576 u32 win_read;
7c3df132 577 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 578
579 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
580 QLA82XX_ADDR_DDR_NET_MAX)) {
581 /* DDR network side */
582 window = MN_WIN(addr);
583 ha->ddr_mn_window = window;
584 qla82xx_wr_32(ha,
585 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
586 win_read = qla82xx_rd_32(ha,
587 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
588 if ((win_read << 17) != window) {
7c3df132
SK		 589 ql_dbg(ql_dbg_p3p, vha, 0xb003,
590 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
a9083016
GM		 591 __func__, window, win_read);
592 }
593 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
594 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
595 QLA82XX_ADDR_OCM0_MAX)) {
596 unsigned int temp1;
597 if ((addr & 0x00ff800) == 0xff800) {
7c3df132 598 ql_log(ql_log_warn, vha, 0xb004,
a9083016
GM		 599 "%s: QM access not handled.\n", __func__);
600 addr = -1UL;
601 }
602 window = OCM_WIN(addr);
603 ha->ddr_mn_window = window;
604 qla82xx_wr_32(ha,
605 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
606 win_read = qla82xx_rd_32(ha,
607 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
608 temp1 = ((window & 0x1FF) << 7) |
609 ((window & 0x0FFFE0000) >> 17);
610 if (win_read != temp1) {
7c3df132
SK		 611 ql_log(ql_log_warn, vha, 0xb005,
612 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
a9083016
GM		 613 __func__, temp1, win_read);
614 }
615 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
616
617 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
618 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
619 /* QDR network side */
620 window = MS_WIN(addr);
621 ha->qdr_sn_window = window;
622 qla82xx_wr_32(ha,
623 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
624 win_read = qla82xx_rd_32(ha,
625 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
626 if (win_read != window) {
7c3df132
SK		 627 ql_log(ql_log_warn, vha, 0xb006,
628 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
a9083016
GM		 629 __func__, window, win_read);
630 }
631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
632 } else {
633 /*
634 * peg gdb frequently accesses memory that doesn't exist,
635 * this limits the chit chat so debugging isn't slowed down.
636 */
637 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
638 (qla82xx_pci_set_window_warning_count%64 == 0)) {
7c3df132
SK		 639 ql_log(ql_log_warn, vha, 0xb007,
640 "%s: Warning:%s Unknown address range!.\n",
641 __func__, QLA2XXX_DRIVER_NAME);
a9083016
GM		 642 }
643 addr = -1UL;
644 }
645 return addr;
646}
647
648/* check if address is in the same windows as the previous access */
649static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
650 unsigned long long addr)
651{
652 int window;
653 unsigned long long qdr_max;
654
655 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
656
657 /* DDR network side */
658 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
659 QLA82XX_ADDR_DDR_NET_MAX))
660 BUG();
661 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
662 QLA82XX_ADDR_OCM0_MAX))
663 return 1;
664 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
665 QLA82XX_ADDR_OCM1_MAX))
666 return 1;
667 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
668 /* QDR network side */
669 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
670 if (ha->qdr_sn_window == window)
671 return 1;
672 }
673 return 0;
674}
675
676static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
677 u64 off, void *data, int size)
678{
679 unsigned long flags;
f1af6208 680 void *addr = NULL;
a9083016
GM		 681 int ret = 0;
682 u64 start;
683 uint8_t *mem_ptr = NULL;
684 unsigned long mem_base;
685 unsigned long mem_page;
7c3df132 686 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 687
688 write_lock_irqsave(&ha->hw_lock, flags);
689
690 /*
691 * If attempting to access unknown address or straddle hw windows,
692 * do not access.
693 */
694 start = qla82xx_pci_set_window(ha, off);
695 if ((start == -1UL) ||
696 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
697 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 698 ql_log(ql_log_fatal, vha, 0xb008,
699 "%s out of bound pci memory "
700 "access, offset is 0x%llx.\n",
701 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 702 return -1;
703 }
704
f1af6208
GM		 705 write_unlock_irqrestore(&ha->hw_lock, flags);
706 mem_base = pci_resource_start(ha->pdev, 0);
707 mem_page = start & PAGE_MASK;
708 /* Map two pages whenever user tries to access addresses in two
709 * consecutive pages.
710 */
711 if (mem_page != ((start + size - 1) & PAGE_MASK))
712 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
713 else
714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
715 if (mem_ptr == 0UL) {
716 *(u8 *)data = 0;
717 return -1;
a9083016 718 }
f1af6208
GM		 719 addr = mem_ptr;
720 addr += start & (PAGE_SIZE - 1);
721 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 722
723 switch (size) {
724 case 1:
725 *(u8 *)data = readb(addr);
726 break;
727 case 2:
728 *(u16 *)data = readw(addr);
729 break;
730 case 4:
731 *(u32 *)data = readl(addr);
732 break;
733 case 8:
734 *(u64 *)data = readq(addr);
735 break;
736 default:
737 ret = -1;
738 break;
739 }
740 write_unlock_irqrestore(&ha->hw_lock, flags);
741
742 if (mem_ptr)
743 iounmap(mem_ptr);
744 return ret;
745}
746
747static int
748qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
749 u64 off, void *data, int size)
750{
751 unsigned long flags;
f1af6208 752 void *addr = NULL;
a9083016
GM		 753 int ret = 0;
754 u64 start;
755 uint8_t *mem_ptr = NULL;
756 unsigned long mem_base;
757 unsigned long mem_page;
7c3df132 758 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 759
760 write_lock_irqsave(&ha->hw_lock, flags);
761
762 /*
763 * If attempting to access unknown address or straddle hw windows,
764 * do not access.
765 */
766 start = qla82xx_pci_set_window(ha, off);
767 if ((start == -1UL) ||
768 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
769 write_unlock_irqrestore(&ha->hw_lock, flags);
7c3df132
SK		 770 ql_log(ql_log_fatal, vha, 0xb009,
771 "%s out of bount memory "
772 "access, offset is 0x%llx.\n",
773 QLA2XXX_DRIVER_NAME, off);
a9083016
GM		 774 return -1;
775 }
776
f1af6208
GM		 777 write_unlock_irqrestore(&ha->hw_lock, flags);
778 mem_base = pci_resource_start(ha->pdev, 0);
779 mem_page = start & PAGE_MASK;
780 /* Map two pages whenever user tries to access addresses in two
781 * consecutive pages.
782 */
783 if (mem_page != ((start + size - 1) & PAGE_MASK))
784 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
785 else
786 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
787 if (mem_ptr == 0UL)
788 return -1;
a9083016 789
f1af6208
GM		 790 addr = mem_ptr;
791 addr += start & (PAGE_SIZE - 1);
792 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 793
794 switch (size) {
795 case 1:
796 writeb(*(u8 *)data, addr);
797 break;
798 case 2:
799 writew(*(u16 *)data, addr);
800 break;
801 case 4:
802 writel(*(u32 *)data, addr);
803 break;
804 case 8:
805 writeq(*(u64 *)data, addr);
806 break;
807 default:
808 ret = -1;
809 break;
810 }
811 write_unlock_irqrestore(&ha->hw_lock, flags);
812 if (mem_ptr)
813 iounmap(mem_ptr);
814 return ret;
815}
816
a9083016 817#define MTU_FUDGE_FACTOR 100
77e334d2
GM		 818static unsigned long
819qla82xx_decode_crb_addr(unsigned long addr)
a9083016
GM		 820{
821 int i;
822 unsigned long base_addr, offset, pci_base;
823
824 if (!qla82xx_crb_table_initialized)
825 qla82xx_crb_addr_transform_setup();
826
827 pci_base = ADDR_ERROR;
828 base_addr = addr & 0xfff00000;
829 offset = addr & 0x000fffff;
830
831 for (i = 0; i < MAX_CRB_XFORM; i++) {
832 if (crb_addr_xform[i] == base_addr) {
833 pci_base = i << 20;
834 break;
835 }
836 }
837 if (pci_base == ADDR_ERROR)
838 return pci_base;
839 return pci_base + offset;
840}
841
842static long rom_max_timeout = 100;
843static long qla82xx_rom_lock_timeout = 100;
844
77e334d2 845static int
a9083016
GM		 846qla82xx_rom_lock(struct qla_hw_data *ha)
847{
848 int done = 0, timeout = 0;
849
850 while (!done) {
851 /* acquire semaphore2 from PCI HW block */
852 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
853 if (done == 1)
854 break;
855 if (timeout >= qla82xx_rom_lock_timeout)
856 return -1;
857 timeout++;
858 }
859 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
860 return 0;
861}
862
d652e093
CD		 863static void
864qla82xx_rom_unlock(struct qla_hw_data *ha)
865{
866 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
867}
868
77e334d2 869static int
a9083016
GM		 870qla82xx_wait_rom_busy(struct qla_hw_data *ha)
871{
872 long timeout = 0;
873 long done = 0 ;
7c3df132 874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 875
876 while (done == 0) {
877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
878 done &= 4;
879 timeout++;
880 if (timeout >= rom_max_timeout) {
7c3df132
SK		 881 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
882 "%s: Timeout reached waiting for rom busy.\n",
883 QLA2XXX_DRIVER_NAME);
a9083016
GM		 884 return -1;
885 }
886 }
887 return 0;
888}
889
77e334d2 890static int
a9083016
GM		 891qla82xx_wait_rom_done(struct qla_hw_data *ha)
892{
893 long timeout = 0;
894 long done = 0 ;
7c3df132 895 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 896
897 while (done == 0) {
898 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
899 done &= 2;
900 timeout++;
901 if (timeout >= rom_max_timeout) {
7c3df132
SK		 902 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
903 "%s: Timeout reached waiting for rom done.\n",
904 QLA2XXX_DRIVER_NAME);
a9083016
GM		 905 return -1;
906 }
907 }
908 return 0;
909}
910
2b29d96d
CD		 911int
912qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
913{
914 uint32_t off_value, rval = 0;
915
916 WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase),
917 (off & 0xFFFF0000));
918
919 /* Read back value to make sure write has gone through */
920 RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
921 off_value = (off & 0x0000FFFF);
922
923 if (flag)
924 WRT_REG_DWORD((void *)
925 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
926 data);
927 else
928 rval = RD_REG_DWORD((void *)
929 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
930
931 return rval;
932}
933
77e334d2 934static int
a9083016
GM		 935qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
936{
2b29d96d
CD		 937 /* Dword reads to flash. */
938 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
939 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
940 (addr & 0x0000FFFF), 0, 0);
7c3df132 941
a9083016
GM		 942 return 0;
943}
944
77e334d2 945static int
a9083016
GM		 946qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
947{
948 int ret, loops = 0;
7c3df132 949 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 950
951 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
952 udelay(100);
953 schedule();
954 loops++;
955 }
956 if (loops >= 50000) {
7c3df132
SK		 957 ql_log(ql_log_fatal, vha, 0x00b9,
958 "Failed to aquire SEM2 lock.\n");
a9083016
GM		 959 return -1;
960 }
961 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
d652e093 962 qla82xx_rom_unlock(ha);
a9083016
GM		 963 return ret;
964}
965
77e334d2 966static int
a9083016
GM		 967qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
968{
7c3df132 969 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 970 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
971 qla82xx_wait_rom_busy(ha);
972 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 973 ql_log(ql_log_warn, vha, 0xb00c,
974 "Error waiting for rom done.\n");
a9083016
GM		 975 return -1;
976 }
977 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
978 return 0;
979}
980
77e334d2 981static int
a9083016
GM		 982qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
983{
984 long timeout = 0;
985 uint32_t done = 1 ;
986 uint32_t val;
987 int ret = 0;
7c3df132 988 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 989
990 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
991 while ((done != 0) && (ret == 0)) {
992 ret = qla82xx_read_status_reg(ha, &val);
993 done = val & 1;
994 timeout++;
995 udelay(10);
996 cond_resched();
997 if (timeout >= 50000) {
7c3df132
SK		 998 ql_log(ql_log_warn, vha, 0xb00d,
999 "Timeout reached waiting for write finish.\n");
a9083016
GM		 1000 return -1;
1001 }
1002 }
1003 return ret;
1004}
1005
77e334d2 1006static int
a9083016
GM		 1007qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1008{
1009 uint32_t val;
1010 qla82xx_wait_rom_busy(ha);
1011 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1012 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1013 qla82xx_wait_rom_busy(ha);
1014 if (qla82xx_wait_rom_done(ha))
1015 return -1;
1016 if (qla82xx_read_status_reg(ha, &val) != 0)
1017 return -1;
1018 if ((val & 2) != 2)
1019 return -1;
1020 return 0;
1021}
1022
77e334d2 1023static int
a9083016
GM		 1024qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1025{
7c3df132 1026 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1027 if (qla82xx_flash_set_write_enable(ha))
1028 return -1;
1029 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1030 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1031 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1032 ql_log(ql_log_warn, vha, 0xb00e,
1033 "Error waiting for rom done.\n");
a9083016
GM		 1034 return -1;
1035 }
1036 return qla82xx_flash_wait_write_finish(ha);
1037}
1038
77e334d2 1039static int
a9083016
GM		 1040qla82xx_write_disable_flash(struct qla_hw_data *ha)
1041{
7c3df132 1042 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1043 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1044 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1045 ql_log(ql_log_warn, vha, 0xb00f,
1046 "Error waiting for rom done.\n");
a9083016
GM		 1047 return -1;
1048 }
1049 return 0;
1050}
1051
77e334d2 1052static int
a9083016
GM		 1053ql82xx_rom_lock_d(struct qla_hw_data *ha)
1054{
1055 int loops = 0;
7c3df132
SK		 1056 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1057
a9083016
GM		 1058 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1059 udelay(100);
1060 cond_resched();
1061 loops++;
1062 }
1063 if (loops >= 50000) {
7c3df132
SK		 1064 ql_log(ql_log_warn, vha, 0xb010,
1065 "ROM lock failed.\n");
a9083016
GM		 1066 return -1;
1067 }
cd6dbb03 1068 return 0;
a9083016
GM		 1069}
1070
77e334d2 1071static int
a9083016
GM		 1072qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1073 uint32_t data)
1074{
1075 int ret = 0;
7c3df132 1076 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1077
1078 ret = ql82xx_rom_lock_d(ha);
1079 if (ret < 0) {
7c3df132
SK		 1080 ql_log(ql_log_warn, vha, 0xb011,
1081 "ROM lock failed.\n");
a9083016
GM		 1082 return ret;
1083 }
1084
1085 if (qla82xx_flash_set_write_enable(ha))
1086 goto done_write;
1087
1088 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1089 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1090 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1091 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1092 qla82xx_wait_rom_busy(ha);
1093 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 1094 ql_log(ql_log_warn, vha, 0xb012,
1095 "Error waiting for rom done.\n");
a9083016
GM		 1096 ret = -1;
1097 goto done_write;
1098 }
1099
1100 ret = qla82xx_flash_wait_write_finish(ha);
1101
1102done_write:
d652e093 1103 qla82xx_rom_unlock(ha);
a9083016
GM		 1104 return ret;
1105}
1106
1107/* This routine does CRB initialize sequence
1108 * to put the ISP into operational state
1109 */
77e334d2
GM		 1110static int
1111qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
a9083016
GM		 1112{
1113 int addr, val;
1114 int i ;
1115 struct crb_addr_pair *buf;
1116 unsigned long off;
1117 unsigned offset, n;
1118 struct qla_hw_data *ha = vha->hw;
1119
1120 struct crb_addr_pair {
1121 long addr;
1122 long data;
1123 };
1124
1125 /* Halt all the indiviual PEGs and other blocks of the ISP */
1126 qla82xx_rom_lock(ha);
c9e8fd5c 1127
02be2215
GM		 1128 /* disable all I2Q */
1129 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1130 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1131 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1132 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1133 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1134 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1135
1136 /* disable all niu interrupts */
c9e8fd5c
MI		 1137 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1138 /* disable xge rx/tx */
1139 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1140 /* disable xg1 rx/tx */
1141 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
02be2215
GM		 1142 /* disable sideband mac */
1143 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1144 /* disable ap0 mac */
1145 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1146 /* disable ap1 mac */
1147 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
c9e8fd5c
MI		 1148
1149 /* halt sre */
1150 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1151 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1152
1153 /* halt epg */
1154 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1155
1156 /* halt timers */
1157 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1158 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1159 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1160 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1161 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
02be2215 1162 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
c9e8fd5c
MI		 1163
1164 /* halt pegs */
1165 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1166 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1167 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1168 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1169 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
02be2215 1170 msleep(20);
c9e8fd5c
MI		 1171
1172 /* big hammer */
a9083016
GM		 1173 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1174 /* don't reset CAM block on reset */
1175 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1176 else
1177 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
d652e093 1178 qla82xx_rom_unlock(ha);
a9083016
GM		 1179
1180 /* Read the signature value from the flash.
1181 * Offset 0: Contain signature (0xcafecafe)
1182 * Offset 4: Offset and number of addr/value pairs
1183 * that present in CRB initialize sequence
1184 */
1185 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1186 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
7c3df132
SK		 1187 ql_log(ql_log_fatal, vha, 0x006e,
1188 "Error Reading crb_init area: n: %08x.\n", n);
a9083016
GM		 1189 return -1;
1190 }
1191
1192 /* Offset in flash = lower 16 bits
00adc9a0 1193 * Number of entries = upper 16 bits
a9083016
GM		 1194 */
1195 offset = n & 0xffffU;
1196 n = (n >> 16) & 0xffffU;
1197
00adc9a0 1198 /* number of addr/value pair should not exceed 1024 entries */
a9083016 1199 if (n >= 1024) {
7c3df132
SK		 1200 ql_log(ql_log_fatal, vha, 0x0071,
1201 "Card flash not initialized:n=0x%x.\n", n);
a9083016
GM		 1202 return -1;
1203 }
1204
7c3df132
SK		 1205 ql_log(ql_log_info, vha, 0x0072,
1206 "%d CRB init values found in ROM.\n", n);
a9083016
GM		 1207
1208 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1209 if (buf == NULL) {
7c3df132
SK		 1210 ql_log(ql_log_fatal, vha, 0x010c,
1211 "Unable to allocate memory.\n");
a9083016
GM		 1212 return -1;
1213 }
1214
1215 for (i = 0; i < n; i++) {
1216 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1217 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1218 kfree(buf);
1219 return -1;
1220 }
1221
1222 buf[i].addr = addr;
1223 buf[i].data = val;
1224 }
1225
1226 for (i = 0; i < n; i++) {
1227 /* Translate internal CRB initialization
1228 * address to PCI bus address
1229 */
1230 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1231 QLA82XX_PCI_CRBSPACE;
1232 /* Not all CRB addr/value pair to be written,
1233 * some of them are skipped
1234 */
1235
1236 /* skipping cold reboot MAGIC */
1237 if (off == QLA82XX_CAM_RAM(0x1fc))
1238 continue;
1239
1240 /* do not reset PCI */
1241 if (off == (ROMUSB_GLB + 0xbc))
1242 continue;
1243
1244 /* skip core clock, so that firmware can increase the clock */
1245 if (off == (ROMUSB_GLB + 0xc8))
1246 continue;
1247
1248 /* skip the function enable register */
1249 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1250 continue;
1251
1252 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1253 continue;
1254
1255 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1256 continue;
1257
1258 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1259 continue;
1260
1261 if (off == ADDR_ERROR) {
7c3df132
SK		 1262 ql_log(ql_log_fatal, vha, 0x0116,
1263 "Unknow addr: 0x%08lx.\n", buf[i].addr);
a9083016
GM		 1264 continue;
1265 }
1266
a9083016
GM		 1267 qla82xx_wr_32(ha, off, buf[i].data);
1268
1269 /* ISP requires much bigger delay to settle down,
1270 * else crb_window returns 0xffffffff
1271 */
1272 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1273 msleep(1000);
1274
1275 /* ISP requires millisec delay between
1276 * successive CRB register updation
1277 */
1278 msleep(1);
1279 }
1280
1281 kfree(buf);
1282
1283 /* Resetting the data and instruction cache */
1284 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1285 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1286 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1287
1288 /* Clear all protocol processing engines */
1289 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1290 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1291 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1292 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1293 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1294 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1295 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1296 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1297 return 0;
1298}
1299
77e334d2
GM		 1300static int
1301qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1302 u64 off, void *data, int size)
1303{
1304 int i, j, ret = 0, loop, sz[2], off0;
1305 int scale, shift_amount, startword;
1306 uint32_t temp;
1307 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1308
1309 /*
1310 * If not MN, go check for MS or invalid.
1311 */
1312 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1313 mem_crb = QLA82XX_CRB_QDR_NET;
1314 else {
1315 mem_crb = QLA82XX_CRB_DDR_NET;
1316 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1317 return qla82xx_pci_mem_write_direct(ha,
1318 off, data, size);
1319 }
1320
1321 off0 = off & 0x7;
1322 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1323 sz[1] = size - sz[0];
1324
1325 off8 = off & 0xfffffff0;
1326 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1327 shift_amount = 4;
1328 scale = 2;
1329 startword = (off & 0xf)/8;
1330
1331 for (i = 0; i < loop; i++) {
1332 if (qla82xx_pci_mem_read_2M(ha, off8 +
1333 (i << shift_amount), &word[i * scale], 8))
1334 return -1;
1335 }
1336
1337 switch (size) {
1338 case 1:
1339 tmpw = *((uint8_t *)data);
1340 break;
1341 case 2:
1342 tmpw = *((uint16_t *)data);
1343 break;
1344 case 4:
1345 tmpw = *((uint32_t *)data);
1346 break;
1347 case 8:
1348 default:
1349 tmpw = *((uint64_t *)data);
1350 break;
1351 }
1352
1353 if (sz[0] == 8) {
1354 word[startword] = tmpw;
1355 } else {
1356 word[startword] &=
1357 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1358 word[startword] |= tmpw << (off0 * 8);
1359 }
1360 if (sz[1] != 0) {
1361 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1362 word[startword+1] |= tmpw >> (sz[0] * 8);
1363 }
1364
77e334d2
GM		 1365 for (i = 0; i < loop; i++) {
1366 temp = off8 + (i << shift_amount);
1367 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1368 temp = 0;
1369 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1370 temp = word[i * scale] & 0xffffffff;
1371 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1372 temp = (word[i * scale] >> 32) & 0xffffffff;
1373 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1374 temp = word[i*scale + 1] & 0xffffffff;
1375 qla82xx_wr_32(ha, mem_crb +
1376 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1377 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1378 qla82xx_wr_32(ha, mem_crb +
1379 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1380
1381 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1382 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1383 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1384 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1385
1386 for (j = 0; j < MAX_CTL_CHECK; j++) {
1387 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1388 if ((temp & MIU_TA_CTL_BUSY) == 0)
1389 break;
1390 }
1391
1392 if (j >= MAX_CTL_CHECK) {
1393 if (printk_ratelimit())
1394 dev_err(&ha->pdev->dev,
7c3df132 1395 "failed to write through agent.\n");
77e334d2
GM		 1396 ret = -1;
1397 break;
1398 }
1399 }
1400
1401 return ret;
1402}
1403
1404static int
a9083016
GM		 1405qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1406{
1407 int i;
1408 long size = 0;
9c2b2975
HZ		 1409 long flashaddr = ha->flt_region_bootload << 2;
1410 long memaddr = BOOTLD_START;
a9083016
GM		 1411 u64 data;
1412 u32 high, low;
1413 size = (IMAGE_START - BOOTLD_START) / 8;
1414
1415 for (i = 0; i < size; i++) {
1416 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1417 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1418 return -1;
1419 }
1420 data = ((u64)high << 32) | low ;
1421 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1422 flashaddr += 8;
1423 memaddr += 8;
1424
1425 if (i % 0x1000 == 0)
1426 msleep(1);
1427 }
1428 udelay(100);
1429 read_lock(&ha->hw_lock);
3711333d
GM		 1430 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1431 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
a9083016
GM		 1432 read_unlock(&ha->hw_lock);
1433 return 0;
1434}
1435
1436int
1437qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1438 u64 off, void *data, int size)
1439{
1440 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1441 int shift_amount;
1442 uint32_t temp;
1443 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1444
1445 /*
1446 * If not MN, go check for MS or invalid.
1447 */
1448
1449 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1450 mem_crb = QLA82XX_CRB_QDR_NET;
1451 else {
1452 mem_crb = QLA82XX_CRB_DDR_NET;
1453 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1454 return qla82xx_pci_mem_read_direct(ha,
1455 off, data, size);
1456 }
1457
3711333d
GM		 1458 off8 = off & 0xfffffff0;
1459 off0[0] = off & 0xf;
1460 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1461 shift_amount = 4;
a9083016
GM		 1462 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1463 off0[1] = 0;
1464 sz[1] = size - sz[0];
1465
a9083016
GM		 1466 for (i = 0; i < loop; i++) {
1467 temp = off8 + (i << shift_amount);
1468 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1469 temp = 0;
1470 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1471 temp = MIU_TA_CTL_ENABLE;
1472 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1473 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1474 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1475
1476 for (j = 0; j < MAX_CTL_CHECK; j++) {
1477 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1478 if ((temp & MIU_TA_CTL_BUSY) == 0)
1479 break;
1480 }
1481
1482 if (j >= MAX_CTL_CHECK) {
1483 if (printk_ratelimit())
1484 dev_err(&ha->pdev->dev,
7c3df132 1485 "failed to read through agent.\n");
a9083016
GM		 1486 break;
1487 }
1488
1489 start = off0[i] >> 2;
1490 end = (off0[i] + sz[i] - 1) >> 2;
1491 for (k = start; k <= end; k++) {
1492 temp = qla82xx_rd_32(ha,
1493 mem_crb + MIU_TEST_AGT_RDDATA(k));
1494 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1495 }
1496 }
1497
a9083016
GM		 1498 if (j >= MAX_CTL_CHECK)
1499 return -1;
1500
1501 if ((off0[0] & 7) == 0) {
1502 val = word[0];
1503 } else {
1504 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1505 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1506 }
1507
1508 switch (size) {
1509 case 1:
1510 *(uint8_t *)data = val;
1511 break;
1512 case 2:
1513 *(uint16_t *)data = val;
1514 break;
1515 case 4:
1516 *(uint32_t *)data = val;
1517 break;
1518 case 8:
1519 *(uint64_t *)data = val;
1520 break;
1521 }
1522 return 0;
1523}
1524
a9083016 1525
9c2b2975
HZ		 1526static struct qla82xx_uri_table_desc *
1527qla82xx_get_table_desc(const u8 *unirom, int section)
1528{
1529 uint32_t i;
1530 struct qla82xx_uri_table_desc *directory =
1531 (struct qla82xx_uri_table_desc *)&unirom[0];
1532 __le32 offset;
1533 __le32 tab_type;
1534 __le32 entries = cpu_to_le32(directory->num_entries);
1535
1536 for (i = 0; i < entries; i++) {
1537 offset = cpu_to_le32(directory->findex) +
1538 (i * cpu_to_le32(directory->entry_size));
1539 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1540
1541 if (tab_type == section)
1542 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1543 }
1544
1545 return NULL;
1546}
1547
1548static struct qla82xx_uri_data_desc *
1549qla82xx_get_data_desc(struct qla_hw_data *ha,
1550 u32 section, u32 idx_offset)
1551{
1552 const u8 *unirom = ha->hablob->fw->data;
1553 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1554 struct qla82xx_uri_table_desc *tab_desc = NULL;
1555 __le32 offset;
1556
1557 tab_desc = qla82xx_get_table_desc(unirom, section);
1558 if (!tab_desc)
1559 return NULL;
1560
1561 offset = cpu_to_le32(tab_desc->findex) +
1562 (cpu_to_le32(tab_desc->entry_size) * idx);
1563
1564 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1565}
1566
1567static u8 *
1568qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1569{
1570 u32 offset = BOOTLD_START;
1571 struct qla82xx_uri_data_desc *uri_desc = NULL;
1572
1573 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1574 uri_desc = qla82xx_get_data_desc(ha,
1575 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1576 if (uri_desc)
1577 offset = cpu_to_le32(uri_desc->findex);
1578 }
1579
1580 return (u8 *)&ha->hablob->fw->data[offset];
1581}
1582
1583static __le32
1584qla82xx_get_fw_size(struct qla_hw_data *ha)
1585{
1586 struct qla82xx_uri_data_desc *uri_desc = NULL;
1587
1588 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1589 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1590 QLA82XX_URI_FIRMWARE_IDX_OFF);
1591 if (uri_desc)
1592 return cpu_to_le32(uri_desc->size);
1593 }
1594
1595 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1596}
1597
1598static u8 *
1599qla82xx_get_fw_offs(struct qla_hw_data *ha)
1600{
1601 u32 offset = IMAGE_START;
1602 struct qla82xx_uri_data_desc *uri_desc = NULL;
1603
1604 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1605 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1606 QLA82XX_URI_FIRMWARE_IDX_OFF);
1607 if (uri_desc)
1608 offset = cpu_to_le32(uri_desc->findex);
1609 }
1610
1611 return (u8 *)&ha->hablob->fw->data[offset];
1612}
1613
a9083016 1614/* PCI related functions */
a9083016
GM		 1615int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1616{
1617 unsigned long val = 0;
1618 u32 control;
1619
1620 switch (region) {
1621 case 0:
1622 val = 0;
1623 break;
1624 case 1:
1625 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1626 val = control + QLA82XX_MSIX_TBL_SPACE;
1627 break;
1628 }
1629 return val;
1630}
1631
a9083016
GM		 1632
1633int
1634qla82xx_iospace_config(struct qla_hw_data *ha)
1635{
1636 uint32_t len = 0;
1637
1638 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1639 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1640 "Failed to reserver selected regions.\n");
a9083016
GM		 1641 goto iospace_error_exit;
1642 }
1643
1644 /* Use MMIO operations for all accesses. */
1645 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
7c3df132
SK		 1646 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1647 "Region #0 not an MMIO resource, aborting.\n");
a9083016
GM		 1648 goto iospace_error_exit;
1649 }
1650
1651 len = pci_resource_len(ha->pdev, 0);
1652 ha->nx_pcibase =
1653 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1654 if (!ha->nx_pcibase) {
7c3df132
SK		 1655 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1656 "Cannot remap pcibase MMIO, aborting.\n");
a9083016
GM		 1657 pci_release_regions(ha->pdev);
1658 goto iospace_error_exit;
1659 }
1660
1661 /* Mapping of IO base pointer */
1662 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1663 0xbc000 + (ha->pdev->devfn << 11));
1664
1665 if (!ql2xdbwr) {
1666 ha->nxdb_wr_ptr =
1667 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1668 (ha->pdev->devfn << 12)), 4);
1669 if (!ha->nxdb_wr_ptr) {
7c3df132
SK		 1670 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1671 "Cannot remap MMIO, aborting.\n");
a9083016
GM		 1672 pci_release_regions(ha->pdev);
1673 goto iospace_error_exit;
1674 }
1675
1676 /* Mapping of IO base pointer,
1677 * door bell read and write pointer
1678 */
1679 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1680 (ha->pdev->devfn * 8);
1681 } else {
1682 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1683 QLA82XX_CAMRAM_DB1 :
1684 QLA82XX_CAMRAM_DB2);
1685 }
1686
1687 ha->max_req_queues = ha->max_rsp_queues = 1;
1688 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1689 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1690 "nx_pci_base=%p iobase=%p "
1691 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1692 (void *)ha->nx_pcibase, ha->iobase,
7c3df132
SK		 1693 ha->max_req_queues, ha->msix_count);
1694 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1695 "nx_pci_base=%p iobase=%p "
1696 "max_req_queues=%d msix_count=%d.\n",
d8424f68 1697 (void *)ha->nx_pcibase, ha->iobase,
7c3df132 1698 ha->max_req_queues, ha->msix_count);
a9083016
GM		 1699 return 0;
1700
1701iospace_error_exit:
1702 return -ENOMEM;
1703}
1704
1705/* GS related functions */
1706
1707/* Initialization related functions */
1708
1709/**
1710 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1711 * @ha: HA context
1712 *
1713 * Returns 0 on success.
1714*/
1715int
1716qla82xx_pci_config(scsi_qla_host_t *vha)
1717{
1718 struct qla_hw_data *ha = vha->hw;
1719 int ret;
1720
1721 pci_set_master(ha->pdev);
1722 ret = pci_set_mwi(ha->pdev);
1723 ha->chip_revision = ha->pdev->revision;
7c3df132 1724 ql_dbg(ql_dbg_init, vha, 0x0043,
d8424f68 1725 "Chip revision:%d.\n",
7c3df132 1726 ha->chip_revision);
a9083016
GM		 1727 return 0;
1728}
1729
1730/**
1731 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1732 * @ha: HA context
1733 *
1734 * Returns 0 on success.
1735 */
1736void
1737qla82xx_reset_chip(scsi_qla_host_t *vha)
1738{
1739 struct qla_hw_data *ha = vha->hw;
1740 ha->isp_ops->disable_intrs(ha);
1741}
1742
1743void qla82xx_config_rings(struct scsi_qla_host *vha)
1744{
1745 struct qla_hw_data *ha = vha->hw;
1746 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1747 struct init_cb_81xx *icb;
1748 struct req_que *req = ha->req_q_map[0];
1749 struct rsp_que *rsp = ha->rsp_q_map[0];
1750
1751 /* Setup ring parameters in initialization control block. */
1752 icb = (struct init_cb_81xx *)ha->init_cb;
1753 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1754 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1755 icb->request_q_length = cpu_to_le16(req->length);
1756 icb->response_q_length = cpu_to_le16(rsp->length);
1757 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1758 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1759 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1760 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1761
a9083016
GM		 1762 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0);
1763 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0);
1764 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1765}
1766
f1af6208
GM		 1767void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1768{
1769 struct qla_hw_data *ha = vha->hw;
1770 vha->flags.online = 0;
1771 qla2x00_try_to_stop_firmware(vha);
1772 ha->isp_ops->disable_intrs(ha);
1773}
1774
77e334d2
GM		 1775static int
1776qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
a9083016
GM		 1777{
1778 u64 *ptr64;
1779 u32 i, flashaddr, size;
1780 __le64 data;
1781
1782 size = (IMAGE_START - BOOTLD_START) / 8;
1783
9c2b2975 1784 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
a9083016
GM		 1785 flashaddr = BOOTLD_START;
1786
1787 for (i = 0; i < size; i++) {
1788 data = cpu_to_le64(ptr64[i]);
9c2b2975
HZ		 1789 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1790 return -EIO;
a9083016
GM		 1791 flashaddr += 8;
1792 }
1793
a9083016 1794 flashaddr = FLASH_ADDR_START;
9c2b2975
HZ		 1795 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1796 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
a9083016
GM		 1797
1798 for (i = 0; i < size; i++) {
1799 data = cpu_to_le64(ptr64[i]);
1800
1801 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1802 return -EIO;
1803 flashaddr += 8;
1804 }
9c2b2975 1805 udelay(100);
a9083016
GM		 1806
1807 /* Write a magic value to CAMRAM register
1808 * at a specified offset to indicate
1809 * that all data is written and
1810 * ready for firmware to initialize.
1811 */
9c2b2975 1812 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
a9083016 1813
9c2b2975 1814 read_lock(&ha->hw_lock);
3711333d
GM		 1815 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1816 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
9c2b2975
HZ		 1817 read_unlock(&ha->hw_lock);
1818 return 0;
1819}
1820
1821static int
1822qla82xx_set_product_offset(struct qla_hw_data *ha)
1823{
1824 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1825 const uint8_t *unirom = ha->hablob->fw->data;
1826 uint32_t i;
1827 __le32 entries;
1828 __le32 flags, file_chiprev, offset;
1829 uint8_t chiprev = ha->chip_revision;
1830 /* Hardcoding mn_present flag for P3P */
1831 int mn_present = 0;
1832 uint32_t flagbit;
1833
1834 ptab_desc = qla82xx_get_table_desc(unirom,
1835 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1836 if (!ptab_desc)
1837 return -1;
1838
1839 entries = cpu_to_le32(ptab_desc->num_entries);
1840
1841 for (i = 0; i < entries; i++) {
1842 offset = cpu_to_le32(ptab_desc->findex) +
1843 (i * cpu_to_le32(ptab_desc->entry_size));
1844 flags = cpu_to_le32(*((int *)&unirom[offset] +
1845 QLA82XX_URI_FLAGS_OFF));
1846 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1847 QLA82XX_URI_CHIP_REV_OFF));
1848
1849 flagbit = mn_present ? 1 : 2;
1850
1851 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1852 ha->file_prd_off = offset;
1853 return 0;
1854 }
1855 }
1856 return -1;
1857}
1858
1859int
1860qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1861{
1862 __le32 val;
1863 uint32_t min_size;
1864 struct qla_hw_data *ha = vha->hw;
1865 const struct firmware *fw = ha->hablob->fw;
1866
1867 ha->fw_type = fw_type;
1868
1869 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1870 if (qla82xx_set_product_offset(ha))
1871 return -EINVAL;
1872
1873 min_size = QLA82XX_URI_FW_MIN_SIZE;
1874 } else {
1875 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1876 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1877 return -EINVAL;
1878
1879 min_size = QLA82XX_FW_MIN_SIZE;
1880 }
1881
1882 if (fw->size < min_size)
1883 return -EINVAL;
a9083016
GM		 1884 return 0;
1885}
1886
77e334d2
GM		 1887static int
1888qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1889{
1890 u32 val = 0;
1891 int retries = 60;
7c3df132 1892 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1893
1894 do {
1895 read_lock(&ha->hw_lock);
1896 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1897 read_unlock(&ha->hw_lock);
1898
1899 switch (val) {
1900 case PHAN_INITIALIZE_COMPLETE:
1901 case PHAN_INITIALIZE_ACK:
1902 return QLA_SUCCESS;
1903 case PHAN_INITIALIZE_FAILED:
1904 break;
1905 default:
1906 break;
1907 }
7c3df132
SK		 1908 ql_log(ql_log_info, vha, 0x00a8,
1909 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1910 val, retries);
a9083016
GM		 1911
1912 msleep(500);
1913
1914 } while (--retries);
1915
7c3df132 1916 ql_log(ql_log_fatal, vha, 0x00a9,
a9083016
GM		 1917 "Cmd Peg initialization failed: 0x%x.\n", val);
1918
a9083016
GM		 1919 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1920 read_lock(&ha->hw_lock);
1921 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1922 read_unlock(&ha->hw_lock);
1923 return QLA_FUNCTION_FAILED;
1924}
1925
77e334d2
GM		 1926static int
1927qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
a9083016
GM		 1928{
1929 u32 val = 0;
1930 int retries = 60;
7c3df132 1931 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 1932
1933 do {
1934 read_lock(&ha->hw_lock);
1935 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1936 read_unlock(&ha->hw_lock);
1937
1938 switch (val) {
1939 case PHAN_INITIALIZE_COMPLETE:
1940 case PHAN_INITIALIZE_ACK:
1941 return QLA_SUCCESS;
1942 case PHAN_INITIALIZE_FAILED:
1943 break;
1944 default:
1945 break;
1946 }
7c3df132
SK		 1947 ql_log(ql_log_info, vha, 0x00ab,
1948 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1949 val, retries);
a9083016
GM		 1950
1951 msleep(500);
1952
1953 } while (--retries);
1954
7c3df132
SK		 1955 ql_log(ql_log_fatal, vha, 0x00ac,
1956 "Rcv Peg initializatin failed: 0x%x.\n", val);
a9083016
GM		 1957 read_lock(&ha->hw_lock);
1958 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1959 read_unlock(&ha->hw_lock);
1960 return QLA_FUNCTION_FAILED;
1961}
1962
1963/* ISR related functions */
1964uint32_t qla82xx_isr_int_target_mask_enable[8] = {
1965 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
1966 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
1967 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
1968 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
1969};
1970
1971uint32_t qla82xx_isr_int_target_status[8] = {
1972 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
1973 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
1974 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
1975 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
1976};
1977
1978static struct qla82xx_legacy_intr_set legacy_intr[] = \
1979 QLA82XX_LEGACY_INTR_CONFIG;
1980
1981/*
1982 * qla82xx_mbx_completion() - Process mailbox command completions.
1983 * @ha: SCSI driver HA context
1984 * @mb0: Mailbox0 register
1985 */
77e334d2 1986static void
a9083016
GM		 1987qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1988{
1989 uint16_t cnt;
1990 uint16_t __iomem *wptr;
1991 struct qla_hw_data *ha = vha->hw;
1992 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1993 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1994
1995 /* Load return mailbox registers. */
1996 ha->flags.mbox_int = 1;
1997 ha->mailbox_out[0] = mb0;
1998
1999 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2000 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2001 wptr++;
2002 }
2003
cfb0919c 2004 if (!ha->mcp)
7c3df132
SK		 2005 ql_dbg(ql_dbg_async, vha, 0x5053,
2006 "MBX pointer ERROR.\n");
a9083016
GM		 2007}
2008
2009/*
2010 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2011 * @irq:
2012 * @dev_id: SCSI driver HA context
2013 * @regs:
2014 *
2015 * Called by system whenever the host adapter generates an interrupt.
2016 *
2017 * Returns handled flag.
2018 */
2019irqreturn_t
2020qla82xx_intr_handler(int irq, void *dev_id)
2021{
2022 scsi_qla_host_t *vha;
2023 struct qla_hw_data *ha;
2024 struct rsp_que *rsp;
2025 struct device_reg_82xx __iomem *reg;
2026 int status = 0, status1 = 0;
2027 unsigned long flags;
2028 unsigned long iter;
7c3df132 2029 uint32_t stat = 0;
a9083016
GM		 2030 uint16_t mb[4];
2031
2032 rsp = (struct rsp_que *) dev_id;
2033 if (!rsp) {
b6d0d9d5 2034 ql_log(ql_log_info, NULL, 0xb053,
3256b435 2035 "%s: NULL response queue pointer.\n", __func__);
a9083016
GM		 2036 return IRQ_NONE;
2037 }
2038 ha = rsp->hw;
2039
2040 if (!ha->flags.msi_enabled) {
2041 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2042 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2043 return IRQ_NONE;
2044
2045 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2046 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2047 return IRQ_NONE;
2048 }
2049
2050 /* clear the interrupt */
2051 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2052
2053 /* read twice to ensure write is flushed */
2054 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2055 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2056
2057 reg = &ha->iobase->isp82;
2058
2059 spin_lock_irqsave(&ha->hardware_lock, flags);
2060 vha = pci_get_drvdata(ha->pdev);
2061 for (iter = 1; iter--; ) {
2062
2063 if (RD_REG_DWORD(&reg->host_int)) {
2064 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2065
2066 switch (stat & 0xff) {
2067 case 0x1:
2068 case 0x2:
2069 case 0x10:
2070 case 0x11:
2071 qla82xx_mbx_completion(vha, MSW(stat));
2072 status |= MBX_INTERRUPT;
2073 break;
2074 case 0x12:
2075 mb[0] = MSW(stat);
2076 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2077 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2078 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2079 qla2x00_async_event(vha, rsp, mb);
2080 break;
2081 case 0x13:
2082 qla24xx_process_response_queue(vha, rsp);
2083 break;
2084 default:
7c3df132
SK		 2085 ql_dbg(ql_dbg_async, vha, 0x5054,
2086 "Unrecognized interrupt type (%d).\n",
2087 stat & 0xff);
a9083016
GM		 2088 break;
2089 }
2090 }
2091 WRT_REG_DWORD(&reg->host_int, 0);
2092 }
2093 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2094 if (!ha->flags.msi_enabled)
2095 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2096
2097#ifdef QL_DEBUG_LEVEL_17
2098 if (!irq && ha->flags.eeh_busy)
7c3df132
SK		 2099 ql_log(ql_log_warn, vha, 0x503d,
2100 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
a9083016
GM		 2101 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2102#endif
2103
2104 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2105 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2106 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2107 complete(&ha->mbx_intr_comp);
2108 }
2109 return IRQ_HANDLED;
2110}
2111
2112irqreturn_t
2113qla82xx_msix_default(int irq, void *dev_id)
2114{
2115 scsi_qla_host_t *vha;
2116 struct qla_hw_data *ha;
2117 struct rsp_que *rsp;
2118 struct device_reg_82xx __iomem *reg;
2119 int status = 0;
2120 unsigned long flags;
7c3df132 2121 uint32_t stat = 0;
a9083016
GM		 2122 uint16_t mb[4];
2123
2124 rsp = (struct rsp_que *) dev_id;
2125 if (!rsp) {
2126 printk(KERN_INFO
7c3df132 2127 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2128 return IRQ_NONE;
2129 }
2130 ha = rsp->hw;
2131
2132 reg = &ha->iobase->isp82;
2133
2134 spin_lock_irqsave(&ha->hardware_lock, flags);
2135 vha = pci_get_drvdata(ha->pdev);
2136 do {
2137 if (RD_REG_DWORD(&reg->host_int)) {
2138 stat = RD_REG_DWORD(&reg->host_status);
a9083016
GM		 2139
2140 switch (stat & 0xff) {
2141 case 0x1:
2142 case 0x2:
2143 case 0x10:
2144 case 0x11:
2145 qla82xx_mbx_completion(vha, MSW(stat));
2146 status |= MBX_INTERRUPT;
2147 break;
2148 case 0x12:
2149 mb[0] = MSW(stat);
2150 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2151 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2152 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2153 qla2x00_async_event(vha, rsp, mb);
2154 break;
2155 case 0x13:
2156 qla24xx_process_response_queue(vha, rsp);
2157 break;
2158 default:
7c3df132
SK		 2159 ql_dbg(ql_dbg_async, vha, 0x5041,
2160 "Unrecognized interrupt type (%d).\n",
2161 stat & 0xff);
a9083016
GM		 2162 break;
2163 }
2164 }
2165 WRT_REG_DWORD(&reg->host_int, 0);
2166 } while (0);
2167
2168 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2169
2170#ifdef QL_DEBUG_LEVEL_17
2171 if (!irq && ha->flags.eeh_busy)
7c3df132
SK		 2172 ql_log(ql_log_warn, vha, 0x5044,
2173 "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2174 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
a9083016
GM		 2175#endif
2176
2177 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2178 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2179 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2180 complete(&ha->mbx_intr_comp);
2181 }
2182 return IRQ_HANDLED;
2183}
2184
2185irqreturn_t
2186qla82xx_msix_rsp_q(int irq, void *dev_id)
2187{
2188 scsi_qla_host_t *vha;
2189 struct qla_hw_data *ha;
2190 struct rsp_que *rsp;
2191 struct device_reg_82xx __iomem *reg;
3553d343 2192 unsigned long flags;
a9083016
GM		 2193
2194 rsp = (struct rsp_que *) dev_id;
2195 if (!rsp) {
2196 printk(KERN_INFO
7c3df132 2197 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2198 return IRQ_NONE;
2199 }
2200
2201 ha = rsp->hw;
2202 reg = &ha->iobase->isp82;
3553d343 2203 spin_lock_irqsave(&ha->hardware_lock, flags);
a9083016
GM		 2204 vha = pci_get_drvdata(ha->pdev);
2205 qla24xx_process_response_queue(vha, rsp);
2206 WRT_REG_DWORD(&reg->host_int, 0);
3553d343 2207 spin_unlock_irqrestore(&ha->hardware_lock, flags);
a9083016
GM		 2208 return IRQ_HANDLED;
2209}
2210
2211void
2212qla82xx_poll(int irq, void *dev_id)
2213{
2214 scsi_qla_host_t *vha;
2215 struct qla_hw_data *ha;
2216 struct rsp_que *rsp;
2217 struct device_reg_82xx __iomem *reg;
2218 int status = 0;
2219 uint32_t stat;
2220 uint16_t mb[4];
2221 unsigned long flags;
2222
2223 rsp = (struct rsp_que *) dev_id;
2224 if (!rsp) {
2225 printk(KERN_INFO
7c3df132 2226 "%s(): NULL response queue pointer.\n", __func__);
a9083016
GM		 2227 return;
2228 }
2229 ha = rsp->hw;
2230
2231 reg = &ha->iobase->isp82;
2232 spin_lock_irqsave(&ha->hardware_lock, flags);
2233 vha = pci_get_drvdata(ha->pdev);
2234
2235 if (RD_REG_DWORD(&reg->host_int)) {
2236 stat = RD_REG_DWORD(&reg->host_status);
2237 switch (stat & 0xff) {
2238 case 0x1:
2239 case 0x2:
2240 case 0x10:
2241 case 0x11:
2242 qla82xx_mbx_completion(vha, MSW(stat));
2243 status |= MBX_INTERRUPT;
2244 break;
2245 case 0x12:
2246 mb[0] = MSW(stat);
2247 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2248 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2249 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2250 qla2x00_async_event(vha, rsp, mb);
2251 break;
2252 case 0x13:
2253 qla24xx_process_response_queue(vha, rsp);
2254 break;
2255 default:
7c3df132
SK		 2256 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2257 "Unrecognized interrupt type (%d).\n",
2258 stat * 0xff);
a9083016
GM		 2259 break;
2260 }
2261 }
2262 WRT_REG_DWORD(&reg->host_int, 0);
2263 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2264}
2265
2266void
2267qla82xx_enable_intrs(struct qla_hw_data *ha)
2268{
2269 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2270 qla82xx_mbx_intr_enable(vha);
2271 spin_lock_irq(&ha->hardware_lock);
2272 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2273 spin_unlock_irq(&ha->hardware_lock);
2274 ha->interrupts_on = 1;
2275}
2276
2277void
2278qla82xx_disable_intrs(struct qla_hw_data *ha)
2279{
2280 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2281 qla82xx_mbx_intr_disable(vha);
2282 spin_lock_irq(&ha->hardware_lock);
2283 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2284 spin_unlock_irq(&ha->hardware_lock);
2285 ha->interrupts_on = 0;
2286}
2287
2288void qla82xx_init_flags(struct qla_hw_data *ha)
2289{
2290 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2291
2292 /* ISP 8021 initializations */
2293 rwlock_init(&ha->hw_lock);
2294 ha->qdr_sn_window = -1;
2295 ha->ddr_mn_window = -1;
2296 ha->curr_window = 255;
2297 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2298 nx_legacy_intr = &legacy_intr[ha->portnum];
2299 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2300 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2301 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2302 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2303}
2304
a5b36321 2305inline void
a9083016
GM		 2306qla82xx_set_drv_active(scsi_qla_host_t *vha)
2307{
2308 uint32_t drv_active;
2309 struct qla_hw_data *ha = vha->hw;
2310
2311 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2312
2313 /* If reset value is all FF's, initialize DRV_ACTIVE */
2314 if (drv_active == 0xffffffff) {
77e334d2
GM		 2315 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2316 QLA82XX_DRV_NOT_ACTIVE);
a9083016
GM		 2317 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2318 }
77e334d2 2319 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2320 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2321}
2322
2323inline void
2324qla82xx_clear_drv_active(struct qla_hw_data *ha)
2325{
2326 uint32_t drv_active;
2327
2328 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
77e334d2 2329 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
a9083016
GM		 2330 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2331}
2332
2333static inline int
2334qla82xx_need_reset(struct qla_hw_data *ha)
2335{
2336 uint32_t drv_state;
2337 int rval;
2338
7d613ac6 2339 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 2340 return 1;
2341 else {
2342 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2343 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2344 return rval;
2345 }
a9083016
GM		 2346}
2347
2348static inline void
2349qla82xx_set_rst_ready(struct qla_hw_data *ha)
2350{
2351 uint32_t drv_state;
2352 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2353
2354 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2355
2356 /* If reset value is all FF's, initialize DRV_STATE */
2357 if (drv_state == 0xffffffff) {
77e334d2 2358 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
a9083016
GM		 2359 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2360 }
2361 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
08de2844
GM		 2362 ql_dbg(ql_dbg_init, vha, 0x00bb,
2363 "drv_state = 0x%08x.\n", drv_state);
a9083016
GM		 2364 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2365}
2366
2367static inline void
2368qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2369{
2370 uint32_t drv_state;
2371
2372 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2373 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2374 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2375}
2376
2377static inline void
2378qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2379{
2380 uint32_t qsnt_state;
2381
2382 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2383 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2384 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2385}
2386
579d12b5
SK		 2387void
2388qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2389{
2390 struct qla_hw_data *ha = vha->hw;
2391 uint32_t qsnt_state;
2392
2393 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2394 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2395 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2396}
2397
77e334d2
GM		 2398static int
2399qla82xx_load_fw(scsi_qla_host_t *vha)
a9083016
GM		 2400{
2401 int rst;
2402 struct fw_blob *blob;
2403 struct qla_hw_data *ha = vha->hw;
2404
a9083016 2405 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
7c3df132
SK		 2406 ql_log(ql_log_fatal, vha, 0x009f,
2407 "Error during CRB initialization.\n");
a9083016
GM		 2408 return QLA_FUNCTION_FAILED;
2409 }
2410 udelay(500);
2411
2412 /* Bring QM and CAMRAM out of reset */
2413 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2414 rst &= ~((1 << 28) | (1 << 24));
2415 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2416
2417 /*
2418 * FW Load priority:
2419 * 1) Operational firmware residing in flash.
2420 * 2) Firmware via request-firmware interface (.bin file).
2421 */
2422 if (ql2xfwloadbin == 2)
2423 goto try_blob_fw;
2424
7c3df132
SK		 2425 ql_log(ql_log_info, vha, 0x00a0,
2426 "Attempting to load firmware from flash.\n");
a9083016
GM		 2427
2428 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
7c3df132 2429 ql_log(ql_log_info, vha, 0x00a1,
00adc9a0 2430 "Firmware loaded successfully from flash.\n");
a9083016 2431 return QLA_SUCCESS;
875efad7 2432 } else {
7c3df132
SK		 2433 ql_log(ql_log_warn, vha, 0x0108,
2434 "Firmware load from flash failed.\n");
a9083016 2435 }
875efad7 2436
a9083016 2437try_blob_fw:
7c3df132
SK		 2438 ql_log(ql_log_info, vha, 0x00a2,
2439 "Attempting to load firmware from blob.\n");
a9083016
GM		 2440
2441 /* Load firmware blob. */
2442 blob = ha->hablob = qla2x00_request_firmware(vha);
2443 if (!blob) {
7c3df132 2444 ql_log(ql_log_fatal, vha, 0x00a3,
00adc9a0 2445 "Firmware image not present.\n");
a9083016
GM		 2446 goto fw_load_failed;
2447 }
2448
9c2b2975
HZ		 2449 /* Validating firmware blob */
2450 if (qla82xx_validate_firmware_blob(vha,
2451 QLA82XX_FLASH_ROMIMAGE)) {
2452 /* Fallback to URI format */
2453 if (qla82xx_validate_firmware_blob(vha,
2454 QLA82XX_UNIFIED_ROMIMAGE)) {
7c3df132
SK		 2455 ql_log(ql_log_fatal, vha, 0x00a4,
2456 "No valid firmware image found.\n");
9c2b2975
HZ		 2457 return QLA_FUNCTION_FAILED;
2458 }
2459 }
2460
a9083016 2461 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
7c3df132
SK		 2462 ql_log(ql_log_info, vha, 0x00a5,
2463 "Firmware loaded successfully from binary blob.\n");
a9083016
GM		 2464 return QLA_SUCCESS;
2465 } else {
7c3df132
SK		 2466 ql_log(ql_log_fatal, vha, 0x00a6,
2467 "Firmware load failed for binary blob.\n");
a9083016
GM		 2468 blob->fw = NULL;
2469 blob = NULL;
2470 goto fw_load_failed;
2471 }
2472 return QLA_SUCCESS;
2473
2474fw_load_failed:
2475 return QLA_FUNCTION_FAILED;
2476}
2477
a5b36321 2478int
a9083016
GM		 2479qla82xx_start_firmware(scsi_qla_host_t *vha)
2480{
2481 int pcie_cap;
2482 uint16_t lnk;
2483 struct qla_hw_data *ha = vha->hw;
2484
2485 /* scrub dma mask expansion register */
77e334d2 2486 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
a9083016 2487
3711333d
GM		 2488 /* Put both the PEG CMD and RCV PEG to default state
2489 * of 0 before resetting the hardware
2490 */
2491 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2492 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2493
a9083016
GM		 2494 /* Overwrite stale initialization register values */
2495 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2496 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2497
2498 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
7c3df132
SK		 2499 ql_log(ql_log_fatal, vha, 0x00a7,
2500 "Error trying to start fw.\n");
a9083016
GM		 2501 return QLA_FUNCTION_FAILED;
2502 }
2503
2504 /* Handshake with the card before we register the devices. */
2505 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
7c3df132
SK		 2506 ql_log(ql_log_fatal, vha, 0x00aa,
2507 "Error during card handshake.\n");
a9083016
GM		 2508 return QLA_FUNCTION_FAILED;
2509 }
2510
2511 /* Negotiated Link width */
e67f1321 2512 pcie_cap = pci_pcie_cap(ha->pdev);
a9083016
GM		 2513 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
2514 ha->link_width = (lnk >> 4) & 0x3f;
2515
2516 /* Synchronize with Receive peg */
2517 return qla82xx_check_rcvpeg_state(ha);
2518}
2519
77e334d2 2520static uint32_t *
a9083016
GM		 2521qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2522 uint32_t length)
2523{
2524 uint32_t i;
2525 uint32_t val;
2526 struct qla_hw_data *ha = vha->hw;
2527
2528 /* Dword reads to flash. */
2529 for (i = 0; i < length/4; i++, faddr += 4) {
2530 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
7c3df132
SK		 2531 ql_log(ql_log_warn, vha, 0x0106,
2532 "Do ROM fast read failed.\n");
a9083016
GM		 2533 goto done_read;
2534 }
2535 dwptr[i] = __constant_cpu_to_le32(val);
2536 }
2537done_read:
2538 return dwptr;
2539}
2540
77e334d2 2541static int
a9083016
GM		 2542qla82xx_unprotect_flash(struct qla_hw_data *ha)
2543{
2544 int ret;
2545 uint32_t val;
7c3df132 2546 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2547
2548 ret = ql82xx_rom_lock_d(ha);
2549 if (ret < 0) {
7c3df132
SK		 2550 ql_log(ql_log_warn, vha, 0xb014,
2551 "ROM Lock failed.\n");
a9083016
GM		 2552 return ret;
2553 }
2554
2555 ret = qla82xx_read_status_reg(ha, &val);
2556 if (ret < 0)
2557 goto done_unprotect;
2558
0547fb37 2559 val &= ~(BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2560 ret = qla82xx_write_status_reg(ha, val);
2561 if (ret < 0) {
0547fb37 2562 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2563 qla82xx_write_status_reg(ha, val);
2564 }
2565
2566 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2567 ql_log(ql_log_warn, vha, 0xb015,
2568 "Write disable failed.\n");
a9083016
GM		 2569
2570done_unprotect:
d652e093 2571 qla82xx_rom_unlock(ha);
a9083016
GM		 2572 return ret;
2573}
2574
77e334d2 2575static int
a9083016
GM		 2576qla82xx_protect_flash(struct qla_hw_data *ha)
2577{
2578 int ret;
2579 uint32_t val;
7c3df132 2580 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2581
2582 ret = ql82xx_rom_lock_d(ha);
2583 if (ret < 0) {
7c3df132
SK		 2584 ql_log(ql_log_warn, vha, 0xb016,
2585 "ROM Lock failed.\n");
a9083016
GM		 2586 return ret;
2587 }
2588
2589 ret = qla82xx_read_status_reg(ha, &val);
2590 if (ret < 0)
2591 goto done_protect;
2592
0547fb37 2593 val |= (BLOCK_PROTECT_BITS << 2);
a9083016
GM		 2594 /* LOCK all sectors */
2595 ret = qla82xx_write_status_reg(ha, val);
2596 if (ret < 0)
7c3df132
SK		 2597 ql_log(ql_log_warn, vha, 0xb017,
2598 "Write status register failed.\n");
a9083016
GM		 2599
2600 if (qla82xx_write_disable_flash(ha) != 0)
7c3df132
SK		 2601 ql_log(ql_log_warn, vha, 0xb018,
2602 "Write disable failed.\n");
a9083016 2603done_protect:
d652e093 2604 qla82xx_rom_unlock(ha);
a9083016
GM		 2605 return ret;
2606}
2607
77e334d2 2608static int
a9083016
GM		 2609qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2610{
2611 int ret = 0;
7c3df132 2612 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
a9083016
GM		 2613
2614 ret = ql82xx_rom_lock_d(ha);
2615 if (ret < 0) {
7c3df132
SK		 2616 ql_log(ql_log_warn, vha, 0xb019,
2617 "ROM Lock failed.\n");
a9083016
GM		 2618 return ret;
2619 }
2620
2621 qla82xx_flash_set_write_enable(ha);
2622 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2623 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2624 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2625
2626 if (qla82xx_wait_rom_done(ha)) {
7c3df132
SK		 2627 ql_log(ql_log_warn, vha, 0xb01a,
2628 "Error waiting for rom done.\n");
a9083016
GM		 2629 ret = -1;
2630 goto done;
2631 }
2632 ret = qla82xx_flash_wait_write_finish(ha);
2633done:
d652e093 2634 qla82xx_rom_unlock(ha);
a9083016
GM		 2635 return ret;
2636}
2637
2638/*
2639 * Address and length are byte address
2640 */
2641uint8_t *
2642qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2643 uint32_t offset, uint32_t length)
2644{
2645 scsi_block_requests(vha->host);
2646 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2647 scsi_unblock_requests(vha->host);
2648 return buf;
2649}
2650
2651static int
2652qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2653 uint32_t faddr, uint32_t dwords)
2654{
2655 int ret;
2656 uint32_t liter;
2657 uint32_t sec_mask, rest_addr;
2658 dma_addr_t optrom_dma;
2659 void *optrom = NULL;
2660 int page_mode = 0;
2661 struct qla_hw_data *ha = vha->hw;
2662
2663 ret = -1;
2664
2665 /* Prepare burst-capable write on supported ISPs. */
2666 if (page_mode && !(faddr & 0xfff) &&
2667 dwords > OPTROM_BURST_DWORDS) {
2668 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2669 &optrom_dma, GFP_KERNEL);
2670 if (!optrom) {
7c3df132
SK		 2671 ql_log(ql_log_warn, vha, 0xb01b,
2672 "Unable to allocate memory "
00adc9a0 2673 "for optrom burst write (%x KB).\n",
7c3df132 2674 OPTROM_BURST_SIZE / 1024);
a9083016
GM		 2675 }
2676 }
2677
2678 rest_addr = ha->fdt_block_size - 1;
2679 sec_mask = ~rest_addr;
2680
2681 ret = qla82xx_unprotect_flash(ha);
2682 if (ret) {
7c3df132
SK		 2683 ql_log(ql_log_warn, vha, 0xb01c,
2684 "Unable to unprotect flash for update.\n");
a9083016
GM		 2685 goto write_done;
2686 }
2687
2688 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2689 /* Are we at the beginning of a sector? */
2690 if ((faddr & rest_addr) == 0) {
2691
2692 ret = qla82xx_erase_sector(ha, faddr);
2693 if (ret) {
7c3df132
SK		 2694 ql_log(ql_log_warn, vha, 0xb01d,
2695 "Unable to erase sector: address=%x.\n",
2696 faddr);
a9083016
GM		 2697 break;
2698 }
2699 }
2700
2701 /* Go with burst-write. */
2702 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2703 /* Copy data to DMA'ble buffer. */
2704 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2705
2706 ret = qla2x00_load_ram(vha, optrom_dma,
2707 (ha->flash_data_off | faddr),
2708 OPTROM_BURST_DWORDS);
2709 if (ret != QLA_SUCCESS) {
7c3df132 2710 ql_log(ql_log_warn, vha, 0xb01e,
a9083016
GM		 2711 "Unable to burst-write optrom segment "
2712 "(%x/%x/%llx).\n", ret,
2713 (ha->flash_data_off | faddr),
2714 (unsigned long long)optrom_dma);
7c3df132 2715 ql_log(ql_log_warn, vha, 0xb01f,
a9083016
GM		 2716 "Reverting to slow-write.\n");
2717
2718 dma_free_coherent(&ha->pdev->dev,
2719 OPTROM_BURST_SIZE, optrom, optrom_dma);
2720 optrom = NULL;
2721 } else {
2722 liter += OPTROM_BURST_DWORDS - 1;
2723 faddr += OPTROM_BURST_DWORDS - 1;
2724 dwptr += OPTROM_BURST_DWORDS - 1;
2725 continue;
2726 }
2727 }
2728
2729 ret = qla82xx_write_flash_dword(ha, faddr,
2730 cpu_to_le32(*dwptr));
2731 if (ret) {
7c3df132
SK		 2732 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2733 "Unable to program flash address=%x data=%x.\n",
2734 faddr, *dwptr);
a9083016
GM		 2735 break;
2736 }
2737 }
2738
2739 ret = qla82xx_protect_flash(ha);
2740 if (ret)
7c3df132 2741 ql_log(ql_log_warn, vha, 0xb021,
a9083016
GM		 2742 "Unable to protect flash after update.\n");
2743write_done:
2744 if (optrom)
2745 dma_free_coherent(&ha->pdev->dev,
2746 OPTROM_BURST_SIZE, optrom, optrom_dma);
2747 return ret;
2748}
2749
2750int
2751qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2752 uint32_t offset, uint32_t length)
2753{
2754 int rval;
2755
2756 /* Suspend HBA. */
2757 scsi_block_requests(vha->host);
2758 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2759 length >> 2);
2760 scsi_unblock_requests(vha->host);
2761
2762 /* Convert return ISP82xx to generic */
2763 if (rval)
2764 rval = QLA_FUNCTION_FAILED;
2765 else
2766 rval = QLA_SUCCESS;
2767 return rval;
2768}
2769
2770void
5162cf0c 2771qla82xx_start_iocbs(scsi_qla_host_t *vha)
a9083016 2772{
5162cf0c 2773 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 2774 struct req_que *req = ha->req_q_map[0];
2775 struct device_reg_82xx __iomem *reg;
2776 uint32_t dbval;
2777
2778 /* Adjust ring index. */
2779 req->ring_index++;
2780 if (req->ring_index == req->length) {
2781 req->ring_index = 0;
2782 req->ring_ptr = req->ring;
2783 } else
2784 req->ring_ptr++;
2785
2786 reg = &ha->iobase->isp82;
2787 dbval = 0x04 | (ha->portnum << 5);
2788
2789 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
6907869d
GM		 2790 if (ql2xdbwr)
2791 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2792 else {
2793 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
a9083016 2794 wmb();
6907869d
GM		 2795 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2796 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
2797 dbval);
2798 wmb();
2799 }
a9083016
GM		 2800 }
2801}
2802
e6a4202a
SS		 2803void qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2804{
7c3df132
SK		 2805 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2806
e6a4202a
SS		 2807 if (qla82xx_rom_lock(ha))
2808 /* Someone else is holding the lock. */
7c3df132
SK		 2809 ql_log(ql_log_info, vha, 0xb022,
2810 "Resetting rom_lock.\n");
e6a4202a
SS		 2811
2812 /*
2813 * Either we got the lock, or someone
2814 * else died while holding it.
2815 * In either case, unlock.
2816 */
d652e093 2817 qla82xx_rom_unlock(ha);
e6a4202a
SS		 2818}
2819
a9083016
GM		 2820/*
2821 * qla82xx_device_bootstrap
2822 * Initialize device, set DEV_READY, start fw
2823 *
2824 * Note:
2825 * IDC lock must be held upon entry
2826 *
2827 * Return:
2828 * Success : 0
2829 * Failed : 1
2830 */
2831static int
2832qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2833{
e6a4202a
SS		 2834 int rval = QLA_SUCCESS;
2835 int i, timeout;
a9083016
GM		 2836 uint32_t old_count, count;
2837 struct qla_hw_data *ha = vha->hw;
e6a4202a 2838 int need_reset = 0, peg_stuck = 1;
a9083016 2839
e6a4202a 2840 need_reset = qla82xx_need_reset(ha);
a9083016
GM		 2841
2842 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2843
2844 for (i = 0; i < 10; i++) {
2845 timeout = msleep_interruptible(200);
2846 if (timeout) {
2847 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2848 QLA8XXX_DEV_FAILED);
a9083016
GM		 2849 return QLA_FUNCTION_FAILED;
2850 }
2851
2852 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2853 if (count != old_count)
e6a4202a
SS		 2854 peg_stuck = 0;
2855 }
2856
2857 if (need_reset) {
2858 /* We are trying to perform a recovery here. */
2859 if (peg_stuck)
2860 qla82xx_rom_lock_recovery(ha);
2861 goto dev_initialize;
2862 } else {
2863 /* Start of day for this ha context. */
2864 if (peg_stuck) {
2865 /* Either we are the first or recovery in progress. */
2866 qla82xx_rom_lock_recovery(ha);
2867 goto dev_initialize;
2868 } else
2869 /* Firmware already running. */
a9083016
GM		 2870 goto dev_ready;
2871 }
2872
e6a4202a
SS		 2873 return rval;
2874
a9083016
GM		 2875dev_initialize:
2876 /* set to DEV_INITIALIZING */
7c3df132
SK		 2877 ql_log(ql_log_info, vha, 0x009e,
2878 "HW State: INITIALIZING.\n");
7d613ac6 2879 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
a9083016
GM		 2880
2881 /* Driver that sets device state to initializating sets IDC version */
2882 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2883
2884 qla82xx_idc_unlock(ha);
2885 rval = qla82xx_start_firmware(vha);
2886 qla82xx_idc_lock(ha);
2887
2888 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2889 ql_log(ql_log_fatal, vha, 0x00ad,
2890 "HW State: FAILED.\n");
a9083016 2891 qla82xx_clear_drv_active(ha);
7d613ac6 2892 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
a9083016
GM		 2893 return rval;
2894 }
2895
2896dev_ready:
7c3df132
SK		 2897 ql_log(ql_log_info, vha, 0x00ae,
2898 "HW State: READY.\n");
7d613ac6 2899 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
a9083016
GM		 2900
2901 return QLA_SUCCESS;
2902}
2903
579d12b5
SK		 2904/*
2905* qla82xx_need_qsnt_handler
2906* Code to start quiescence sequence
2907*
2908* Note:
2909* IDC lock must be held upon entry
2910*
2911* Return: void
2912*/
2913
2914static void
2915qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2916{
2917 struct qla_hw_data *ha = vha->hw;
2918 uint32_t dev_state, drv_state, drv_active;
2919 unsigned long reset_timeout;
2920
2921 if (vha->flags.online) {
2922 /*Block any further I/O and wait for pending cmnds to complete*/
8fcd6b8b 2923 qla2x00_quiesce_io(vha);
579d12b5
SK		 2924 }
2925
2926 /* Set the quiescence ready bit */
2927 qla82xx_set_qsnt_ready(ha);
2928
2929 /*wait for 30 secs for other functions to ack */
2930 reset_timeout = jiffies + (30 * HZ);
2931
2932 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2933 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2934 /* Its 2 that is written when qsnt is acked, moving one bit */
2935 drv_active = drv_active << 0x01;
2936
2937 while (drv_state != drv_active) {
2938
2939 if (time_after_eq(jiffies, reset_timeout)) {
2940 /* quiescence timeout, other functions didn't ack
2941 * changing the state to DEV_READY
2942 */
7c3df132 2943 ql_log(ql_log_info, vha, 0xb023,
5f28d2d7
SK		 2944 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2945 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
7c3df132 2946 drv_active, drv_state);
579d12b5 2947 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2948 QLA8XXX_DEV_READY);
7c3df132
SK		 2949 ql_log(ql_log_info, vha, 0xb025,
2950 "HW State: DEV_READY.\n");
579d12b5
SK		 2951 qla82xx_idc_unlock(ha);
2952 qla2x00_perform_loop_resync(vha);
2953 qla82xx_idc_lock(ha);
2954
2955 qla82xx_clear_qsnt_ready(vha);
2956 return;
2957 }
2958
2959 qla82xx_idc_unlock(ha);
2960 msleep(1000);
2961 qla82xx_idc_lock(ha);
2962
2963 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2964 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2965 drv_active = drv_active << 0x01;
2966 }
2967 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2968 /* everyone acked so set the state to DEV_QUIESCENCE */
7d613ac6 2969 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
7c3df132
SK		 2970 ql_log(ql_log_info, vha, 0xb026,
2971 "HW State: DEV_QUIESCENT.\n");
7d613ac6 2972 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
579d12b5
SK		 2973 }
2974}
2975
2976/*
2977* qla82xx_wait_for_state_change
2978* Wait for device state to change from given current state
2979*
2980* Note:
2981* IDC lock must not be held upon entry
2982*
2983* Return:
2984* Changed device state.
2985*/
2986uint32_t
2987qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2988{
2989 struct qla_hw_data *ha = vha->hw;
2990 uint32_t dev_state;
2991
2992 do {
2993 msleep(1000);
2994 qla82xx_idc_lock(ha);
2995 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2996 qla82xx_idc_unlock(ha);
2997 } while (dev_state == curr_state);
2998
2999 return dev_state;
3000}
3001
7d613ac6
SV		 3002void
3003qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
a9083016
GM		 3004{
3005 struct qla_hw_data *ha = vha->hw;
3006
3007 /* Disable the board */
7c3df132
SK		 3008 ql_log(ql_log_fatal, vha, 0x00b8,
3009 "Disabling the board.\n");
a9083016 3010
b963752f
GM		 3011 qla82xx_clear_drv_active(ha);
3012 qla82xx_idc_unlock(ha);
3013
a9083016
GM		 3014 /* Set DEV_FAILED flag to disable timer */
3015 vha->device_flags |= DFLG_DEV_FAILED;
3016 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3017 qla2x00_mark_all_devices_lost(vha, 0);
3018 vha->flags.online = 0;
3019 vha->flags.init_done = 0;
3020}
3021
3022/*
3023 * qla82xx_need_reset_handler
3024 * Code to start reset sequence
3025 *
3026 * Note:
3027 * IDC lock must be held upon entry
3028 *
3029 * Return:
3030 * Success : 0
3031 * Failed : 1
3032 */
3033static void
3034qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3035{
e5fdae55
CD		 3036 uint32_t dev_state, drv_state, drv_active;
3037 uint32_t active_mask = 0;
a9083016
GM		 3038 unsigned long reset_timeout;
3039 struct qla_hw_data *ha = vha->hw;
3040 struct req_que *req = ha->req_q_map[0];
3041
3042 if (vha->flags.online) {
3043 qla82xx_idc_unlock(ha);
3044 qla2x00_abort_isp_cleanup(vha);
3045 ha->isp_ops->get_flash_version(vha, req->ring);
3046 ha->isp_ops->nvram_config(vha);
3047 qla82xx_idc_lock(ha);
3048 }
3049
08de2844 3050 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3051 if (!ha->flags.nic_core_reset_owner) {
08de2844
GM		 3052 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3053 "reset_acknowledged by 0x%x\n", ha->portnum);
3054 qla82xx_set_rst_ready(ha);
3055 } else {
3056 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3057 drv_active &= active_mask;
3058 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3059 "active_mask: 0x%08x\n", active_mask);
3060 }
a9083016
GM		 3061
3062 /* wait for 10 seconds for reset ack from all functions */
7d613ac6 3063 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
a9083016
GM		 3064
3065 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3066 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
08de2844 3067 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016 3068
08de2844
GM		 3069 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3070 "drv_state: 0x%08x, drv_active: 0x%08x, "
3071 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3072 drv_state, drv_active, dev_state, active_mask);
3073
3074 while (drv_state != drv_active &&
7d613ac6 3075 dev_state != QLA8XXX_DEV_INITIALIZING) {
a9083016 3076 if (time_after_eq(jiffies, reset_timeout)) {
7c3df132
SK		 3077 ql_log(ql_log_warn, vha, 0x00b5,
3078 "Reset timeout.\n");
a9083016
GM		 3079 break;
3080 }
3081 qla82xx_idc_unlock(ha);
3082 msleep(1000);
3083 qla82xx_idc_lock(ha);
3084 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3085 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7d613ac6 3086 if (ha->flags.nic_core_reset_owner)
08de2844
GM		 3087 drv_active &= active_mask;
3088 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
a9083016
GM		 3089 }
3090
08de2844
GM		 3091 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3092 "drv_state: 0x%08x, drv_active: 0x%08x, "
3093 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3094 drv_state, drv_active, dev_state, active_mask);
3095
7c3df132
SK		 3096 ql_log(ql_log_info, vha, 0x00b6,
3097 "Device state is 0x%x = %s.\n",
3098 dev_state,
08de2844 3099 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
f1af6208 3100
a9083016 3101 /* Force to DEV_COLD unless someone else is starting a reset */
7d613ac6
SV		 3102 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3103 dev_state != QLA8XXX_DEV_COLD) {
7c3df132
SK		 3104 ql_log(ql_log_info, vha, 0x00b7,
3105 "HW State: COLD/RE-INIT.\n");
7d613ac6 3106 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
f4e1648a 3107 qla82xx_set_rst_ready(ha);
08de2844
GM		 3108 if (ql2xmdenable) {
3109 if (qla82xx_md_collect(vha))
3110 ql_log(ql_log_warn, vha, 0xb02c,
b6d0d9d5 3111 "Minidump not collected.\n");
08de2844
GM		 3112 } else
3113 ql_log(ql_log_warn, vha, 0xb04f,
3114 "Minidump disabled.\n");
a9083016
GM		 3115 }
3116}
3117
3173167f 3118int
08de2844
GM		 3119qla82xx_check_md_needed(scsi_qla_host_t *vha)
3120{
3121 struct qla_hw_data *ha = vha->hw;
3122 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3173167f
GM		 3123 int rval = QLA_SUCCESS;
3124
3125 fw_major_version = ha->fw_major_version;
3126 fw_minor_version = ha->fw_minor_version;
3127 fw_subminor_version = ha->fw_subminor_version;
3128
6246b8a1 3129 rval = qla2x00_get_fw_version(vha);
3173167f
GM		 3130 if (rval != QLA_SUCCESS)
3131 return rval;
3132
3133 if (ql2xmdenable) {
3134 if (!ha->fw_dumped) {
3135 if (fw_major_version != ha->fw_major_version ||
3136 fw_minor_version != ha->fw_minor_version ||
3137 fw_subminor_version != ha->fw_subminor_version) {
3173167f
GM		 3138 ql_log(ql_log_info, vha, 0xb02d,
3139 "Firmware version differs "
3140 "Previous version: %d:%d:%d - "
3141 "New version: %d:%d:%d\n",
9bc3bf27
GM		 3142 fw_major_version, fw_minor_version,
3143 fw_subminor_version,
3173167f
GM		 3144 ha->fw_major_version,
3145 ha->fw_minor_version,
9bc3bf27 3146 ha->fw_subminor_version);
3173167f
GM		 3147 /* Release MiniDump resources */
3148 qla82xx_md_free(vha);
3149 /* ALlocate MiniDump resources */
3150 qla82xx_md_prep(vha);
2e264269
GM		 3151 }
3152 } else
3153 ql_log(ql_log_info, vha, 0xb02e,
3154 "Firmware dump available to retrieve\n");
3173167f
GM		 3155 }
3156 return rval;
08de2844
GM		 3157}
3158
3159
7190575f 3160int
a9083016
GM		 3161qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3162{
7190575f
GM		 3163 uint32_t fw_heartbeat_counter;
3164 int status = 0;
a9083016 3165
7190575f
GM		 3166 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3167 QLA82XX_PEG_ALIVE_COUNTER);
a5b36321 3168 /* all 0xff, assume AER/EEH in progress, ignore */
7c3df132
SK		 3169 if (fw_heartbeat_counter == 0xffffffff) {
3170 ql_dbg(ql_dbg_timer, vha, 0x6003,
3171 "FW heartbeat counter is 0xffffffff, "
3172 "returning status=%d.\n", status);
7190575f 3173 return status;
7c3df132 3174 }
a9083016
GM		 3175 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3176 vha->seconds_since_last_heartbeat++;
3177 /* FW not alive after 2 seconds */
3178 if (vha->seconds_since_last_heartbeat == 2) {
3179 vha->seconds_since_last_heartbeat = 0;
7190575f 3180 status = 1;
a9083016 3181 }
efa786cc
LC		 3182 } else
3183 vha->seconds_since_last_heartbeat = 0;
a9083016 3184 vha->fw_heartbeat_counter = fw_heartbeat_counter;
7c3df132
SK		 3185 if (status)
3186 ql_dbg(ql_dbg_timer, vha, 0x6004,
3187 "Returning status=%d.\n", status);
7190575f 3188 return status;
a9083016
GM		 3189}
3190
3191/*
3192 * qla82xx_device_state_handler
3193 * Main state handler
3194 *
3195 * Note:
3196 * IDC lock must be held upon entry
3197 *
3198 * Return:
3199 * Success : 0
3200 * Failed : 1
3201 */
3202int
3203qla82xx_device_state_handler(scsi_qla_host_t *vha)
3204{
3205 uint32_t dev_state;
92dbf273 3206 uint32_t old_dev_state;
a9083016
GM		 3207 int rval = QLA_SUCCESS;
3208 unsigned long dev_init_timeout;
3209 struct qla_hw_data *ha = vha->hw;
92dbf273 3210 int loopcount = 0;
a9083016
GM		 3211
3212 qla82xx_idc_lock(ha);
3213 if (!vha->flags.init_done)
3214 qla82xx_set_drv_active(vha);
3215
f1af6208 3216 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273 3217 old_dev_state = dev_state;
7c3df132
SK		 3218 ql_log(ql_log_info, vha, 0x009b,
3219 "Device state is 0x%x = %s.\n",
3220 dev_state,
08de2844 3221 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
a9083016
GM		 3222
3223 /* wait for 30 seconds for device to go ready */
7d613ac6 3224 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
a9083016
GM		 3225
3226 while (1) {
3227
3228 if (time_after_eq(jiffies, dev_init_timeout)) {
7c3df132
SK		 3229 ql_log(ql_log_fatal, vha, 0x009c,
3230 "Device init failed.\n");
a9083016
GM		 3231 rval = QLA_FUNCTION_FAILED;
3232 break;
3233 }
3234 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
92dbf273
GM		 3235 if (old_dev_state != dev_state) {
3236 loopcount = 0;
3237 old_dev_state = dev_state;
3238 }
3239 if (loopcount < 5) {
7c3df132
SK		 3240 ql_log(ql_log_info, vha, 0x009d,
3241 "Device state is 0x%x = %s.\n",
3242 dev_state,
08de2844 3243 dev_state < MAX_STATES ? qdev_state(dev_state) :
7c3df132 3244 "Unknown");
92dbf273 3245 }
f1af6208 3246
a9083016 3247 switch (dev_state) {
7d613ac6
SV		 3248 case QLA8XXX_DEV_READY:
3249 ha->flags.nic_core_reset_owner = 0;
7916bb90 3250 goto rel_lock;
7d613ac6 3251 case QLA8XXX_DEV_COLD:
a9083016 3252 rval = qla82xx_device_bootstrap(vha);
08de2844 3253 break;
7d613ac6 3254 case QLA8XXX_DEV_INITIALIZING:
a9083016
GM		 3255 qla82xx_idc_unlock(ha);
3256 msleep(1000);
3257 qla82xx_idc_lock(ha);
3258 break;
7d613ac6 3259 case QLA8XXX_DEV_NEED_RESET:
c8582ad9
SK		 3260 if (!ql2xdontresethba)
3261 qla82xx_need_reset_handler(vha);
3262 else {
3263 qla82xx_idc_unlock(ha);
3264 msleep(1000);
3265 qla82xx_idc_lock(ha);
3266 }
0060ddf8 3267 dev_init_timeout = jiffies +
7d613ac6 3268 (ha->fcoe_dev_init_timeout * HZ);
a9083016 3269 break;
7d613ac6 3270 case QLA8XXX_DEV_NEED_QUIESCENT:
579d12b5
SK		 3271 qla82xx_need_qsnt_handler(vha);
3272 /* Reset timeout value after quiescence handler */
7d613ac6 3273 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5
SK		 3274 * HZ);
3275 break;
7d613ac6 3276 case QLA8XXX_DEV_QUIESCENT:
579d12b5
SK		 3277 /* Owner will exit and other will wait for the state
3278 * to get changed
3279 */
3280 if (ha->flags.quiesce_owner)
7916bb90 3281 goto rel_lock;
579d12b5 3282
a9083016
GM		 3283 qla82xx_idc_unlock(ha);
3284 msleep(1000);
3285 qla82xx_idc_lock(ha);
579d12b5
SK		 3286
3287 /* Reset timeout value after quiescence handler */
7d613ac6 3288 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
579d12b5 3289 * HZ);
a9083016 3290 break;
7d613ac6
SV		 3291 case QLA8XXX_DEV_FAILED:
3292 qla8xxx_dev_failed_handler(vha);
a9083016
GM		 3293 rval = QLA_FUNCTION_FAILED;
3294 goto exit;
3295 default:
3296 qla82xx_idc_unlock(ha);
3297 msleep(1000);
3298 qla82xx_idc_lock(ha);
3299 }
92dbf273 3300 loopcount++;
a9083016 3301 }
7916bb90 3302rel_lock:
a9083016 3303 qla82xx_idc_unlock(ha);
7916bb90 3304exit:
a9083016
GM		 3305 return rval;
3306}
3307
5988aeb2
GM		 3308static int qla82xx_check_temp(scsi_qla_host_t *vha)
3309{
3310 uint32_t temp, temp_state, temp_val;
3311 struct qla_hw_data *ha = vha->hw;
3312
3313 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3314 temp_state = qla82xx_get_temp_state(temp);
3315 temp_val = qla82xx_get_temp_val(temp);
3316
3317 if (temp_state == QLA82XX_TEMP_PANIC) {
3318 ql_log(ql_log_warn, vha, 0x600e,
3319 "Device temperature %d degrees C exceeds "
3320 " maximum allowed. Hardware has been shut down.\n",
3321 temp_val);
3322 return 1;
3323 } else if (temp_state == QLA82XX_TEMP_WARN) {
3324 ql_log(ql_log_warn, vha, 0x600f,
3325 "Device temperature %d degrees C exceeds "
3326 "operating range. Immediate action needed.\n",
3327 temp_val);
3328 }
3329 return 0;
3330}
3331
c8f6544e
CD		 3332void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3333{
3334 struct qla_hw_data *ha = vha->hw;
3335
3336 if (ha->flags.mbox_busy) {
3337 ha->flags.mbox_int = 1;
8937f2f1 3338 ha->flags.mbox_busy = 0;
c8f6544e
CD		 3339 ql_log(ql_log_warn, vha, 0x6010,
3340 "Doing premature completion of mbx command.\n");
3341 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3342 complete(&ha->mbx_intr_comp);
3343 }
3344}
3345
a9083016
GM		 3346void qla82xx_watchdog(scsi_qla_host_t *vha)
3347{
7190575f 3348 uint32_t dev_state, halt_status;
a9083016
GM		 3349 struct qla_hw_data *ha = vha->hw;
3350
a9083016 3351 /* don't poll if reset is going on */
7d613ac6 3352 if (!ha->flags.nic_core_reset_hdlr_active) {
7190575f 3353 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
5988aeb2
GM		 3354 if (qla82xx_check_temp(vha)) {
3355 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3356 ha->flags.isp82xx_fw_hung = 1;
3357 qla82xx_clear_pending_mbx(vha);
7d613ac6 3358 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
7190575f 3359 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3360 ql_log(ql_log_warn, vha, 0x6001,
3361 "Adapter reset needed.\n");
a9083016 3362 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
7d613ac6 3363 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
579d12b5 3364 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
7c3df132
SK		 3365 ql_log(ql_log_warn, vha, 0x6002,
3366 "Quiescent needed.\n");
579d12b5 3367 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
7d613ac6 3368 } else if (dev_state == QLA8XXX_DEV_FAILED &&
7916bb90
CD		 3369 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3370 vha->flags.online == 1) {
3371 ql_log(ql_log_warn, vha, 0xb055,
3372 "Adapter state is failed. Offlining.\n");
3373 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3374 ha->flags.isp82xx_fw_hung = 1;
3375 qla82xx_clear_pending_mbx(vha);
a9083016 3376 } else {
7190575f 3377 if (qla82xx_check_fw_alive(vha)) {
63154916
GM		 3378 ql_dbg(ql_dbg_timer, vha, 0x6011,
3379 "disabling pause transmit on port 0 & 1.\n");
3380 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3381 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
7190575f
GM		 3382 halt_status = qla82xx_rd_32(ha,
3383 QLA82XX_PEG_HALT_STATUS1);
63154916 3384 ql_log(ql_log_info, vha, 0x6005,
7c3df132
SK		 3385 "dumping hw/fw registers:.\n "
3386 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3387 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3388 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3389 " PEG_NET_4_PC: 0x%x.\n", halt_status,
0e8edb03
GM		 3390 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3391 qla82xx_rd_32(ha,
3392 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3393 qla82xx_rd_32(ha,
3394 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3395 qla82xx_rd_32(ha,
3396 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3397 qla82xx_rd_32(ha,
3398 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3399 qla82xx_rd_32(ha,
3400 QLA82XX_CRB_PEG_NET_4 + 0x3c));
2cc97965 3401 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
10a340e6
CD		 3402 ql_log(ql_log_warn, vha, 0xb052,
3403 "Firmware aborted with "
3404 "error code 0x00006700. Device is "
3405 "being reset.\n");
7190575f
GM		 3406 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3407 set_bit(ISP_UNRECOVERABLE,
3408 &vha->dpc_flags);
3409 } else {
7c3df132
SK		 3410 ql_log(ql_log_info, vha, 0x6006,
3411 "Detect abort needed.\n");
7190575f
GM		 3412 set_bit(ISP_ABORT_NEEDED,
3413 &vha->dpc_flags);
3414 }
7190575f 3415 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 3416 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3417 qla82xx_clear_pending_mbx(vha);
7190575f 3418 }
a9083016
GM		 3419 }
3420 }
3421}
3422
3423int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3424{
3425 int rval;
3426 rval = qla82xx_device_state_handler(vha);
3427 return rval;
3428}
3429
08de2844
GM		 3430void
3431qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3432{
3433 struct qla_hw_data *ha = vha->hw;
3434 uint32_t dev_state;
3435
3436 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
7d613ac6 3437 if (dev_state == QLA8XXX_DEV_READY) {
08de2844
GM		 3438 ql_log(ql_log_info, vha, 0xb02f,
3439 "HW State: NEED RESET\n");
3440 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6
SV		 3441 QLA8XXX_DEV_NEED_RESET);
3442 ha->flags.nic_core_reset_owner = 1;
08de2844
GM		 3443 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3444 "reset_owner is 0x%x\n", ha->portnum);
3445 } else
3446 ql_log(ql_log_info, vha, 0xb031,
3447 "Device state is 0x%x = %s.\n",
3448 dev_state,
3449 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3450}
3451
a9083016
GM		 3452/*
3453 * qla82xx_abort_isp
3454 * Resets ISP and aborts all outstanding commands.
3455 *
3456 * Input:
3457 * ha = adapter block pointer.
3458 *
3459 * Returns:
3460 * 0 = success
3461 */
3462int
3463qla82xx_abort_isp(scsi_qla_host_t *vha)
3464{
3465 int rval;
3466 struct qla_hw_data *ha = vha->hw;
a9083016
GM		 3467
3468 if (vha->device_flags & DFLG_DEV_FAILED) {
7c3df132
SK		 3469 ql_log(ql_log_warn, vha, 0x8024,
3470 "Device in failed state, exiting.\n");
a9083016
GM		 3471 return QLA_SUCCESS;
3472 }
7d613ac6 3473 ha->flags.nic_core_reset_hdlr_active = 1;
a9083016
GM		 3474
3475 qla82xx_idc_lock(ha);
08de2844 3476 qla82xx_set_reset_owner(vha);
a9083016
GM		 3477 qla82xx_idc_unlock(ha);
3478
3479 rval = qla82xx_device_state_handler(vha);
3480
3481 qla82xx_idc_lock(ha);
3482 qla82xx_clear_rst_ready(ha);
3483 qla82xx_idc_unlock(ha);
3484
cdbb0a4f 3485 if (rval == QLA_SUCCESS) {
7190575f 3486 ha->flags.isp82xx_fw_hung = 0;
7d613ac6 3487 ha->flags.nic_core_reset_hdlr_active = 0;
a9083016 3488 qla82xx_restart_isp(vha);
cdbb0a4f 3489 }
f1af6208
GM		 3490
3491 if (rval) {
3492 vha->flags.online = 1;
3493 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3494 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 3495 ql_log(ql_log_warn, vha, 0x8027,
3496 "ISP error recover failed - board "
3497 "disabled.\n");
f1af6208
GM		 3498 /*
3499 * The next call disables the board
3500 * completely.
3501 */
3502 ha->isp_ops->reset_adapter(vha);
3503 vha->flags.online = 0;
3504 clear_bit(ISP_ABORT_RETRY,
3505 &vha->dpc_flags);
3506 rval = QLA_SUCCESS;
3507 } else { /* schedule another ISP abort */
3508 ha->isp_abort_cnt--;
7c3df132
SK		 3509 ql_log(ql_log_warn, vha, 0x8036,
3510 "ISP abort - retry remaining %d.\n",
3511 ha->isp_abort_cnt);
f1af6208
GM		 3512 rval = QLA_FUNCTION_FAILED;
3513 }
3514 } else {
3515 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 3516 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3517 "ISP error recovery - retrying (%d) more times.\n",
3518 ha->isp_abort_cnt);
f1af6208
GM		 3519 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3520 rval = QLA_FUNCTION_FAILED;
3521 }
3522 }
a9083016
GM		 3523 return rval;
3524}
3525
3526/*
3527 * qla82xx_fcoe_ctx_reset
3528 * Perform a quick reset and aborts all outstanding commands.
3529 * This will only perform an FCoE context reset and avoids a full blown
3530 * chip reset.
3531 *
3532 * Input:
3533 * ha = adapter block pointer.
3534 * is_reset_path = flag for identifying the reset path.
3535 *
3536 * Returns:
3537 * 0 = success
3538 */
3539int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3540{
3541 int rval = QLA_FUNCTION_FAILED;
3542
3543 if (vha->flags.online) {
3544 /* Abort all outstanding commands, so as to be requeued later */
3545 qla2x00_abort_isp_cleanup(vha);
3546 }
3547
3548 /* Stop currently executing firmware.
3549 * This will destroy existing FCoE context at the F/W end.
3550 */
3551 qla2x00_try_to_stop_firmware(vha);
3552
3553 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3554 rval = qla82xx_restart_isp(vha);
3555
3556 return rval;
3557}
3558
3559/*
3560 * qla2x00_wait_for_fcoe_ctx_reset
3561 * Wait till the FCoE context is reset.
3562 *
3563 * Note:
3564 * Does context switching here.
3565 * Release SPIN_LOCK (if any) before calling this routine.
3566 *
3567 * Return:
3568 * Success (fcoe_ctx reset is done) : 0
3569 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3570 */
3571int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3572{
3573 int status = QLA_FUNCTION_FAILED;
3574 unsigned long wait_reset;
3575
3576 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3577 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3578 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3579 && time_before(jiffies, wait_reset)) {
3580
3581 set_current_state(TASK_UNINTERRUPTIBLE);
3582 schedule_timeout(HZ);
3583
3584 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3585 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3586 status = QLA_SUCCESS;
3587 break;
3588 }
3589 }
7c3df132 3590 ql_dbg(ql_dbg_p3p, vha, 0xb027,
d8424f68 3591 "%s: status=%d.\n", __func__, status);
a9083016
GM		 3592
3593 return status;
3594}
7190575f
GM		 3595
3596void
3597qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3598{
3599 int i;
3600 unsigned long flags;
3601 struct qla_hw_data *ha = vha->hw;
3602
3603 /* Check if 82XX firmware is alive or not
3604 * We may have arrived here from NEED_RESET
3605 * detection only
3606 */
3607 if (!ha->flags.isp82xx_fw_hung) {
3608 for (i = 0; i < 2; i++) {
3609 msleep(1000);
3610 if (qla82xx_check_fw_alive(vha)) {
3611 ha->flags.isp82xx_fw_hung = 1;
c8f6544e 3612 qla82xx_clear_pending_mbx(vha);
7190575f
GM		 3613 break;
3614 }
3615 }
3616 }
7c3df132
SK		 3617 ql_dbg(ql_dbg_init, vha, 0x00b0,
3618 "Entered %s fw_hung=%d.\n",
3619 __func__, ha->flags.isp82xx_fw_hung);
7190575f
GM		 3620
3621 /* Abort all commands gracefully if fw NOT hung */
3622 if (!ha->flags.isp82xx_fw_hung) {
3623 int cnt, que;
3624 srb_t *sp;
3625 struct req_que *req;
3626
3627 spin_lock_irqsave(&ha->hardware_lock, flags);
3628 for (que = 0; que < ha->max_req_queues; que++) {
3629 req = ha->req_q_map[que];
3630 if (!req)
3631 continue;
3632 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
3633 sp = req->outstanding_cmds[cnt];
3634 if (sp) {
9ba56b95 3635 if (!sp->u.scmd.ctx ||
7190575f
GM		 3636 (sp->flags & SRB_FCP_CMND_DMA_VALID)) {
3637 spin_unlock_irqrestore(
3638 &ha->hardware_lock, flags);
3639 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 3640 ql_log(ql_log_info, vha,
3641 0x00b1,
3642 "mbx abort failed.\n");
7190575f 3643 } else {
7c3df132
SK		 3644 ql_log(ql_log_info, vha,
3645 0x00b2,
3646 "mbx abort success.\n");
7190575f
GM		 3647 }
3648 spin_lock_irqsave(&ha->hardware_lock, flags);
3649 }
3650 }
3651 }
3652 }
3653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3654
3655 /* Wait for pending cmds (physical and virtual) to complete */
3656 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3657 WAIT_HOST) == QLA_SUCCESS) {
7c3df132
SK		 3658 ql_dbg(ql_dbg_init, vha, 0x00b3,
3659 "Done wait for "
3660 "pending commands.\n");
7190575f
GM		 3661 }
3662 }
3663}
08de2844
GM		 3664
3665/* Minidump related functions */
08de2844
GM		 3666static int
3667qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3668 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3669{
3670 struct qla_hw_data *ha = vha->hw;
3671 struct qla82xx_md_entry_crb *crb_entry;
3672 uint32_t read_value, opcode, poll_time;
3673 uint32_t addr, index, crb_addr;
3674 unsigned long wtime;
3675 struct qla82xx_md_template_hdr *tmplt_hdr;
3676 uint32_t rval = QLA_SUCCESS;
3677 int i;
3678
3679 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3680 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3681 crb_addr = crb_entry->addr;
3682
3683 for (i = 0; i < crb_entry->op_count; i++) {
3684 opcode = crb_entry->crb_ctrl.opcode;
3685 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3686 qla82xx_md_rw_32(ha, crb_addr,
3687 crb_entry->value_1, 1);
3688 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3689 }
3690
3691 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3692 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3693 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3694 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3695 }
3696
3697 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3698 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3699 read_value &= crb_entry->value_2;
3700 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3701 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3702 read_value |= crb_entry->value_3;
3703 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3704 }
3705 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3706 }
3707
3708 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3709 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3710 read_value |= crb_entry->value_3;
3711 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3712 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3713 }
3714
3715 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3716 poll_time = crb_entry->crb_strd.poll_timeout;
3717 wtime = jiffies + poll_time;
3718 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3719
3720 do {
3721 if ((read_value & crb_entry->value_2)
3722 == crb_entry->value_1)
3723 break;
3724 else if (time_after_eq(jiffies, wtime)) {
3725 /* capturing dump failed */
3726 rval = QLA_FUNCTION_FAILED;
3727 break;
3728 } else
3729 read_value = qla82xx_md_rw_32(ha,
3730 crb_addr, 0, 0);
3731 } while (1);
3732 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3733 }
3734
3735 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3736 if (crb_entry->crb_strd.state_index_a) {
3737 index = crb_entry->crb_strd.state_index_a;
3738 addr = tmplt_hdr->saved_state_array[index];
3739 } else
3740 addr = crb_addr;
3741
3742 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3743 index = crb_entry->crb_ctrl.state_index_v;
3744 tmplt_hdr->saved_state_array[index] = read_value;
3745 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3746 }
3747
3748 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3749 if (crb_entry->crb_strd.state_index_a) {
3750 index = crb_entry->crb_strd.state_index_a;
3751 addr = tmplt_hdr->saved_state_array[index];
3752 } else
3753 addr = crb_addr;
3754
3755 if (crb_entry->crb_ctrl.state_index_v) {
3756 index = crb_entry->crb_ctrl.state_index_v;
3757 read_value =
3758 tmplt_hdr->saved_state_array[index];
3759 } else
3760 read_value = crb_entry->value_1;
3761
3762 qla82xx_md_rw_32(ha, addr, read_value, 1);
3763 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3764 }
3765
3766 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3767 index = crb_entry->crb_ctrl.state_index_v;
3768 read_value = tmplt_hdr->saved_state_array[index];
3769 read_value <<= crb_entry->crb_ctrl.shl;
3770 read_value >>= crb_entry->crb_ctrl.shr;
3771 if (crb_entry->value_2)
3772 read_value &= crb_entry->value_2;
3773 read_value |= crb_entry->value_3;
3774 read_value += crb_entry->value_1;
3775 tmplt_hdr->saved_state_array[index] = read_value;
3776 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3777 }
3778 crb_addr += crb_entry->crb_strd.addr_stride;
3779 }
3780 return rval;
3781}
3782
3783static void
3784qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3785 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3786{
3787 struct qla_hw_data *ha = vha->hw;
3788 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3789 struct qla82xx_md_entry_rdocm *ocm_hdr;
3790 uint32_t *data_ptr = *d_ptr;
3791
3792 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3793 r_addr = ocm_hdr->read_addr;
3794 r_stride = ocm_hdr->read_addr_stride;
3795 loop_cnt = ocm_hdr->op_count;
3796
3797 for (i = 0; i < loop_cnt; i++) {
3798 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase));
3799 *data_ptr++ = cpu_to_le32(r_value);
3800 r_addr += r_stride;
3801 }
3802 *d_ptr = data_ptr;
3803}
3804
3805static void
3806qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3807 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3808{
3809 struct qla_hw_data *ha = vha->hw;
3810 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3811 struct qla82xx_md_entry_mux *mux_hdr;
3812 uint32_t *data_ptr = *d_ptr;
3813
3814 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3815 r_addr = mux_hdr->read_addr;
3816 s_addr = mux_hdr->select_addr;
3817 s_stride = mux_hdr->select_value_stride;
3818 s_value = mux_hdr->select_value;
3819 loop_cnt = mux_hdr->op_count;
3820
3821 for (i = 0; i < loop_cnt; i++) {
3822 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3823 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3824 *data_ptr++ = cpu_to_le32(s_value);
3825 *data_ptr++ = cpu_to_le32(r_value);
3826 s_value += s_stride;
3827 }
3828 *d_ptr = data_ptr;
3829}
3830
3831static void
3832qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3833 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3834{
3835 struct qla_hw_data *ha = vha->hw;
3836 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3837 struct qla82xx_md_entry_crb *crb_hdr;
3838 uint32_t *data_ptr = *d_ptr;
3839
3840 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3841 r_addr = crb_hdr->addr;
3842 r_stride = crb_hdr->crb_strd.addr_stride;
3843 loop_cnt = crb_hdr->op_count;
3844
3845 for (i = 0; i < loop_cnt; i++) {
3846 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3847 *data_ptr++ = cpu_to_le32(r_addr);
3848 *data_ptr++ = cpu_to_le32(r_value);
3849 r_addr += r_stride;
3850 }
3851 *d_ptr = data_ptr;
3852}
3853
3854static int
3855qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3856 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3857{
3858 struct qla_hw_data *ha = vha->hw;
3859 uint32_t addr, r_addr, c_addr, t_r_addr;
3860 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3861 unsigned long p_wait, w_time, p_mask;
3862 uint32_t c_value_w, c_value_r;
3863 struct qla82xx_md_entry_cache *cache_hdr;
3864 int rval = QLA_FUNCTION_FAILED;
3865 uint32_t *data_ptr = *d_ptr;
3866
3867 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3868 loop_count = cache_hdr->op_count;
3869 r_addr = cache_hdr->read_addr;
3870 c_addr = cache_hdr->control_addr;
3871 c_value_w = cache_hdr->cache_ctrl.write_value;
3872
3873 t_r_addr = cache_hdr->tag_reg_addr;
3874 t_value = cache_hdr->addr_ctrl.init_tag_value;
3875 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3876 p_wait = cache_hdr->cache_ctrl.poll_wait;
3877 p_mask = cache_hdr->cache_ctrl.poll_mask;
3878
3879 for (i = 0; i < loop_count; i++) {
3880 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3881 if (c_value_w)
3882 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3883
3884 if (p_mask) {
3885 w_time = jiffies + p_wait;
3886 do {
3887 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3888 if ((c_value_r & p_mask) == 0)
3889 break;
3890 else if (time_after_eq(jiffies, w_time)) {
3891 /* capturing dump failed */
3892 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3893 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3894 "w_time: 0x%lx\n",
3895 c_value_r, p_mask, w_time);
3896 return rval;
3897 }
3898 } while (1);
3899 }
3900
3901 addr = r_addr;
3902 for (k = 0; k < r_cnt; k++) {
3903 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3904 *data_ptr++ = cpu_to_le32(r_value);
3905 addr += cache_hdr->read_ctrl.read_addr_stride;
3906 }
3907 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3908 }
3909 *d_ptr = data_ptr;
3910 return QLA_SUCCESS;
3911}
3912
3913static void
3914qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3915 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3916{
3917 struct qla_hw_data *ha = vha->hw;
3918 uint32_t addr, r_addr, c_addr, t_r_addr;
3919 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3920 uint32_t c_value_w;
3921 struct qla82xx_md_entry_cache *cache_hdr;
3922 uint32_t *data_ptr = *d_ptr;
3923
3924 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3925 loop_count = cache_hdr->op_count;
3926 r_addr = cache_hdr->read_addr;
3927 c_addr = cache_hdr->control_addr;
3928 c_value_w = cache_hdr->cache_ctrl.write_value;
3929
3930 t_r_addr = cache_hdr->tag_reg_addr;
3931 t_value = cache_hdr->addr_ctrl.init_tag_value;
3932 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3933
3934 for (i = 0; i < loop_count; i++) {
3935 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3936 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3937 addr = r_addr;
3938 for (k = 0; k < r_cnt; k++) {
3939 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3940 *data_ptr++ = cpu_to_le32(r_value);
3941 addr += cache_hdr->read_ctrl.read_addr_stride;
3942 }
3943 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3944 }
3945 *d_ptr = data_ptr;
3946}
3947
3948static void
3949qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3950 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3951{
3952 struct qla_hw_data *ha = vha->hw;
3953 uint32_t s_addr, r_addr;
3954 uint32_t r_stride, r_value, r_cnt, qid = 0;
3955 uint32_t i, k, loop_cnt;
3956 struct qla82xx_md_entry_queue *q_hdr;
3957 uint32_t *data_ptr = *d_ptr;
3958
3959 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3960 s_addr = q_hdr->select_addr;
3961 r_cnt = q_hdr->rd_strd.read_addr_cnt;
3962 r_stride = q_hdr->rd_strd.read_addr_stride;
3963 loop_cnt = q_hdr->op_count;
3964
3965 for (i = 0; i < loop_cnt; i++) {
3966 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3967 r_addr = q_hdr->read_addr;
3968 for (k = 0; k < r_cnt; k++) {
3969 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3970 *data_ptr++ = cpu_to_le32(r_value);
3971 r_addr += r_stride;
3972 }
3973 qid += q_hdr->q_strd.queue_id_stride;
3974 }
3975 *d_ptr = data_ptr;
3976}
3977
3978static void
3979qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3980 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3981{
3982 struct qla_hw_data *ha = vha->hw;
3983 uint32_t r_addr, r_value;
3984 uint32_t i, loop_cnt;
3985 struct qla82xx_md_entry_rdrom *rom_hdr;
3986 uint32_t *data_ptr = *d_ptr;
3987
3988 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
3989 r_addr = rom_hdr->read_addr;
3990 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
3991
3992 for (i = 0; i < loop_cnt; i++) {
3993 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
3994 (r_addr & 0xFFFF0000), 1);
3995 r_value = qla82xx_md_rw_32(ha,
3996 MD_DIRECT_ROM_READ_BASE +
3997 (r_addr & 0x0000FFFF), 0, 0);
3998 *data_ptr++ = cpu_to_le32(r_value);
3999 r_addr += sizeof(uint32_t);
4000 }
4001 *d_ptr = data_ptr;
4002}
4003
4004static int
4005qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4006 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4007{
4008 struct qla_hw_data *ha = vha->hw;
4009 uint32_t r_addr, r_value, r_data;
4010 uint32_t i, j, loop_cnt;
4011 struct qla82xx_md_entry_rdmem *m_hdr;
4012 unsigned long flags;
4013 int rval = QLA_FUNCTION_FAILED;
4014 uint32_t *data_ptr = *d_ptr;
4015
4016 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4017 r_addr = m_hdr->read_addr;
4018 loop_cnt = m_hdr->read_data_size/16;
4019
4020 if (r_addr & 0xf) {
4021 ql_log(ql_log_warn, vha, 0xb033,
d6a03581 4022 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
08de2844
GM		 4023 return rval;
4024 }
4025
4026 if (m_hdr->read_data_size % 16) {
4027 ql_log(ql_log_warn, vha, 0xb034,
4028 "Read data[0x%x] not multiple of 16 bytes\n",
4029 m_hdr->read_data_size);
4030 return rval;
4031 }
4032
4033 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4034 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4035 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4036
4037 write_lock_irqsave(&ha->hw_lock, flags);
4038 for (i = 0; i < loop_cnt; i++) {
4039 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4040 r_value = 0;
4041 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4042 r_value = MIU_TA_CTL_ENABLE;
4043 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4044 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4045 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4046
4047 for (j = 0; j < MAX_CTL_CHECK; j++) {
4048 r_value = qla82xx_md_rw_32(ha,
4049 MD_MIU_TEST_AGT_CTRL, 0, 0);
4050 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4051 break;
4052 }
4053
4054 if (j >= MAX_CTL_CHECK) {
4055 printk_ratelimited(KERN_ERR
4056 "failed to read through agent\n");
4057 write_unlock_irqrestore(&ha->hw_lock, flags);
4058 return rval;
4059 }
4060
4061 for (j = 0; j < 4; j++) {
4062 r_data = qla82xx_md_rw_32(ha,
4063 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4064 *data_ptr++ = cpu_to_le32(r_data);
4065 }
4066 r_addr += 16;
4067 }
4068 write_unlock_irqrestore(&ha->hw_lock, flags);
4069 *d_ptr = data_ptr;
4070 return QLA_SUCCESS;
4071}
4072
4073static int
4074qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4075{
4076 struct qla_hw_data *ha = vha->hw;
4077 uint64_t chksum = 0;
4078 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4079 int count = ha->md_template_size/sizeof(uint32_t);
4080
4081 while (count-- > 0)
4082 chksum += *d_ptr++;
4083 while (chksum >> 32)
4084 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4085 return ~chksum;
4086}
4087
4088static void
4089qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4090 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4091{
4092 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4093 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4094 "Skipping entry[%d]: "
4095 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4096 index, entry_hdr->entry_type,
4097 entry_hdr->d_ctrl.entry_capture_mask);
4098}
4099
4100int
4101qla82xx_md_collect(scsi_qla_host_t *vha)
4102{
4103 struct qla_hw_data *ha = vha->hw;
4104 int no_entry_hdr = 0;
4105 qla82xx_md_entry_hdr_t *entry_hdr;
4106 struct qla82xx_md_template_hdr *tmplt_hdr;
4107 uint32_t *data_ptr;
4108 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4109 int i = 0, rval = QLA_FUNCTION_FAILED;
4110
4111 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4112 data_ptr = (uint32_t *)ha->md_dump;
4113
4114 if (ha->fw_dumped) {
a8faa263
GM		 4115 ql_log(ql_log_warn, vha, 0xb037,
4116 "Firmware has been previously dumped (%p) "
4117 "-- ignoring request.\n", ha->fw_dump);
08de2844
GM		 4118 goto md_failed;
4119 }
4120
4121 ha->fw_dumped = 0;
4122
4123 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4124 ql_log(ql_log_warn, vha, 0xb038,
4125 "Memory not allocated for minidump capture\n");
4126 goto md_failed;
4127 }
4128
b6d0d9d5
GM		 4129 if (ha->flags.isp82xx_no_md_cap) {
4130 ql_log(ql_log_warn, vha, 0xb054,
4131 "Forced reset from application, "
4132 "ignore minidump capture\n");
4133 ha->flags.isp82xx_no_md_cap = 0;
4134 goto md_failed;
4135 }
4136
08de2844
GM		 4137 if (qla82xx_validate_template_chksum(vha)) {
4138 ql_log(ql_log_info, vha, 0xb039,
4139 "Template checksum validation error\n");
4140 goto md_failed;
4141 }
4142
4143 no_entry_hdr = tmplt_hdr->num_of_entries;
4144 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4145 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4146
4147 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4148 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4149
4150 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4151
4152 /* Validate whether required debug level is set */
4153 if ((f_capture_mask & 0x3) != 0x3) {
4154 ql_log(ql_log_warn, vha, 0xb03c,
4155 "Minimum required capture mask[0x%x] level not set\n",
4156 f_capture_mask);
4157 goto md_failed;
4158 }
4159 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4160
4161 tmplt_hdr->driver_info[0] = vha->host_no;
4162 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4163 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4164 QLA_DRIVER_BETA_VER;
4165
4166 total_data_size = ha->md_dump_size;
4167
880fdedb 4168 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
08de2844
GM		 4169 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4170
4171 /* Check whether template obtained is valid */
4172 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4173 ql_log(ql_log_warn, vha, 0xb04e,
4174 "Bad template header entry type: 0x%x obtained\n",
4175 tmplt_hdr->entry_type);
4176 goto md_failed;
4177 }
4178
4179 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4180 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4181
4182 /* Walk through the entry headers */
4183 for (i = 0; i < no_entry_hdr; i++) {
4184
4185 if (data_collected > total_data_size) {
4186 ql_log(ql_log_warn, vha, 0xb03e,
4187 "More MiniDump data collected: [0x%x]\n",
4188 data_collected);
4189 goto md_failed;
4190 }
4191
4192 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4193 ql2xmdcapmask)) {
4194 entry_hdr->d_ctrl.driver_flags |=
4195 QLA82XX_DBG_SKIPPED_FLAG;
4196 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4197 "Skipping entry[%d]: "
4198 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4199 i, entry_hdr->entry_type,
4200 entry_hdr->d_ctrl.entry_capture_mask);
4201 goto skip_nxt_entry;
4202 }
4203
4204 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4205 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4206 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4207 __func__, i, data_ptr, entry_hdr,
4208 entry_hdr->entry_type,
4209 entry_hdr->d_ctrl.entry_capture_mask);
4210
4211 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4212 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4213 data_collected, (ha->md_dump_size - data_collected));
4214
4215 /* Decode the entry type and take
4216 * required action to capture debug data */
4217 switch (entry_hdr->entry_type) {
4218 case QLA82XX_RDEND:
4219 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4220 break;
4221 case QLA82XX_CNTRL:
4222 rval = qla82xx_minidump_process_control(vha,
4223 entry_hdr, &data_ptr);
4224 if (rval != QLA_SUCCESS) {
4225 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4226 goto md_failed;
4227 }
4228 break;
4229 case QLA82XX_RDCRB:
4230 qla82xx_minidump_process_rdcrb(vha,
4231 entry_hdr, &data_ptr);
4232 break;
4233 case QLA82XX_RDMEM:
4234 rval = qla82xx_minidump_process_rdmem(vha,
4235 entry_hdr, &data_ptr);
4236 if (rval != QLA_SUCCESS) {
4237 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4238 goto md_failed;
4239 }
4240 break;
4241 case QLA82XX_BOARD:
4242 case QLA82XX_RDROM:
4243 qla82xx_minidump_process_rdrom(vha,
4244 entry_hdr, &data_ptr);
4245 break;
4246 case QLA82XX_L2DTG:
4247 case QLA82XX_L2ITG:
4248 case QLA82XX_L2DAT:
4249 case QLA82XX_L2INS:
4250 rval = qla82xx_minidump_process_l2tag(vha,
4251 entry_hdr, &data_ptr);
4252 if (rval != QLA_SUCCESS) {
4253 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4254 goto md_failed;
4255 }
4256 break;
4257 case QLA82XX_L1DAT:
4258 case QLA82XX_L1INS:
4259 qla82xx_minidump_process_l1cache(vha,
4260 entry_hdr, &data_ptr);
4261 break;
4262 case QLA82XX_RDOCM:
4263 qla82xx_minidump_process_rdocm(vha,
4264 entry_hdr, &data_ptr);
4265 break;
4266 case QLA82XX_RDMUX:
4267 qla82xx_minidump_process_rdmux(vha,
4268 entry_hdr, &data_ptr);
4269 break;
4270 case QLA82XX_QUEUE:
4271 qla82xx_minidump_process_queue(vha,
4272 entry_hdr, &data_ptr);
4273 break;
4274 case QLA82XX_RDNOP:
4275 default:
4276 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4277 break;
4278 }
4279
4280 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4281 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4282
4283 data_collected = (uint8_t *)data_ptr -
4284 (uint8_t *)ha->md_dump;
4285skip_nxt_entry:
4286 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4287 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4288 }
4289
4290 if (data_collected != total_data_size) {
880fdedb 4291 ql_dbg(ql_dbg_p3p, vha, 0xb043,
08de2844
GM		 4292 "MiniDump data mismatch: Data collected: [0x%x],"
4293 "total_data_size:[0x%x]\n",
4294 data_collected, total_data_size);
4295 goto md_failed;
4296 }
4297
4298 ql_log(ql_log_info, vha, 0xb044,
4299 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4300 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4301 ha->fw_dumped = 1;
4302 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4303
4304md_failed:
4305 return rval;
4306}
4307
4308int
4309qla82xx_md_alloc(scsi_qla_host_t *vha)
4310{
4311 struct qla_hw_data *ha = vha->hw;
4312 int i, k;
4313 struct qla82xx_md_template_hdr *tmplt_hdr;
4314
4315 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4316
4317 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4318 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4319 ql_log(ql_log_info, vha, 0xb045,
4320 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4321 ql2xmdcapmask);
4322 }
4323
4324 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4325 if (i & ql2xmdcapmask)
4326 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4327 }
4328
4329 if (ha->md_dump) {
4330 ql_log(ql_log_warn, vha, 0xb046,
4331 "Firmware dump previously allocated.\n");
4332 return 1;
4333 }
4334
4335 ha->md_dump = vmalloc(ha->md_dump_size);
4336 if (ha->md_dump == NULL) {
4337 ql_log(ql_log_warn, vha, 0xb047,
4338 "Unable to allocate memory for Minidump size "
4339 "(0x%x).\n", ha->md_dump_size);
4340 return 1;
4341 }
4342 return 0;
4343}
4344
4345void
4346qla82xx_md_free(scsi_qla_host_t *vha)
4347{
4348 struct qla_hw_data *ha = vha->hw;
4349
4350 /* Release the template header allocated */
4351 if (ha->md_tmplt_hdr) {
4352 ql_log(ql_log_info, vha, 0xb048,
4353 "Free MiniDump template: %p, size (%d KB)\n",
4354 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4355 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4356 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4357 ha->md_tmplt_hdr = 0;
4358 }
4359
4360 /* Release the template data buffer allocated */
4361 if (ha->md_dump) {
4362 ql_log(ql_log_info, vha, 0xb049,
4363 "Free MiniDump memory: %p, size (%d KB)\n",
4364 ha->md_dump, ha->md_dump_size / 1024);
4365 vfree(ha->md_dump);
4366 ha->md_dump_size = 0;
4367 ha->md_dump = 0;
4368 }
4369}
4370
4371void
4372qla82xx_md_prep(scsi_qla_host_t *vha)
4373{
4374 struct qla_hw_data *ha = vha->hw;
4375 int rval;
4376
4377 /* Get Minidump template size */
4378 rval = qla82xx_md_get_template_size(vha);
4379 if (rval == QLA_SUCCESS) {
4380 ql_log(ql_log_info, vha, 0xb04a,
4381 "MiniDump Template size obtained (%d KB)\n",
4382 ha->md_template_size / 1024);
4383
4384 /* Get Minidump template */
4385 rval = qla82xx_md_get_template(vha);
4386 if (rval == QLA_SUCCESS) {
4387 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4388 "MiniDump Template obtained\n");
4389
4390 /* Allocate memory for minidump */
4391 rval = qla82xx_md_alloc(vha);
4392 if (rval == QLA_SUCCESS)
4393 ql_log(ql_log_info, vha, 0xb04c,
4394 "MiniDump memory allocated (%d KB)\n",
4395 ha->md_dump_size / 1024);
4396 else {
4397 ql_log(ql_log_info, vha, 0xb04d,
4398 "Free MiniDump template: %p, size: (%d KB)\n",
4399 ha->md_tmplt_hdr,
4400 ha->md_template_size / 1024);
4401 dma_free_coherent(&ha->pdev->dev,
4402 ha->md_template_size,
4403 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4404 ha->md_tmplt_hdr = 0;
4405 }
4406
4407 }
4408 }
4409}
999916dc
SK		 4410
4411int
4412qla82xx_beacon_on(struct scsi_qla_host *vha)
4413{
4414
4415 int rval;
4416 struct qla_hw_data *ha = vha->hw;
4417 qla82xx_idc_lock(ha);
4418 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4419
4420 if (rval) {
4421 ql_log(ql_log_warn, vha, 0xb050,
4422 "mbx set led config failed in %s\n", __func__);
4423 goto exit;
4424 }
4425 ha->beacon_blink_led = 1;
4426exit:
4427 qla82xx_idc_unlock(ha);
4428 return rval;
4429}
4430
4431int
4432qla82xx_beacon_off(struct scsi_qla_host *vha)
4433{
4434
4435 int rval;
4436 struct qla_hw_data *ha = vha->hw;
4437 qla82xx_idc_lock(ha);
4438 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4439
4440 if (rval) {
4441 ql_log(ql_log_warn, vha, 0xb051,
4442 "mbx set led config failed in %s\n", __func__);
4443 goto exit;
4444 }
4445 ha->beacon_blink_led = 0;
4446exit:
4447 qla82xx_idc_unlock(ha);
4448 return rval;
4449}
Michael's Linux tree.