[people/ms/linux.git] / drivers / scsi / sata_sil.c

/*
 *  sata_sil.c - Silicon Image SATA
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003-2005 Red Hat, Inc.
 *  Copyright 2003 Benjamin Herrenschmidt
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Documentation for SiI 3112:
 *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
 *
 *  Other errata and documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sil"
#define DRV_VERSION	"0.9"

enum {
	SIL_FLAG_MOD15WRITE	= (1 << 30),

	sil_3112		= 0,
	sil_3112_m15w		= 1,
	sil_3114		= 2,

	SIL_FIFO_R0		= 0x40,
	SIL_FIFO_W0		= 0x41,
	SIL_FIFO_R1		= 0x44,
	SIL_FIFO_W1		= 0x45,
	SIL_FIFO_R2		= 0x240,
	SIL_FIFO_W2		= 0x241,
	SIL_FIFO_R3		= 0x244,
	SIL_FIFO_W3		= 0x245,

	SIL_SYSCFG		= 0x48,
	SIL_MASK_IDE0_INT	= (1 << 22),
	SIL_MASK_IDE1_INT	= (1 << 23),
	SIL_MASK_IDE2_INT	= (1 << 24),
	SIL_MASK_IDE3_INT	= (1 << 25),
	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
	SIL_MASK_4PORT		= SIL_MASK_2PORT |
				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,

	SIL_IDE2_BMDMA		= 0x200,

	SIL_INTR_STEERING	= (1 << 1),
	SIL_QUIRK_MOD15WRITE	= (1 << 0),
	SIL_QUIRK_UDMA5MAX	= (1 << 1),
};

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void sil_post_set_mode (struct ata_port *ap);

static struct pci_device_id sil_pci_tbl[] = {
	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	{ }	/* terminate list */
};


/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
	const char * product;
	unsigned int quirk;
} sil_blacklist [] = {
	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120026AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3200822AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
	{ }
};

static struct pci_driver sil_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil_pci_tbl,
	.probe			= sil_init_one,
	.remove			= ata_pci_remove_one,
};

static Scsi_Host_Template sil_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};

static struct ata_port_operations sil_ops = {
	.port_disable		= ata_port_disable,
	.dev_config		= sil_dev_config,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.post_set_mode		= sil_post_set_mode,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sil_scr_read,
	.scr_write		= sil_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_port_info sil_port_info[] = {
	/* sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	}, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO |
				  SIL_FLAG_MOD15WRITE,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	}, /* sil_3114 */
	{
		.sht		= &sil_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_SRST | ATA_FLAG_MMIO,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
};

/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
	unsigned long tf;	/* ATA taskfile register block */
	unsigned long ctl;	/* ATA control/altstatus register block */
	unsigned long bmdma;	/* DMA register block */
	unsigned long scr;	/* SATA control register block */
	unsigned long sien;	/* SATA Interrupt Enable register */
	unsigned long xfer_mode;/* data transfer mode register */
} sil_port[] = {
	/* port 0 ... */
	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	/* ... port 3 */
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
	u8 cache_line = 0;
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	return cache_line;
}

static void sil_post_set_mode (struct ata_port *ap)
{
	struct ata_host_set *host_set = ap->host_set;
	struct ata_device *dev;
	void __iomem *addr =
		host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	u32 tmp, dev_mode[2];
	unsigned int i;

	for (i = 0; i < 2; i++) {
		dev = &ap->device[i];
		if (!ata_dev_present(dev))
			dev_mode[i] = 0;	/* PIO0/1/2 */
		else if (dev->flags & ATA_DFLAG_PIO)
			dev_mode[i] = 1;	/* PIO3/4 */
		else
			dev_mode[i] = 3;	/* UDMA */
		/* value 2 indicates MDMA */
	}

	tmp = readl(addr);
	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
	tmp |= dev_mode[0];
	tmp |= (dev_mode[1] << 4);
	writel(tmp, addr);
	readl(addr);	/* flush */
}

static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
{
	unsigned long offset = ap->ioaddr.scr_addr;

	switch (sc_reg) {
	case SCR_STATUS:
		return offset + 4;
	case SCR_ERROR:
		return offset + 8;
	case SCR_CONTROL:
		return offset;
	default:
		/* do nothing */
		break;
	}

	return 0;
}

static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		return readl(mmio);
	return 0xffffffffU;
}

static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void *mmio = (void *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		writel(val, mmio);
}

/**
 *	sil_dev_config - Apply device/host-specific errata fixups
 *	@ap: Port containing device to be examined
 *	@dev: Device to be examined
 *
 *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
 *	device is known to be present, this function is called.
 *	We apply two errata fixups which are specific to Silicon Image,
 *	a Seagate and a Maxtor fixup.
 *
 *	For certain Seagate devices, we must limit the maximum sectors
 *	to under 8K.
 *
 *	For certain Maxtor devices, we must not program the drive
 *	beyond udma5.
 *
 *	Both fixups are unfairly pessimistic.  As soon as I get more
 *	information on these errata, I will create a more exhaustive
 *	list, and apply the fixups to only the specific
 *	devices/hosts/firmwares that need it.
 *
 *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 *	The Maxtor quirk is in the blacklist, but I'm keeping the original
 *	pessimistic fix for the following reasons...
 *	- There seems to be less info on it, only one device gleaned off the
 *	Windows	driver, maybe only one is affected.  More info would be greatly
 *	appreciated.
 *	- But then again UDMA5 is hardly anything to complain about
 */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
	unsigned int n, quirks = 0;
	unsigned char model_num[40];
	const char *s;
	unsigned int len;

	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
			  sizeof(model_num));
	s = &model_num[0];
	len = strnlen(s, sizeof(model_num));

	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	while ((len > 0) && (s[len - 1] == ' '))
		len--;

	for (n = 0; sil_blacklist[n].product; n++)
		if (!memcmp(sil_blacklist[n].product, s,
			    strlen(sil_blacklist[n].product))) {
			quirks = sil_blacklist[n].quirk;
			break;
		}

	/* limit requests to 15 sectors */
	if ((ap->flags & SIL_FLAG_MOD15WRITE) && (quirks & SIL_QUIRK_MOD15WRITE)) {
		printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
		       ap->id, dev->devno);
		ap->host->max_sectors = 15;
		ap->host->hostt->max_sectors = 15;
		dev->flags |= ATA_DFLAG_LOCK_SECTORS;
		return;
	}

	/* limit to udma5 */
	if (quirks & SIL_QUIRK_UDMA5MAX) {
		printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
		       ap->id, dev->devno, s);
		ap->udma_mask &= ATA_UDMA5;
		return;
	}
}

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int rc;
	unsigned int i;
	int pci_dev_busy = 0;
	u32 tmp, irq_mask;
	u8 cls;

	if (!printed_version++)
		printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	INIT_LIST_HEAD(&probe_ent->node);
	probe_ent->dev = pci_dev_to_dev(pdev);
	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
       	probe_ent->irq = pdev->irq;
       	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;

	mmio_base = ioremap(pci_resource_start(pdev, 5),
		            pci_resource_len(pdev, 5));
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}

	probe_ent->mmio_base = mmio_base;

	base = (unsigned long) mmio_base;

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
		probe_ent->port[i].altstatus_addr =
		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
		probe_ent->port[i].scr_addr = base + sil_port[i].scr;
		ata_std_ports(&probe_ent->port[i]);
	}

	/* Initialize FIFO PCI bus arbitration */
	cls = sil_get_device_cache_line(pdev);
	if (cls) {
		cls >>= 3;
		cls++;  /* cls = (line_size/8)+1 */
		writeb(cls, mmio_base + SIL_FIFO_R0);
		writeb(cls, mmio_base + SIL_FIFO_W0);
		writeb(cls, mmio_base + SIL_FIFO_R1);
		writeb(cls, mmio_base + SIL_FIFO_W1);
		if (ent->driver_data == sil_3114) {
			writeb(cls, mmio_base + SIL_FIFO_R2);
			writeb(cls, mmio_base + SIL_FIFO_W2);
			writeb(cls, mmio_base + SIL_FIFO_R3);
			writeb(cls, mmio_base + SIL_FIFO_W3);
		}
	} else
		printk(KERN_WARNING DRV_NAME "(%s): cache line size not set.  Driver may not function\n",
			pci_name(pdev));

	if (ent->driver_data == sil_3114) {
		irq_mask = SIL_MASK_4PORT;

		/* flip the magic "make 4 ports work" bit */
		tmp = readl(mmio_base + SIL_IDE2_BMDMA);
		if ((tmp & SIL_INTR_STEERING) == 0)
			writel(tmp | SIL_INTR_STEERING,
			       mmio_base + SIL_IDE2_BMDMA);

	} else {
		irq_mask = SIL_MASK_2PORT;
	}

	/* make sure IDE0/1/2/3 interrupts are not masked */
	tmp = readl(mmio_base + SIL_SYSCFG);
	if (tmp & irq_mask) {
		tmp &= ~irq_mask;
		writel(tmp, mmio_base + SIL_SYSCFG);
		readl(mmio_base + SIL_SYSCFG);	/* flush */
	}

	/* mask all SATA phy-related interrupts */
	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	for (i = 0; i < probe_ent->n_ports; i++)
		writel(0, mmio_base + sil_port[i].sien);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

static int __init sil_init(void)
{
	return pci_module_init(&sil_pci_driver);
}

static void __exit sil_exit(void)
{
	pci_unregister_driver(&sil_pci_driver);
}


module_init(sil_init);
module_exit(sil_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sil.c - Silicon Image SATA
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
af36d7f0	8	* Copyright 2003-2005 Red Hat, Inc.
1da177e4 LT	9	* Copyright 2003 Benjamin Herrenschmidt
1da177e4 LT	10	*
af36d7f0 JG	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
1da177e4	29	*
953d1137 JG	30	* Documentation for SiI 3112:
	31	* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
	32	*
	33	* Other errata and documentation available under NDA.
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
	44	#include "scsi.h"
	45	#include <scsi/scsi_host.h>
	46	#include <linux/libata.h>
	47
	48	#define DRV_NAME "sata_sil"
	49	#define DRV_VERSION "0.9"
	50
	51	enum {
e4deec63 TH	52	SIL_FLAG_MOD15WRITE = (1 << 30),
e4deec63 TH	53
1da177e4	54	sil_3112 = 0,
e4deec63 TH	55	sil_3112_m15w = 1,
e4deec63 TH	56	sil_3114 = 2,
1da177e4 LT	57
	58	SIL_FIFO_R0 = 0x40,
	59	SIL_FIFO_W0 = 0x41,
	60	SIL_FIFO_R1 = 0x44,
	61	SIL_FIFO_W1 = 0x45,
	62	SIL_FIFO_R2 = 0x240,
	63	SIL_FIFO_W2 = 0x241,
	64	SIL_FIFO_R3 = 0x244,
	65	SIL_FIFO_W3 = 0x245,
	66
	67	SIL_SYSCFG = 0x48,
	68	SIL_MASK_IDE0_INT = (1 << 22),
	69	SIL_MASK_IDE1_INT = (1 << 23),
	70	SIL_MASK_IDE2_INT = (1 << 24),
	71	SIL_MASK_IDE3_INT = (1 << 25),
	72	SIL_MASK_2PORT = SIL_MASK_IDE0_INT \| SIL_MASK_IDE1_INT,
	73	SIL_MASK_4PORT = SIL_MASK_2PORT \|
	74	SIL_MASK_IDE2_INT \| SIL_MASK_IDE3_INT,
	75
	76	SIL_IDE2_BMDMA = 0x200,
	77
	78	SIL_INTR_STEERING = (1 << 1),
	79	SIL_QUIRK_MOD15WRITE = (1 << 0),
	80	SIL_QUIRK_UDMA5MAX = (1 << 1),
	81	};
	82
	83	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	84	static void sil_dev_config(struct ata_port ap, struct ata_device dev);
	85	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
	86	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	87	static void sil_post_set_mode (struct ata_port *ap);
	88
	89	static struct pci_device_id sil_pci_tbl[] = {
e4deec63 TH	90	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
e4deec63 TH	91	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
1da177e4 LT	92	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
1da177e4 LT	93	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
e4deec63 TH	94	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	95	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
	96	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },
1da177e4 LT	97	{ } /* terminate list */
	98	};
	99
	100
	101	/* TODO firmware versions should be added - eric */
	102	static const struct sil_drivelist {
	103	const char * product;
	104	unsigned int quirk;
	105	} sil_blacklist [] = {
	106	{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
	107	{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
	108	{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
	109	{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
	110	{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
	111	{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
	112	{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
	113	{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
	114	{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
	115	{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
	116	{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
	117	{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
	118	{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
	119	{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
	120	{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
	121	{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
	122	{ }
	123	};
	124
	125	static struct pci_driver sil_pci_driver = {
	126	.name = DRV_NAME,
	127	.id_table = sil_pci_tbl,
	128	.probe = sil_init_one,
	129	.remove = ata_pci_remove_one,
	130	};
	131
	132	static Scsi_Host_Template sil_sht = {
	133	.module = THIS_MODULE,
	134	.name = DRV_NAME,
	135	.ioctl = ata_scsi_ioctl,
	136	.queuecommand = ata_scsi_queuecmd,
	137	.eh_strategy_handler = ata_scsi_error,
	138	.can_queue = ATA_DEF_QUEUE,
	139	.this_id = ATA_SHT_THIS_ID,
	140	.sg_tablesize = LIBATA_MAX_PRD,
	141	.max_sectors = ATA_MAX_SECTORS,
	142	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	143	.emulated = ATA_SHT_EMULATED,
	144	.use_clustering = ATA_SHT_USE_CLUSTERING,
	145	.proc_name = DRV_NAME,
	146	.dma_boundary = ATA_DMA_BOUNDARY,
	147	.slave_configure = ata_scsi_slave_config,
	148	.bios_param = ata_std_bios_param,
	149	.ordered_flush = 1,
	150	};
	151
	152	static struct ata_port_operations sil_ops = {
	153	.port_disable = ata_port_disable,
	154	.dev_config = sil_dev_config,
	155	.tf_load = ata_tf_load,
	156	.tf_read = ata_tf_read,
	157	.check_status = ata_check_status,
	158	.exec_command = ata_exec_command,
	159	.dev_select = ata_std_dev_select,
	160	.phy_reset = sata_phy_reset,
161	.post_set_mode = sil_post_set_mode,
162	.bmdma_setup = ata_bmdma_setup,
163	.bmdma_start = ata_bmdma_start,
164	.bmdma_stop = ata_bmdma_stop,
165	.bmdma_status = ata_bmdma_status,
166	.qc_prep = ata_qc_prep,
167	.qc_issue = ata_qc_issue_prot,
168	.eng_timeout = ata_eng_timeout,
169	.irq_handler = ata_interrupt,
170	.irq_clear = ata_bmdma_irq_clear,
171	.scr_read = sil_scr_read,
172	.scr_write = sil_scr_write,
173	.port_start = ata_port_start,
174	.port_stop = ata_port_stop,
aa8f0dc6	175	.host_stop = ata_host_stop,
1da177e4 LT	176	};
	177
	178	static struct ata_port_info sil_port_info[] = {
	179	/* sil_3112 */
	180	{
	181	.sht = &sil_sht,
	182	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	183	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	184	.pio_mask = 0x1f, /* pio0-4 */
	185	.mwdma_mask = 0x07, /* mwdma0-2 */
	186	.udma_mask = 0x3f, /* udma0-5 */
	187	.port_ops = &sil_ops,
e4deec63 TH	188	}, /* sil_3112_15w - keep it sync'd w/ sil_3112 */
	189	{
	190	.sht = &sil_sht,
	191	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	192	ATA_FLAG_SRST \| ATA_FLAG_MMIO \|
	193	SIL_FLAG_MOD15WRITE,
	194	.pio_mask = 0x1f, /* pio0-4 */
	195	.mwdma_mask = 0x07, /* mwdma0-2 */
	196	.udma_mask = 0x3f, /* udma0-5 */
	197	.port_ops = &sil_ops,
1da177e4 LT	198	}, /* sil_3114 */
	199	{
	200	.sht = &sil_sht,
	201	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
	202	ATA_FLAG_SRST \| ATA_FLAG_MMIO,
	203	.pio_mask = 0x1f, /* pio0-4 */
	204	.mwdma_mask = 0x07, /* mwdma0-2 */
	205	.udma_mask = 0x3f, /* udma0-5 */
	206	.port_ops = &sil_ops,
	207	},
	208	};
	209
	210	/* per-port register offsets */
	211	/* TODO: we can probably calculate rather than use a table */
	212	static const struct {
	213	unsigned long tf; /* ATA taskfile register block */
	214	unsigned long ctl; /* ATA control/altstatus register block */
	215	unsigned long bmdma; /* DMA register block */
	216	unsigned long scr; /* SATA control register block */
	217	unsigned long sien; /* SATA Interrupt Enable register */
	218	unsigned long xfer_mode;/* data transfer mode register */
	219	} sil_port[] = {
	220	/* port 0 ... */
	221	{ 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
	222	{ 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
	223	{ 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
	224	{ 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
	225	/* ... port 3 */
	226	};
	227
	228	MODULE_AUTHOR("Jeff Garzik");
	229	MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
	230	MODULE_LICENSE("GPL");
	231	MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
	232	MODULE_VERSION(DRV_VERSION);
	233
	234	static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
	235	{
	236	u8 cache_line = 0;
	237	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	238	return cache_line;
	239	}
	240
	241	static void sil_post_set_mode (struct ata_port *ap)
	242	{
	243	struct ata_host_set *host_set = ap->host_set;
	244	struct ata_device *dev;
ea6ba10b JG	245	void __iomem *addr =
ea6ba10b JG	246	host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
1da177e4 LT	247	u32 tmp, dev_mode[2];
	248	unsigned int i;
	249
	250	for (i = 0; i < 2; i++) {
	251	dev = &ap->device[i];
	252	if (!ata_dev_present(dev))
	253	dev_mode[i] = 0; /* PIO0/1/2 */
	254	else if (dev->flags & ATA_DFLAG_PIO)
	255	dev_mode[i] = 1; /* PIO3/4 */
	256	else
	257	dev_mode[i] = 3; /* UDMA */
	258	/* value 2 indicates MDMA */
	259	}
	260
	261	tmp = readl(addr);
	262	tmp &= ~((1<<5) \| (1<<4) \| (1<<1) \| (1<<0));
	263	tmp \|= dev_mode[0];
	264	tmp \|= (dev_mode[1] << 4);
	265	writel(tmp, addr);
	266	readl(addr); /* flush */
	267	}
	268
	269	static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
	270	{
	271	unsigned long offset = ap->ioaddr.scr_addr;
	272
	273	switch (sc_reg) {
	274	case SCR_STATUS:
	275	return offset + 4;
	276	case SCR_ERROR:
	277	return offset + 8;
	278	case SCR_CONTROL:
	279	return offset;
	280	default:
	281	/* do nothing */
	282	break;
	283	}
	284
	285	return 0;
	286	}
	287
	288	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
	289	{
	290	void mmio = (void ) sil_scr_addr(ap, sc_reg);
	291	if (mmio)
	292	return readl(mmio);
	293	return 0xffffffffU;
	294	}
	295
	296	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	297	{
	298	void mmio = (void ) sil_scr_addr(ap, sc_reg);
	299	if (mmio)
	300	writel(val, mmio);
	301	}
	302
	303	/**
	304	* sil_dev_config - Apply device/host-specific errata fixups
	305	* @ap: Port containing device to be examined
	306	* @dev: Device to be examined
	307	*
	308	* After the IDENTIFY [PACKET] DEVICE step is complete, and a
	309	* device is known to be present, this function is called.
	310	* We apply two errata fixups which are specific to Silicon Image,
311	* a Seagate and a Maxtor fixup.
312	*
313	* For certain Seagate devices, we must limit the maximum sectors
314	* to under 8K.
315	*
316	* For certain Maxtor devices, we must not program the drive
317	* beyond udma5.
318	*
319	* Both fixups are unfairly pessimistic. As soon as I get more
320	* information on these errata, I will create a more exhaustive
321	* list, and apply the fixups to only the specific
322	* devices/hosts/firmwares that need it.
323	*
324	* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
325	* The Maxtor quirk is in the blacklist, but I'm keeping the original
326	* pessimistic fix for the following reasons...
327	* - There seems to be less info on it, only one device gleaned off the
328	* Windows driver, maybe only one is affected. More info would be greatly
329	* appreciated.
330	* - But then again UDMA5 is hardly anything to complain about
331	*/
332	static void sil_dev_config(struct ata_port ap, struct ata_device dev)
333	{
334	unsigned int n, quirks = 0;
335	unsigned char model_num[40];
336	const char *s;
337	unsigned int len;
338
339	ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
340	sizeof(model_num));
341	s = &model_num[0];
342	len = strnlen(s, sizeof(model_num));
343
344	/* ATAPI specifies that empty space is blank-filled; remove blanks */
345	while ((len > 0) && (s[len - 1] == ' '))
346	len--;
347
8a60a071	348	for (n = 0; sil_blacklist[n].product; n++)
1da177e4 LT	349	if (!memcmp(sil_blacklist[n].product, s,
	350	strlen(sil_blacklist[n].product))) {
	351	quirks = sil_blacklist[n].quirk;
	352	break;
	353	}
8a60a071	354
1da177e4	355	/* limit requests to 15 sectors */
e4deec63	356	if ((ap->flags & SIL_FLAG_MOD15WRITE) && (quirks & SIL_QUIRK_MOD15WRITE)) {
1da177e4 LT	357	printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",
	358	ap->id, dev->devno);
	359	ap->host->max_sectors = 15;
	360	ap->host->hostt->max_sectors = 15;
	361	dev->flags \|= ATA_DFLAG_LOCK_SECTORS;
	362	return;
	363	}
	364
	365	/* limit to udma5 */
	366	if (quirks & SIL_QUIRK_UDMA5MAX) {
	367	printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
	368	ap->id, dev->devno, s);
	369	ap->udma_mask &= ATA_UDMA5;
	370	return;
	371	}
	372	}
	373
	374	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	375	{
	376	static int printed_version;
	377	struct ata_probe_ent *probe_ent = NULL;
	378	unsigned long base;
ea6ba10b	379	void __iomem *mmio_base;
1da177e4 LT	380	int rc;
	381	unsigned int i;
	382	int pci_dev_busy = 0;
	383	u32 tmp, irq_mask;
	384	u8 cls;
	385
	386	if (!printed_version++)
	387	printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
	388
	389	/*
	390	* If this driver happens to only be useful on Apple's K2, then
	391	* we should check that here as it has a normal Serverworks ID
	392	*/
	393	rc = pci_enable_device(pdev);
	394	if (rc)
	395	return rc;
	396
	397	rc = pci_request_regions(pdev, DRV_NAME);
	398	if (rc) {
	399	pci_dev_busy = 1;
	400	goto err_out;
	401	}
	402
	403	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	404	if (rc)
	405	goto err_out_regions;
	406	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	407	if (rc)
	408	goto err_out_regions;
	409
	410	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	411	if (probe_ent == NULL) {
	412	rc = -ENOMEM;
	413	goto err_out_regions;
	414	}
	415
	416	memset(probe_ent, 0, sizeof(*probe_ent));
	417	INIT_LIST_HEAD(&probe_ent->node);
	418	probe_ent->dev = pci_dev_to_dev(pdev);
	419	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	420	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	421	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	422	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	423	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	424	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
	425	probe_ent->irq = pdev->irq;
	426	probe_ent->irq_flags = SA_SHIRQ;
	427	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
	428
	429	mmio_base = ioremap(pci_resource_start(pdev, 5),
	430	pci_resource_len(pdev, 5));
	431	if (mmio_base == NULL) {
	432	rc = -ENOMEM;
	433	goto err_out_free_ent;
	434	}
	435
	436	probe_ent->mmio_base = mmio_base;
	437
	438	base = (unsigned long) mmio_base;
	439
	440	for (i = 0; i < probe_ent->n_ports; i++) {
	441	probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
	442	probe_ent->port[i].altstatus_addr =
	443	probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
444	probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
445	probe_ent->port[i].scr_addr = base + sil_port[i].scr;
446	ata_std_ports(&probe_ent->port[i]);
447	}
448
449	/* Initialize FIFO PCI bus arbitration */
450	cls = sil_get_device_cache_line(pdev);
451	if (cls) {
452	cls >>= 3;
453	cls++; /* cls = (line_size/8)+1 */
454	writeb(cls, mmio_base + SIL_FIFO_R0);
455	writeb(cls, mmio_base + SIL_FIFO_W0);
456	writeb(cls, mmio_base + SIL_FIFO_R1);
e1dd23a0 JA	457	writeb(cls, mmio_base + SIL_FIFO_W1);
	458	if (ent->driver_data == sil_3114) {
	459	writeb(cls, mmio_base + SIL_FIFO_R2);
	460	writeb(cls, mmio_base + SIL_FIFO_W2);
	461	writeb(cls, mmio_base + SIL_FIFO_R3);
	462	writeb(cls, mmio_base + SIL_FIFO_W3);
	463	}
1da177e4 LT	464	} else
	465	printk(KERN_WARNING DRV_NAME "(%s): cache line size not set. Driver may not function\n",
	466	pci_name(pdev));
	467
	468	if (ent->driver_data == sil_3114) {
	469	irq_mask = SIL_MASK_4PORT;
	470
	471	/* flip the magic "make 4 ports work" bit */
	472	tmp = readl(mmio_base + SIL_IDE2_BMDMA);
	473	if ((tmp & SIL_INTR_STEERING) == 0)
	474	writel(tmp \| SIL_INTR_STEERING,
	475	mmio_base + SIL_IDE2_BMDMA);
	476
	477	} else {
	478	irq_mask = SIL_MASK_2PORT;
	479	}
	480
	481	/* make sure IDE0/1/2/3 interrupts are not masked */
	482	tmp = readl(mmio_base + SIL_SYSCFG);
	483	if (tmp & irq_mask) {
	484	tmp &= ~irq_mask;
	485	writel(tmp, mmio_base + SIL_SYSCFG);
	486	readl(mmio_base + SIL_SYSCFG); /* flush */
	487	}
	488
	489	/* mask all SATA phy-related interrupts */
	490	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	491	for (i = 0; i < probe_ent->n_ports; i++)
	492	writel(0, mmio_base + sil_port[i].sien);
	493
	494	pci_set_master(pdev);
	495
	496	/* FIXME: check ata_device_add return value */
	497	ata_device_add(probe_ent);
	498	kfree(probe_ent);
	499
	500	return 0;
	501
	502	err_out_free_ent:
	503	kfree(probe_ent);
	504	err_out_regions:
	505	pci_release_regions(pdev);
	506	err_out:
	507	if (!pci_dev_busy)
	508	pci_disable_device(pdev);
	509	return rc;
	510	}
	511
	512	static int __init sil_init(void)
	513	{
	514	return pci_module_init(&sil_pci_driver);
	515	}
	516
	517	static void __exit sil_exit(void)
	518	{
	519	pci_unregister_driver(&sil_pci_driver);
	520	}
	521
	522
	523	module_init(sil_init);
	524	module_exit(sil_exit);