[people/ms/u-boot.git] / drivers / serial / altera_uart.c

/*
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <serial.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* status register */
#define ALTERA_UART_TMT		BIT(5)	/* tx empty */
#define ALTERA_UART_TRDY	BIT(6)	/* tx ready */
#define ALTERA_UART_RRDY	BIT(7)	/* rx ready */

struct altera_uart_regs {
	u32	rxdata;		/* Rx data reg */
	u32	txdata;		/* Tx data reg */
	u32	status;		/* Status reg */
	u32	control;	/* Control reg */
	u32	divisor;	/* Baud rate divisor reg */
	u32	endofpacket;	/* End-of-packet reg */
};

struct altera_uart_platdata {
	struct altera_uart_regs *regs;
	unsigned int uartclk;
};

static int altera_uart_setbrg(struct udevice *dev, int baudrate)
{
	struct altera_uart_platdata *plat = dev->platdata;
	struct altera_uart_regs *const regs = plat->regs;
	u32 div;

	div = (plat->uartclk / baudrate) - 1;
	writel(div, &regs->divisor);

	return 0;
}

static int altera_uart_putc(struct udevice *dev, const char ch)
{
	struct altera_uart_platdata *plat = dev->platdata;
	struct altera_uart_regs *const regs = plat->regs;

	if (!(readl(&regs->status) & ALTERA_UART_TRDY))
		return -EAGAIN;

	writel(ch, &regs->txdata);

	return 0;
}

static int altera_uart_pending(struct udevice *dev, bool input)
{
	struct altera_uart_platdata *plat = dev->platdata;
	struct altera_uart_regs *const regs = plat->regs;
	u32 st = readl(&regs->status);

	if (input)
		return st & ALTERA_UART_RRDY ? 1 : 0;
	else
		return !(st & ALTERA_UART_TMT);
}

static int altera_uart_getc(struct udevice *dev)
{
	struct altera_uart_platdata *plat = dev->platdata;
	struct altera_uart_regs *const regs = plat->regs;

	if (!(readl(&regs->status) & ALTERA_UART_RRDY))
		return -EAGAIN;

	return readl(&regs->rxdata) & 0xff;
}

static int altera_uart_probe(struct udevice *dev)
{
	return 0;
}

static int altera_uart_ofdata_to_platdata(struct udevice *dev)
{
	struct altera_uart_platdata *plat = dev_get_platdata(dev);

	plat->regs = map_physmem(devfdt_get_addr(dev),
				 sizeof(struct altera_uart_regs),
				 MAP_NOCACHE);
	plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
		"clock-frequency", 0);

	return 0;
}

static const struct dm_serial_ops altera_uart_ops = {
	.putc = altera_uart_putc,
	.pending = altera_uart_pending,
	.getc = altera_uart_getc,
	.setbrg = altera_uart_setbrg,
};

static const struct udevice_id altera_uart_ids[] = {
	{ .compatible = "altr,uart-1.0" },
	{}
};

U_BOOT_DRIVER(altera_uart) = {
	.name	= "altera_uart",
	.id	= UCLASS_SERIAL,
	.of_match = altera_uart_ids,
	.ofdata_to_platdata = altera_uart_ofdata_to_platdata,
	.platdata_auto_alloc_size = sizeof(struct altera_uart_platdata),
	.probe = altera_uart_probe,
	.ops	= &altera_uart_ops,
	.flags = DM_FLAG_PRE_RELOC,
};

#ifdef CONFIG_DEBUG_UART_ALTERA_UART

#include <debug_uart.h>

static inline void _debug_uart_init(void)
{
	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;
	u32 div;

	div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
	writel(div, &regs->divisor);
}

static inline void _debug_uart_putc(int ch)
{
	struct altera_uart_regs *regs = (void *)CONFIG_DEBUG_UART_BASE;

	while (1) {
		u32 st = readl(&regs->status);

		if (st & ALTERA_UART_TRDY)
			break;
	}

	writel(ch, &regs->txdata);
}

DEBUG_UART_FUNCS

#endif
Commit	Line	Data
c9d4f46b SM	1	/*
	2	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	3	* Scott McNutt <smcnutt@psyent.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c9d4f46b SM	6	*/
c9d4f46b SM	7
c9d4f46b	8	#include <common.h>
da2f838d TC	9	#include <dm.h>
da2f838d TC	10	#include <errno.h>
b207d645	11	#include <serial.h>
89241482 TC	12	#include <asm/io.h>
	13
	14	DECLARE_GLOBAL_DATA_PTR;
	15
	16	/* status register */
	17	#define ALTERA_UART_TMT BIT(5) /* tx empty */
	18	#define ALTERA_UART_TRDY BIT(6) /* tx ready */
	19	#define ALTERA_UART_RRDY BIT(7) /* rx ready */
c9d4f46b	20
da2f838d TC	21	struct altera_uart_regs {
	22	u32 rxdata; /* Rx data reg */
	23	u32 txdata; /* Tx data reg */
	24	u32 status; /* Status reg */
	25	u32 control; /* Control reg */
	26	u32 divisor; /* Baud rate divisor reg */
	27	u32 endofpacket; /* End-of-packet reg */
	28	};
	29
	30	struct altera_uart_platdata {
	31	struct altera_uart_regs *regs;
	32	unsigned int uartclk;
	33	};
86450710	34
da2f838d TC	35	static int altera_uart_setbrg(struct udevice *dev, int baudrate)
	36	{
	37	struct altera_uart_platdata *plat = dev->platdata;
	38	struct altera_uart_regs *const regs = plat->regs;
	39	u32 div;
c9d4f46b	40
da2f838d TC	41	div = (plat->uartclk / baudrate) - 1;
da2f838d TC	42	writel(div, &regs->divisor);
c9d4f46b	43
da2f838d	44	return 0;
b207d645 MV	45	}
b207d645 MV	46
da2f838d	47	static int altera_uart_putc(struct udevice *dev, const char ch)
b207d645	48	{
da2f838d TC	49	struct altera_uart_platdata *plat = dev->platdata;
da2f838d TC	50	struct altera_uart_regs *const regs = plat->regs;
c9d4f46b	51
da2f838d TC	52	if (!(readl(&regs->status) & ALTERA_UART_TRDY))
da2f838d TC	53	return -EAGAIN;
c9d4f46b	54
da2f838d	55	writel(ch, &regs->txdata);
c9d4f46b	56
da2f838d	57	return 0;
c9d4f46b SM	58	}
c9d4f46b SM	59
da2f838d	60	static int altera_uart_pending(struct udevice *dev, bool input)
c9d4f46b	61	{
da2f838d TC	62	struct altera_uart_platdata *plat = dev->platdata;
	63	struct altera_uart_regs *const regs = plat->regs;
	64	u32 st = readl(&regs->status);
	65
	66	if (input)
	67	return st & ALTERA_UART_RRDY ? 1 : 0;
	68	else
	69	return !(st & ALTERA_UART_TMT);
c9d4f46b SM	70	}
c9d4f46b SM	71
da2f838d	72	static int altera_uart_getc(struct udevice *dev)
c9d4f46b	73	{
da2f838d TC	74	struct altera_uart_platdata *plat = dev->platdata;
	75	struct altera_uart_regs *const regs = plat->regs;
	76
	77	if (!(readl(&regs->status) & ALTERA_UART_RRDY))
	78	return -EAGAIN;
	79
	80	return readl(&regs->rxdata) & 0xff;
c9d4f46b SM	81	}
c9d4f46b SM	82
da2f838d	83	static int altera_uart_probe(struct udevice *dev)
c9d4f46b	84	{
da2f838d	85	return 0;
c9d4f46b SM	86	}
c9d4f46b SM	87
da2f838d	88	static int altera_uart_ofdata_to_platdata(struct udevice *dev)
c9d4f46b	89	{
da2f838d TC	90	struct altera_uart_platdata *plat = dev_get_platdata(dev);
da2f838d TC	91
a821c4af	92	plat->regs = map_physmem(devfdt_get_addr(dev),
1ec60b93 TC	93	sizeof(struct altera_uart_regs),
1ec60b93 TC	94	MAP_NOCACHE);
e160f7d4	95	plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
da2f838d TC	96	"clock-frequency", 0);
	97
	98	return 0;
c9d4f46b	99	}
b207d645	100
da2f838d TC	101	static const struct dm_serial_ops altera_uart_ops = {
	102	.putc = altera_uart_putc,
	103	.pending = altera_uart_pending,
	104	.getc = altera_uart_getc,
	105	.setbrg = altera_uart_setbrg,
	106	};
	107
	108	static const struct udevice_id altera_uart_ids[] = {
89241482 TC	109	{ .compatible = "altr,uart-1.0" },
89241482 TC	110	{}
da2f838d TC	111	};
	112
	113	U_BOOT_DRIVER(altera_uart) = {
	114	.name = "altera_uart",
	115	.id = UCLASS_SERIAL,
	116	.of_match = altera_uart_ids,
	117	.ofdata_to_platdata = altera_uart_ofdata_to_platdata,
	118	.platdata_auto_alloc_size = sizeof(struct altera_uart_platdata),
	119	.probe = altera_uart_probe,
	120	.ops = &altera_uart_ops,
	121	.flags = DM_FLAG_PRE_RELOC,
b207d645 MV	122	};
b207d645 MV	123
da2f838d TC	124	#ifdef CONFIG_DEBUG_UART_ALTERA_UART
	125
	126	#include <debug_uart.h>
	127
e03c17d0	128	static inline void _debug_uart_init(void)
b207d645	129	{
da2f838d TC	130	struct altera_uart_regs regs = (void )CONFIG_DEBUG_UART_BASE;
	131	u32 div;
	132
	133	div = (CONFIG_DEBUG_UART_CLOCK / CONFIG_BAUDRATE) - 1;
	134	writel(div, &regs->divisor);
b207d645 MV	135	}
b207d645 MV	136
da2f838d	137	static inline void _debug_uart_putc(int ch)
b207d645	138	{
da2f838d TC	139	struct altera_uart_regs regs = (void )CONFIG_DEBUG_UART_BASE;
	140
	141	while (1) {
	142	u32 st = readl(&regs->status);
	143
	144	if (st & ALTERA_UART_TRDY)
	145	break;
	146	}
	147
	148	writel(ch, &regs->txdata);
b207d645	149	}
da2f838d TC	150
	151	DEBUG_UART_FUNCS
	152
	153	#endif