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4f572898 JCPV |
1 | /* |
2 | * Copyright (C) 2004-2007 ARM Limited. | |
3 | * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
966bfa73 | 4 | * Copyright (C) 2015 - 2016 Xilinx, Inc, Michal Simek |
4f572898 | 5 | * |
5b8031cc | 6 | * SPDX-License-Identifier: GPL-2.0 |
4f572898 JCPV |
7 | * |
8 | * As a special exception, if other files instantiate templates or use macros | |
9 | * or inline functions from this file, or you compile this file and link it | |
10 | * with other works to produce a work based on this file, this file does not | |
11 | * by itself cause the resulting work to be covered by the GNU General Public | |
12 | * License. However the source code for this file must still be made available | |
13 | * in accordance with section (3) of the GNU General Public License. | |
14 | ||
15 | * This exception does not invalidate any other reasons why a work based on | |
16 | * this file might be covered by the GNU General Public License. | |
17 | */ | |
18 | ||
19 | #include <common.h> | |
966bfa73 | 20 | #include <dm.h> |
a168d3af | 21 | #include <serial.h> |
4f572898 | 22 | |
fd602c56 | 23 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7) |
4f572898 | 24 | /* |
fd602c56 | 25 | * ARMV6 & ARMV7 |
4f572898 | 26 | */ |
66e8f9da JCPV |
27 | #define DCC_RBIT (1 << 30) |
28 | #define DCC_WBIT (1 << 29) | |
4f572898 | 29 | |
66e8f9da JCPV |
30 | #define write_dcc(x) \ |
31 | __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) | |
4f572898 | 32 | |
66e8f9da JCPV |
33 | #define read_dcc(x) \ |
34 | __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) | |
4f572898 | 35 | |
66e8f9da JCPV |
36 | #define status_dcc(x) \ |
37 | __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) | |
4f572898 | 38 | |
65a76d4f JCPV |
39 | #elif defined(CONFIG_CPU_XSCALE) |
40 | /* | |
41 | * XSCALE | |
42 | */ | |
43 | #define DCC_RBIT (1 << 31) | |
44 | #define DCC_WBIT (1 << 28) | |
45 | ||
46 | #define write_dcc(x) \ | |
47 | __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x)) | |
48 | ||
49 | #define read_dcc(x) \ | |
50 | __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x)) | |
51 | ||
52 | #define status_dcc(x) \ | |
53 | __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) | |
54 | ||
e05412f5 SDPP |
55 | #elif defined(CONFIG_CPU_ARMV8) |
56 | /* | |
57 | * ARMV8 | |
58 | */ | |
59 | #define DCC_RBIT (1 << 30) | |
60 | #define DCC_WBIT (1 << 29) | |
61 | ||
62 | #define write_dcc(x) \ | |
63 | __asm__ volatile ("msr dbgdtrtx_el0, %0\n" : : "r" (x)) | |
64 | ||
65 | #define read_dcc(x) \ | |
66 | __asm__ volatile ("mrs %0, dbgdtrrx_el0\n" : "=r" (x)) | |
67 | ||
68 | #define status_dcc(x) \ | |
69 | __asm__ volatile ("mrs %0, mdccsr_el0\n" : "=r" (x)) | |
70 | ||
66e8f9da JCPV |
71 | #else |
72 | #define DCC_RBIT (1 << 0) | |
73 | #define DCC_WBIT (1 << 1) | |
4f572898 | 74 | |
66e8f9da JCPV |
75 | #define write_dcc(x) \ |
76 | __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) | |
4f572898 | 77 | |
66e8f9da JCPV |
78 | #define read_dcc(x) \ |
79 | __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) | |
4f572898 | 80 | |
66e8f9da JCPV |
81 | #define status_dcc(x) \ |
82 | __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) | |
83 | ||
84 | #endif | |
4f572898 | 85 | |
66e8f9da JCPV |
86 | #define can_read_dcc(x) do { \ |
87 | status_dcc(x); \ | |
88 | x &= DCC_RBIT; \ | |
4f572898 JCPV |
89 | } while (0); |
90 | ||
66e8f9da JCPV |
91 | #define can_write_dcc(x) do { \ |
92 | status_dcc(x); \ | |
93 | x &= DCC_WBIT; \ | |
94 | x = (x == 0); \ | |
4f572898 JCPV |
95 | } while (0); |
96 | ||
97 | #define TIMEOUT_COUNT 0x4000000 | |
98 | ||
966bfa73 | 99 | static int arm_dcc_getc(struct udevice *dev) |
4f572898 JCPV |
100 | { |
101 | int ch; | |
102 | register unsigned int reg; | |
103 | ||
66e8f9da JCPV |
104 | do { |
105 | can_read_dcc(reg); | |
106 | } while (!reg); | |
107 | read_dcc(ch); | |
4f572898 JCPV |
108 | |
109 | return ch; | |
110 | } | |
111 | ||
966bfa73 | 112 | static int arm_dcc_putc(struct udevice *dev, char ch) |
4f572898 JCPV |
113 | { |
114 | register unsigned int reg; | |
115 | unsigned int timeout_count = TIMEOUT_COUNT; | |
116 | ||
66e8f9da JCPV |
117 | while (--timeout_count) { |
118 | can_write_dcc(reg); | |
119 | if (reg) | |
120 | break; | |
4f572898 | 121 | } |
66e8f9da | 122 | if (timeout_count == 0) |
966bfa73 | 123 | return -EAGAIN; |
66e8f9da JCPV |
124 | else |
125 | write_dcc(ch); | |
966bfa73 MS |
126 | |
127 | return 0; | |
4f572898 JCPV |
128 | } |
129 | ||
966bfa73 | 130 | static int arm_dcc_pending(struct udevice *dev, bool input) |
4f572898 JCPV |
131 | { |
132 | register unsigned int reg; | |
133 | ||
966bfa73 MS |
134 | if (input) { |
135 | can_read_dcc(reg); | |
136 | } else { | |
137 | can_write_dcc(reg); | |
138 | } | |
4f572898 JCPV |
139 | |
140 | return reg; | |
141 | } | |
142 | ||
966bfa73 MS |
143 | static const struct dm_serial_ops arm_dcc_ops = { |
144 | .putc = arm_dcc_putc, | |
145 | .pending = arm_dcc_pending, | |
146 | .getc = arm_dcc_getc, | |
147 | }; | |
148 | ||
149 | static const struct udevice_id arm_dcc_ids[] = { | |
150 | { .compatible = "arm,dcc", }, | |
151 | { } | |
152 | }; | |
a168d3af | 153 | |
966bfa73 | 154 | U_BOOT_DRIVER(serial_dcc) = { |
a168d3af | 155 | .name = "arm_dcc", |
966bfa73 MS |
156 | .id = UCLASS_SERIAL, |
157 | .of_match = arm_dcc_ids, | |
158 | .ops = &arm_dcc_ops, | |
159 | .flags = DM_FLAG_PRE_RELOC, | |
a168d3af JT |
160 | }; |
161 | ||
966bfa73 MS |
162 | #ifdef CONFIG_DEBUG_UART_ARM_DCC |
163 | ||
164 | #include <debug_uart.h> | |
165 | ||
166 | static inline void _debug_uart_init(void) | |
a168d3af | 167 | { |
a168d3af JT |
168 | } |
169 | ||
966bfa73 | 170 | static inline void _debug_uart_putc(int ch) |
e70fb539 | 171 | { |
966bfa73 | 172 | arm_dcc_putc(NULL, ch); |
e70fb539 | 173 | } |
966bfa73 MS |
174 | |
175 | DEBUG_UART_FUNCS | |
176 | #endif |