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4f572898 JCPV |
1 | /* |
2 | * Copyright (C) 2004-2007 ARM Limited. | |
3 | * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | * | |
18 | * As a special exception, if other files instantiate templates or use macros | |
19 | * or inline functions from this file, or you compile this file and link it | |
20 | * with other works to produce a work based on this file, this file does not | |
21 | * by itself cause the resulting work to be covered by the GNU General Public | |
22 | * License. However the source code for this file must still be made available | |
23 | * in accordance with section (3) of the GNU General Public License. | |
24 | ||
25 | * This exception does not invalidate any other reasons why a work based on | |
26 | * this file might be covered by the GNU General Public License. | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
a168d3af | 30 | #include <serial.h> |
4f572898 | 31 | |
66e8f9da | 32 | #if defined(CONFIG_CPU_V6) |
4f572898 | 33 | /* |
66e8f9da | 34 | * ARMV6 |
4f572898 | 35 | */ |
66e8f9da JCPV |
36 | #define DCC_RBIT (1 << 30) |
37 | #define DCC_WBIT (1 << 29) | |
4f572898 | 38 | |
66e8f9da JCPV |
39 | #define write_dcc(x) \ |
40 | __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) | |
4f572898 | 41 | |
66e8f9da JCPV |
42 | #define read_dcc(x) \ |
43 | __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) | |
4f572898 | 44 | |
66e8f9da JCPV |
45 | #define status_dcc(x) \ |
46 | __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) | |
4f572898 | 47 | |
65a76d4f JCPV |
48 | #elif defined(CONFIG_CPU_XSCALE) |
49 | /* | |
50 | * XSCALE | |
51 | */ | |
52 | #define DCC_RBIT (1 << 31) | |
53 | #define DCC_WBIT (1 << 28) | |
54 | ||
55 | #define write_dcc(x) \ | |
56 | __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x)) | |
57 | ||
58 | #define read_dcc(x) \ | |
59 | __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x)) | |
60 | ||
61 | #define status_dcc(x) \ | |
62 | __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x)) | |
63 | ||
66e8f9da JCPV |
64 | #else |
65 | #define DCC_RBIT (1 << 0) | |
66 | #define DCC_WBIT (1 << 1) | |
4f572898 | 67 | |
66e8f9da JCPV |
68 | #define write_dcc(x) \ |
69 | __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) | |
4f572898 | 70 | |
66e8f9da JCPV |
71 | #define read_dcc(x) \ |
72 | __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) | |
4f572898 | 73 | |
66e8f9da JCPV |
74 | #define status_dcc(x) \ |
75 | __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) | |
76 | ||
77 | #endif | |
4f572898 | 78 | |
66e8f9da JCPV |
79 | #define can_read_dcc(x) do { \ |
80 | status_dcc(x); \ | |
81 | x &= DCC_RBIT; \ | |
4f572898 JCPV |
82 | } while (0); |
83 | ||
66e8f9da JCPV |
84 | #define can_write_dcc(x) do { \ |
85 | status_dcc(x); \ | |
86 | x &= DCC_WBIT; \ | |
87 | x = (x == 0); \ | |
4f572898 JCPV |
88 | } while (0); |
89 | ||
90 | #define TIMEOUT_COUNT 0x4000000 | |
91 | ||
a168d3af | 92 | static int arm_dcc_init(void) |
4f572898 | 93 | { |
4f572898 JCPV |
94 | return 0; |
95 | } | |
96 | ||
a168d3af | 97 | static int arm_dcc_getc(void) |
4f572898 JCPV |
98 | { |
99 | int ch; | |
100 | register unsigned int reg; | |
101 | ||
66e8f9da JCPV |
102 | do { |
103 | can_read_dcc(reg); | |
104 | } while (!reg); | |
105 | read_dcc(ch); | |
4f572898 JCPV |
106 | |
107 | return ch; | |
108 | } | |
109 | ||
a168d3af | 110 | static void arm_dcc_putc(char ch) |
4f572898 JCPV |
111 | { |
112 | register unsigned int reg; | |
113 | unsigned int timeout_count = TIMEOUT_COUNT; | |
114 | ||
66e8f9da JCPV |
115 | while (--timeout_count) { |
116 | can_write_dcc(reg); | |
117 | if (reg) | |
118 | break; | |
4f572898 | 119 | } |
66e8f9da JCPV |
120 | if (timeout_count == 0) |
121 | return; | |
122 | else | |
123 | write_dcc(ch); | |
4f572898 JCPV |
124 | } |
125 | ||
a168d3af | 126 | static int arm_dcc_tstc(void) |
4f572898 JCPV |
127 | { |
128 | register unsigned int reg; | |
129 | ||
66e8f9da | 130 | can_read_dcc(reg); |
4f572898 JCPV |
131 | |
132 | return reg; | |
133 | } | |
134 | ||
a168d3af JT |
135 | static void arm_dcc_setbrg(void) |
136 | { | |
137 | } | |
138 | ||
139 | static struct serial_device arm_dcc_drv = { | |
140 | .name = "arm_dcc", | |
141 | .start = arm_dcc_init, | |
142 | .stop = NULL, | |
143 | .setbrg = arm_dcc_setbrg, | |
144 | .putc = arm_dcc_putc, | |
012a2c15 | 145 | .puts = default_serial_puts, |
a168d3af JT |
146 | .getc = arm_dcc_getc, |
147 | .tstc = arm_dcc_tstc, | |
148 | }; | |
149 | ||
150 | void arm_dcc_initialize(void) | |
151 | { | |
152 | serial_register(&arm_dcc_drv); | |
153 | } | |
154 | ||
e70fb539 MS |
155 | __weak struct serial_device *default_serial_console(void) |
156 | { | |
a168d3af | 157 | return &arm_dcc_drv; |
e70fb539 | 158 | } |