projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f93ae788 WD |
1 | /* |
| 2 | * Copyright (C) 2004-2006 Atmel Corporation | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License as published by | |
| 6 | * the Free Software Foundation; either version 2 of the License, or | |
| 7 | * (at your option) any later version. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License | |
| 15 | * along with this program; if not, write to the Free Software | |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 17 | */ | |
| 18 | #include <common.h> | |
| 0cf0b931 JS |
19 | #ifndef CONFIG_AT91_LEGACY |
| 20 | #define CONFIG_AT91_LEGACY | |
| 21 | #warning Please update to use C structur SoC access ! | |
| 22 | #endif | |
| 843a2654 | 23 | #include <watchdog.h> |
| f93ae788 | 24 | |
| f93ae788 | 25 | #include <asm/io.h> |
| df548d3c HS |
26 | #include <asm/arch/clk.h> |
| 27 | #include <asm/arch/memory-map.h> | |
| 28 | ||
| 29 | #if defined(CONFIG_USART0) | |
| 30 | # define USART_ID 0 | |
| 31 | # define USART_BASE USART0_BASE | |
| 32 | #elif defined(CONFIG_USART1) | |
| 33 | # define USART_ID 1 | |
| 34 | # define USART_BASE USART1_BASE | |
| 35 | #elif defined(CONFIG_USART2) | |
| 36 | # define USART_ID 2 | |
| 37 | # define USART_BASE USART2_BASE | |
| 38 | #elif defined(CONFIG_USART3) | |
| 39 | # define USART_ID 3 | |
| 40 | # define USART_BASE USART3_BASE | |
| 41 | #endif | |
| f93ae788 WD |
42 | |
| 43 | #include "atmel_usart.h" | |
| 44 | ||
| 45 | DECLARE_GLOBAL_DATA_PTR; | |
| 46 | ||
| 47 | void serial_setbrg(void) | |
| 48 | { | |
| 49 | unsigned long divisor; | |
| 50 | unsigned long usart_hz; | |
| 51 | ||
| 52 | /* | |
| 53 | * Master Clock | |
| 54 | * Baud Rate = -------------- | |
| 55 | * 16 * CD | |
| 56 | */ | |
| df548d3c | 57 | usart_hz = get_usart_clk_rate(USART_ID); |
| f93ae788 | 58 | divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate; |
| df548d3c | 59 | usart3_writel(BRGR, USART3_BF(CD, divisor)); |
| f93ae788 WD |
60 | } |
| 61 | ||
| 62 | int serial_init(void) | |
| 63 | { | |
| df548d3c | 64 | usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX)); |
| f93ae788 WD |
65 | |
| 66 | serial_setbrg(); | |
| 67 | ||
| df548d3c HS |
68 | usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN)); |
| 69 | usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) | |
| 70 | | USART3_BF(USCLKS, USART3_USCLKS_MCK) | |
| 71 | | USART3_BF(CHRL, USART3_CHRL_8) | |
| 72 | | USART3_BF(PAR, USART3_PAR_NONE) | |
| 73 | | USART3_BF(NBSTOP, USART3_NBSTOP_1))); | |
| f93ae788 WD |
74 | |
| 75 | return 0; | |
| 76 | } | |
| 77 | ||
| 78 | void serial_putc(char c) | |
| 79 | { | |
| 80 | if (c == '\n') | |
| 81 | serial_putc('\r'); | |
| 82 | ||
| df548d3c HS |
83 | while (!(usart3_readl(CSR) & USART3_BIT(TXRDY))) ; |
| 84 | usart3_writel(THR, c); | |
| f93ae788 WD |
85 | } |
| 86 | ||
| 87 | void serial_puts(const char *s) | |
| 88 | { | |
| 89 | while (*s) | |
| 90 | serial_putc(*s++); | |
| 91 | } | |
| 92 | ||
| 93 | int serial_getc(void) | |
| 94 | { | |
| 843a2654 JCPV |
95 | while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) |
| 96 | WATCHDOG_RESET(); | |
| df548d3c | 97 | return usart3_readl(RHR); |
| f93ae788 WD |
98 | } |
| 99 | ||
| 100 | int serial_tstc(void) | |
| 101 | { | |
| df548d3c | 102 | return (usart3_readl(CSR) & USART3_BIT(RXRDY)) != 0; |
| f93ae788 | 103 | } |