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1 | /* |
2 | * Register definitions for the Atmel USART3 module. | |
3 | * | |
4 | * Copyright (C) 2005-2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | #ifndef __DRIVERS_ATMEL_USART_H__ | |
21 | #define __DRIVERS_ATMEL_USART_H__ | |
22 | ||
23 | /* USART3 register offsets */ | |
24 | #define USART3_CR 0x0000 | |
25 | #define USART3_MR 0x0004 | |
26 | #define USART3_IER 0x0008 | |
27 | #define USART3_IDR 0x000c | |
28 | #define USART3_IMR 0x0010 | |
29 | #define USART3_CSR 0x0014 | |
30 | #define USART3_RHR 0x0018 | |
31 | #define USART3_THR 0x001c | |
32 | #define USART3_BRGR 0x0020 | |
33 | #define USART3_RTOR 0x0024 | |
34 | #define USART3_TTGR 0x0028 | |
35 | #define USART3_FIDI 0x0040 | |
36 | #define USART3_NER 0x0044 | |
37 | #define USART3_XXR 0x0048 | |
38 | #define USART3_IFR 0x004c | |
39 | #define USART3_RPR 0x0100 | |
40 | #define USART3_RCR 0x0104 | |
41 | #define USART3_TPR 0x0108 | |
42 | #define USART3_TCR 0x010c | |
43 | #define USART3_RNPR 0x0110 | |
44 | #define USART3_RNCR 0x0114 | |
45 | #define USART3_TNPR 0x0118 | |
46 | #define USART3_TNCR 0x011c | |
47 | #define USART3_PTCR 0x0120 | |
48 | #define USART3_PTSR 0x0124 | |
49 | ||
50 | /* Bitfields in CR */ | |
51 | #define USART3_RSTRX_OFFSET 2 | |
52 | #define USART3_RSTRX_SIZE 1 | |
53 | #define USART3_RSTTX_OFFSET 3 | |
54 | #define USART3_RSTTX_SIZE 1 | |
55 | #define USART3_RXEN_OFFSET 4 | |
56 | #define USART3_RXEN_SIZE 1 | |
57 | #define USART3_RXDIS_OFFSET 5 | |
58 | #define USART3_RXDIS_SIZE 1 | |
59 | #define USART3_TXEN_OFFSET 6 | |
60 | #define USART3_TXEN_SIZE 1 | |
61 | #define USART3_TXDIS_OFFSET 7 | |
62 | #define USART3_TXDIS_SIZE 1 | |
63 | #define USART3_RSTSTA_OFFSET 8 | |
64 | #define USART3_RSTSTA_SIZE 1 | |
65 | #define USART3_STTBRK_OFFSET 9 | |
66 | #define USART3_STTBRK_SIZE 1 | |
67 | #define USART3_STPBRK_OFFSET 10 | |
68 | #define USART3_STPBRK_SIZE 1 | |
69 | #define USART3_STTTO_OFFSET 11 | |
70 | #define USART3_STTTO_SIZE 1 | |
71 | #define USART3_SENDA_OFFSET 12 | |
72 | #define USART3_SENDA_SIZE 1 | |
73 | #define USART3_RSTIT_OFFSET 13 | |
74 | #define USART3_RSTIT_SIZE 1 | |
75 | #define USART3_RSTNACK_OFFSET 14 | |
76 | #define USART3_RSTNACK_SIZE 1 | |
77 | #define USART3_RETTO_OFFSET 15 | |
78 | #define USART3_RETTO_SIZE 1 | |
79 | #define USART3_DTREN_OFFSET 16 | |
80 | #define USART3_DTREN_SIZE 1 | |
81 | #define USART3_DTRDIS_OFFSET 17 | |
82 | #define USART3_DTRDIS_SIZE 1 | |
83 | #define USART3_RTSEN_OFFSET 18 | |
84 | #define USART3_RTSEN_SIZE 1 | |
85 | #define USART3_RTSDIS_OFFSET 19 | |
86 | #define USART3_RTSDIS_SIZE 1 | |
87 | #define USART3_COMM_TX_OFFSET 30 | |
88 | #define USART3_COMM_TX_SIZE 1 | |
89 | #define USART3_COMM_RX_OFFSET 31 | |
90 | #define USART3_COMM_RX_SIZE 1 | |
91 | ||
92 | /* Bitfields in MR */ | |
93 | #define USART3_USART_MODE_OFFSET 0 | |
94 | #define USART3_USART_MODE_SIZE 4 | |
95 | #define USART3_USCLKS_OFFSET 4 | |
96 | #define USART3_USCLKS_SIZE 2 | |
97 | #define USART3_CHRL_OFFSET 6 | |
98 | #define USART3_CHRL_SIZE 2 | |
99 | #define USART3_SYNC_OFFSET 8 | |
100 | #define USART3_SYNC_SIZE 1 | |
101 | #define USART3_PAR_OFFSET 9 | |
102 | #define USART3_PAR_SIZE 3 | |
103 | #define USART3_NBSTOP_OFFSET 12 | |
104 | #define USART3_NBSTOP_SIZE 2 | |
105 | #define USART3_CHMODE_OFFSET 14 | |
106 | #define USART3_CHMODE_SIZE 2 | |
107 | #define USART3_MSBF_OFFSET 16 | |
108 | #define USART3_MSBF_SIZE 1 | |
109 | #define USART3_MODE9_OFFSET 17 | |
110 | #define USART3_MODE9_SIZE 1 | |
111 | #define USART3_CLKO_OFFSET 18 | |
112 | #define USART3_CLKO_SIZE 1 | |
113 | #define USART3_OVER_OFFSET 19 | |
114 | #define USART3_OVER_SIZE 1 | |
115 | #define USART3_INACK_OFFSET 20 | |
116 | #define USART3_INACK_SIZE 1 | |
117 | #define USART3_DSNACK_OFFSET 21 | |
118 | #define USART3_DSNACK_SIZE 1 | |
119 | #define USART3_MAX_ITERATION_OFFSET 24 | |
120 | #define USART3_MAX_ITERATION_SIZE 3 | |
121 | #define USART3_FILTER_OFFSET 28 | |
122 | #define USART3_FILTER_SIZE 1 | |
123 | ||
124 | /* Bitfields in CSR */ | |
125 | #define USART3_RXRDY_OFFSET 0 | |
126 | #define USART3_RXRDY_SIZE 1 | |
127 | #define USART3_TXRDY_OFFSET 1 | |
128 | #define USART3_TXRDY_SIZE 1 | |
129 | #define USART3_RXBRK_OFFSET 2 | |
130 | #define USART3_RXBRK_SIZE 1 | |
131 | #define USART3_ENDRX_OFFSET 3 | |
132 | #define USART3_ENDRX_SIZE 1 | |
133 | #define USART3_ENDTX_OFFSET 4 | |
134 | #define USART3_ENDTX_SIZE 1 | |
135 | #define USART3_OVRE_OFFSET 5 | |
136 | #define USART3_OVRE_SIZE 1 | |
137 | #define USART3_FRAME_OFFSET 6 | |
138 | #define USART3_FRAME_SIZE 1 | |
139 | #define USART3_PARE_OFFSET 7 | |
140 | #define USART3_PARE_SIZE 1 | |
141 | #define USART3_TIMEOUT_OFFSET 8 | |
142 | #define USART3_TIMEOUT_SIZE 1 | |
143 | #define USART3_TXEMPTY_OFFSET 9 | |
144 | #define USART3_TXEMPTY_SIZE 1 | |
145 | #define USART3_ITERATION_OFFSET 10 | |
146 | #define USART3_ITERATION_SIZE 1 | |
147 | #define USART3_TXBUFE_OFFSET 11 | |
148 | #define USART3_TXBUFE_SIZE 1 | |
149 | #define USART3_RXBUFF_OFFSET 12 | |
150 | #define USART3_RXBUFF_SIZE 1 | |
151 | #define USART3_NACK_OFFSET 13 | |
152 | #define USART3_NACK_SIZE 1 | |
153 | #define USART3_RIIC_OFFSET 16 | |
154 | #define USART3_RIIC_SIZE 1 | |
155 | #define USART3_DSRIC_OFFSET 17 | |
156 | #define USART3_DSRIC_SIZE 1 | |
157 | #define USART3_DCDIC_OFFSET 18 | |
158 | #define USART3_DCDIC_SIZE 1 | |
159 | #define USART3_CTSIC_OFFSET 19 | |
160 | #define USART3_CTSIC_SIZE 1 | |
161 | #define USART3_RI_OFFSET 20 | |
162 | #define USART3_RI_SIZE 1 | |
163 | #define USART3_DSR_OFFSET 21 | |
164 | #define USART3_DSR_SIZE 1 | |
165 | #define USART3_DCD_OFFSET 22 | |
166 | #define USART3_DCD_SIZE 1 | |
167 | #define USART3_CTS_OFFSET 23 | |
168 | #define USART3_CTS_SIZE 1 | |
169 | ||
170 | /* Bitfields in RHR */ | |
171 | #define USART3_RXCHR_OFFSET 0 | |
172 | #define USART3_RXCHR_SIZE 9 | |
173 | ||
174 | /* Bitfields in THR */ | |
175 | #define USART3_TXCHR_OFFSET 0 | |
176 | #define USART3_TXCHR_SIZE 9 | |
177 | ||
178 | /* Bitfields in BRGR */ | |
179 | #define USART3_CD_OFFSET 0 | |
180 | #define USART3_CD_SIZE 16 | |
181 | ||
182 | /* Bitfields in RTOR */ | |
183 | #define USART3_TO_OFFSET 0 | |
184 | #define USART3_TO_SIZE 16 | |
185 | ||
186 | /* Bitfields in TTGR */ | |
187 | #define USART3_TG_OFFSET 0 | |
188 | #define USART3_TG_SIZE 8 | |
189 | ||
190 | /* Bitfields in FIDI */ | |
191 | #define USART3_FI_DI_RATIO_OFFSET 0 | |
192 | #define USART3_FI_DI_RATIO_SIZE 11 | |
193 | ||
194 | /* Bitfields in NER */ | |
195 | #define USART3_NB_ERRORS_OFFSET 0 | |
196 | #define USART3_NB_ERRORS_SIZE 8 | |
197 | ||
198 | /* Bitfields in XXR */ | |
199 | #define USART3_XOFF_OFFSET 0 | |
200 | #define USART3_XOFF_SIZE 8 | |
201 | #define USART3_XON_OFFSET 8 | |
202 | #define USART3_XON_SIZE 8 | |
203 | ||
204 | /* Bitfields in IFR */ | |
205 | #define USART3_IRDA_FILTER_OFFSET 0 | |
206 | #define USART3_IRDA_FILTER_SIZE 8 | |
207 | ||
208 | /* Bitfields in RCR */ | |
209 | #define USART3_RXCTR_OFFSET 0 | |
210 | #define USART3_RXCTR_SIZE 16 | |
211 | ||
212 | /* Bitfields in TCR */ | |
213 | #define USART3_TXCTR_OFFSET 0 | |
214 | #define USART3_TXCTR_SIZE 16 | |
215 | ||
216 | /* Bitfields in RNCR */ | |
217 | #define USART3_RXNCR_OFFSET 0 | |
218 | #define USART3_RXNCR_SIZE 16 | |
219 | ||
220 | /* Bitfields in TNCR */ | |
221 | #define USART3_TXNCR_OFFSET 0 | |
222 | #define USART3_TXNCR_SIZE 16 | |
223 | ||
224 | /* Bitfields in PTCR */ | |
225 | #define USART3_RXTEN_OFFSET 0 | |
226 | #define USART3_RXTEN_SIZE 1 | |
227 | #define USART3_RXTDIS_OFFSET 1 | |
228 | #define USART3_RXTDIS_SIZE 1 | |
229 | #define USART3_TXTEN_OFFSET 8 | |
230 | #define USART3_TXTEN_SIZE 1 | |
231 | #define USART3_TXTDIS_OFFSET 9 | |
232 | #define USART3_TXTDIS_SIZE 1 | |
233 | ||
234 | /* Constants for USART_MODE */ | |
235 | #define USART3_USART_MODE_NORMAL 0 | |
236 | #define USART3_USART_MODE_RS485 1 | |
237 | #define USART3_USART_MODE_HARDWARE 2 | |
238 | #define USART3_USART_MODE_MODEM 3 | |
239 | #define USART3_USART_MODE_ISO7816_T0 4 | |
240 | #define USART3_USART_MODE_ISO7816_T1 6 | |
241 | #define USART3_USART_MODE_IRDA 8 | |
242 | ||
243 | /* Constants for USCLKS */ | |
244 | #define USART3_USCLKS_MCK 0 | |
245 | #define USART3_USCLKS_MCK_DIV 1 | |
246 | #define USART3_USCLKS_SCK 3 | |
247 | ||
248 | /* Constants for CHRL */ | |
249 | #define USART3_CHRL_5 0 | |
250 | #define USART3_CHRL_6 1 | |
251 | #define USART3_CHRL_7 2 | |
252 | #define USART3_CHRL_8 3 | |
253 | ||
254 | /* Constants for PAR */ | |
255 | #define USART3_PAR_EVEN 0 | |
256 | #define USART3_PAR_ODD 1 | |
257 | #define USART3_PAR_SPACE 2 | |
258 | #define USART3_PAR_MARK 3 | |
259 | #define USART3_PAR_NONE 4 | |
260 | #define USART3_PAR_MULTI 6 | |
261 | ||
262 | /* Constants for NBSTOP */ | |
263 | #define USART3_NBSTOP_1 0 | |
264 | #define USART3_NBSTOP_1_5 1 | |
265 | #define USART3_NBSTOP_2 2 | |
266 | ||
267 | /* Constants for CHMODE */ | |
268 | #define USART3_CHMODE_NORMAL 0 | |
269 | #define USART3_CHMODE_ECHO 1 | |
270 | #define USART3_CHMODE_LOCAL_LOOP 2 | |
271 | #define USART3_CHMODE_REMOTE_LOOP 3 | |
272 | ||
273 | /* Constants for MSBF */ | |
274 | #define USART3_MSBF_LSBF 0 | |
275 | #define USART3_MSBF_MSBF 1 | |
276 | ||
277 | /* Constants for OVER */ | |
278 | #define USART3_OVER_X16 0 | |
279 | #define USART3_OVER_X8 1 | |
280 | ||
281 | /* Constants for CD */ | |
282 | #define USART3_CD_DISABLE 0 | |
283 | #define USART3_CD_BYPASS 1 | |
284 | ||
285 | /* Constants for TO */ | |
286 | #define USART3_TO_DISABLE 0 | |
287 | ||
288 | /* Constants for TG */ | |
289 | #define USART3_TG_DISABLE 0 | |
290 | ||
291 | /* Constants for FI_DI_RATIO */ | |
292 | #define USART3_FI_DI_RATIO_DISABLE 0 | |
293 | ||
294 | /* Bit manipulation macros */ | |
295 | #define USART3_BIT(name) \ | |
296 | (1 << USART3_##name##_OFFSET) | |
297 | #define USART3_BF(name,value) \ | |
298 | (((value) & ((1 << USART3_##name##_SIZE) - 1)) \ | |
299 | << USART3_##name##_OFFSET) | |
300 | #define USART3_BFEXT(name,value) \ | |
301 | (((value) >> USART3_##name##_OFFSET) \ | |
302 | & ((1 << USART3_##name##_SIZE) - 1)) | |
303 | #define USART3_BFINS(name,value,old) \ | |
304 | (((old) & ~(((1 << USART3_##name##_SIZE) - 1) \ | |
305 | << USART3_##name##_OFFSET)) \ | |
306 | | USART3_BF(name,value)) | |
307 | ||
308 | /* Register access macros */ | |
df548d3c HS |
309 | #define usart3_readl(reg) \ |
310 | readl((void *)USART_BASE + USART3_##reg) | |
311 | #define usart3_writel(reg,value) \ | |
312 | writel((value), (void *)USART_BASE + USART3_##reg) | |
f93ae788 WD |
313 | |
314 | #endif /* __DRIVERS_ATMEL_USART_H__ */ |