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[thirdparty/u-boot.git] / drivers / serial / ns16550.c
CommitLineData
e85390dc
WD
1/*
2 * COM1 NS16550 support
a47a12be 3 * originally from linux source (arch/powerpc/boot/ns16550.c)
6d0f6bcf 4 * modified to use CONFIG_SYS_ISA_MEM and new defines
e85390dc
WD
5 */
6
d96c2604 7#include <clock_legacy.h>
fa54eb12 8#include <common.h>
50fce1d5 9#include <clk.h>
12e431b2
SG
10#include <dm.h>
11#include <errno.h>
f7ae49fc 12#include <log.h>
e85390dc 13#include <ns16550.h>
b051eecb 14#include <reset.h>
12e431b2 15#include <serial.h>
a1b322a9 16#include <watchdog.h>
401d1c4f 17#include <asm/global_data.h>
61b29b82 18#include <linux/err.h>
167cdad1
GR
19#include <linux/types.h>
20#include <asm/io.h>
e85390dc 21
12e431b2
SG
22DECLARE_GLOBAL_DATA_PTR;
23
200779e3
DZ
24#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
25#define UART_MCRVAL (UART_MCR_DTR | \
26 UART_MCR_RTS) /* RTS/DTR */
12e431b2 27
2e2c514a 28#if !CONFIG_IS_ENABLED(DM_SERIAL)
167cdad1 29#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
f8df9d0d
SG
30#define serial_out(x, y) outb(x, (ulong)y)
31#define serial_in(y) inb((ulong)y)
79df1208 32#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
f8df9d0d
SG
33#define serial_out(x, y) out_be32(y, x)
34#define serial_in(y) in_be32(y)
79df1208 35#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
f8df9d0d
SG
36#define serial_out(x, y) out_le32(y, x)
37#define serial_in(y) in_le32(y)
167cdad1 38#else
f8df9d0d
SG
39#define serial_out(x, y) writeb(x, y)
40#define serial_in(y) readb(y)
167cdad1 41#endif
12e431b2 42#endif /* !CONFIG_DM_SERIAL */
e85390dc 43
7c387646 44#if defined(CONFIG_SOC_KEYSTONE)
ef509b90
VA
45#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
46#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
d57dee57
KM
47#undef UART_MCRVAL
48#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
49#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
50#else
51#define UART_MCRVAL (UART_MCR_RTS)
52#endif
ef509b90
VA
53#endif
54
a160ea0b
PW
55#ifndef CONFIG_SYS_NS16550_IER
56#define CONFIG_SYS_NS16550_IER 0x00
57#endif /* CONFIG_SYS_NS16550_IER */
58
363e6da1 59static inline void serial_out_shift(void *addr, int shift, int value)
76571674 60{
12e431b2 61#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
1f77690e 62 outb(value, (ulong)addr);
78b7d37b 63#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
12e431b2
SG
64 out_le32(addr, value);
65#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
66 out_be32(addr, value);
90914008
SG
67#elif defined(CONFIG_SYS_NS16550_MEM32)
68 writel(value, addr);
12e431b2 69#elif defined(CONFIG_SYS_BIG_ENDIAN)
76571674 70 writeb(value, addr + (1 << shift) - 1);
12e431b2
SG
71#else
72 writeb(value, addr);
73#endif
74}
75
363e6da1 76static inline int serial_in_shift(void *addr, int shift)
12e431b2 77{
12e431b2 78#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
1f77690e 79 return inb((ulong)addr);
78b7d37b 80#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
12e431b2
SG
81 return in_le32(addr);
82#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
83 return in_be32(addr);
90914008
SG
84#elif defined(CONFIG_SYS_NS16550_MEM32)
85 return readl(addr);
12e431b2 86#elif defined(CONFIG_SYS_BIG_ENDIAN)
20379c11 87 return readb(addr + (1 << shift) - 1);
12e431b2
SG
88#else
89 return readb(addr);
90#endif
91}
92
2e2c514a 93#if CONFIG_IS_ENABLED(DM_SERIAL)
fa4ce723
MV
94
95#ifndef CONFIG_SYS_NS16550_CLK
96#define CONFIG_SYS_NS16550_CLK 0
97#endif
98
62cbde4c
SG
99/*
100 * Use this #ifdef for now since many platforms don't define in(), out(),
101 * out_le32(), etc. but we don't have #defines to indicate this.
102 *
103 * TODO(sjg@chromium.org): Add CONFIG options to indicate what I/O is available
104 * on a platform
105 */
106#ifdef CONFIG_NS16550_DYNAMIC
8a8d24bd 107static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
62cbde4c
SG
108 int value)
109{
110 if (plat->flags & NS16550_FLAG_IO) {
111 outb(value, addr);
112 } else if (plat->reg_width == 4) {
113 if (plat->flags & NS16550_FLAG_ENDIAN) {
114 if (plat->flags & NS16550_FLAG_BE)
115 out_be32(addr, value);
116 else
117 out_le32(addr, value);
118 } else {
119 writel(value, addr);
120 }
121 } else if (plat->flags & NS16550_FLAG_BE) {
122 writeb(value, addr + (1 << plat->reg_shift) - 1);
123 } else {
124 writeb(value, addr);
125 }
126}
127
8a8d24bd 128static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
62cbde4c
SG
129{
130 if (plat->flags & NS16550_FLAG_IO) {
131 return inb(addr);
132 } else if (plat->reg_width == 4) {
133 if (plat->flags & NS16550_FLAG_ENDIAN) {
134 if (plat->flags & NS16550_FLAG_BE)
135 return in_be32(addr);
136 else
137 return in_le32(addr);
138 } else {
139 return readl(addr);
140 }
141 } else if (plat->flags & NS16550_FLAG_BE) {
142 return readb(addr + (1 << plat->reg_shift) - 1);
143 } else {
144 return readb(addr);
145 }
146}
147#else
8a8d24bd 148static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
62cbde4c
SG
149 int value)
150{
151}
152
8a8d24bd 153static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
62cbde4c
SG
154{
155 return 0;
156}
157
158#endif /* CONFIG_NS16550_DYNAMIC */
159
d30c7209 160static void ns16550_writeb(struct ns16550 *port, int offset, int value)
76571674 161{
8a8d24bd 162 struct ns16550_plat *plat = port->plat;
76571674
SG
163 unsigned char *addr;
164
165 offset *= 1 << plat->reg_shift;
62cbde4c 166 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
df8ec55d 167
62cbde4c
SG
168 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
169 serial_out_dynamic(plat, addr, value);
170 else
171 serial_out_shift(addr, plat->reg_shift, value);
76571674
SG
172}
173
d30c7209 174static int ns16550_readb(struct ns16550 *port, int offset)
76571674 175{
8a8d24bd 176 struct ns16550_plat *plat = port->plat;
76571674
SG
177 unsigned char *addr;
178
179 offset *= 1 << plat->reg_shift;
62cbde4c 180 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
76571674 181
62cbde4c
SG
182 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
183 return serial_in_dynamic(plat, addr);
184 else
185 return serial_in_shift(addr, plat->reg_shift);
76571674
SG
186}
187
d30c7209 188static u32 ns16550_getfcr(struct ns16550 *port)
65f83802 189{
8a8d24bd 190 struct ns16550_plat *plat = port->plat;
65f83802
MV
191
192 return plat->fcr;
193}
194
12e431b2
SG
195/* We can clean these up once everything is moved to driver model */
196#define serial_out(value, addr) \
363e6da1
SG
197 ns16550_writeb(com_port, \
198 (unsigned char *)addr - (unsigned char *)com_port, value)
12e431b2 199#define serial_in(addr) \
363e6da1
SG
200 ns16550_readb(com_port, \
201 (unsigned char *)addr - (unsigned char *)com_port)
65f83802 202#else
d30c7209 203static u32 ns16550_getfcr(struct ns16550 *port)
65f83802 204{
17fa0326 205 return UART_FCR_DEFVAL;
65f83802 206}
12e431b2
SG
207#endif
208
d30c7209 209int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
fa54eb12
SG
210{
211 const unsigned int mode_x_div = 16;
212
21d00436
SG
213 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
214}
215
2d6bf754 216static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
8bbe33c8 217{
9ad3b049
SG
218 /* to keep serial format, read lcr before writing BKSE */
219 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
220
221 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
8bbe33c8
SG
222 serial_out(baud_divisor & 0xff, &com_port->dll);
223 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
9ad3b049 224 serial_out(lcr_val, &com_port->lcr);
8bbe33c8
SG
225}
226
2d6bf754 227void ns16550_init(struct ns16550 *com_port, int baud_divisor)
e85390dc 228{
956a8bae
GG
229#if (defined(CONFIG_SPL_BUILD) && \
230 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
fd2aeac5 231 /*
956a8bae
GG
232 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
233 * before SPL starts only THRE bit is set. We have to empty the
234 * transmitter before initialization starts.
fd2aeac5
MH
235 */
236 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
237 == UART_LSR_THRE) {
12e431b2 238 if (baud_divisor != -1)
2d6bf754 239 ns16550_setbrg(com_port, baud_divisor);
1c16606a
PD
240 else {
241 // Re-use old baud rate divisor to flush transmit reg.
242 const int dll = serial_in(&com_port->dll);
243 const int dlm = serial_in(&com_port->dlm);
244 const int divisor = dll | (dlm << 8);
2d6bf754 245 ns16550_setbrg(com_port, divisor);
1c16606a 246 }
fd2aeac5
MH
247 serial_out(0, &com_port->mdr1);
248 }
249#endif
250
cb55b332
SW
251 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
252 ;
253
a160ea0b 254 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
5d754197 255#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
167cdad1 256 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
945af8d7 257#endif
b051eecb 258
167cdad1 259 serial_out(UART_MCRVAL, &com_port->mcr);
65f83802 260 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
9ad3b049
SG
261 /* initialize serial config to 8N1 before writing baudrate */
262 serial_out(UART_LCRVAL, &com_port->lcr);
12e431b2 263 if (baud_divisor != -1)
2d6bf754 264 ns16550_setbrg(com_port, baud_divisor);
5d754197
LV
265#if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
266 defined(CONFIG_OMAP_SERIAL)
f8df9d0d
SG
267 /* /16 is proper to hit 115200 with 48MHz */
268 serial_out(0, &com_port->mdr1);
89024ddc 269#endif
7c387646 270#if defined(CONFIG_SOC_KEYSTONE)
ef509b90
VA
271 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
272#endif
e85390dc
WD
273}
274
f5675aa5 275#ifndef CONFIG_NS16550_MIN_FUNCTIONS
2d6bf754 276void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
e85390dc 277{
a160ea0b 278 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
2d6bf754 279 ns16550_setbrg(com_port, 0);
167cdad1 280 serial_out(UART_MCRVAL, &com_port->mcr);
65f83802 281 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
2d6bf754 282 ns16550_setbrg(com_port, baud_divisor);
e85390dc 283}
f5675aa5 284#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
e85390dc 285
2d6bf754 286void ns16550_putc(struct ns16550 *com_port, char c)
e85390dc 287{
f8df9d0d
SG
288 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
289 ;
167cdad1 290 serial_out(c, &com_port->thr);
1a2d9b30
SR
291
292 /*
293 * Call watchdog_reset() upon newline. This is done here in putc
294 * since the environment code uses a single puts() to print the complete
295 * environment upon "printenv". So we can't put this watchdog call
296 * in puts().
297 */
298 if (c == '\n')
299 WATCHDOG_RESET();
e85390dc
WD
300}
301
f5675aa5 302#ifndef CONFIG_NS16550_MIN_FUNCTIONS
2d6bf754 303char ns16550_getc(struct ns16550 *com_port)
e85390dc 304{
167cdad1 305 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
f2041388 306#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
232c150a
WD
307 extern void usbtty_poll(void);
308 usbtty_poll();
309#endif
a1b322a9 310 WATCHDOG_RESET();
232c150a 311 }
167cdad1 312 return serial_in(&com_port->rbr);
e85390dc
WD
313}
314
2d6bf754 315int ns16550_tstc(struct ns16550 *com_port)
e85390dc 316{
f8df9d0d 317 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
e85390dc
WD
318}
319
f5675aa5 320#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
12e431b2 321
21d00436
SG
322#ifdef CONFIG_DEBUG_UART_NS16550
323
324#include <debug_uart.h>
325
97b05973 326static inline void _debug_uart_init(void)
21d00436 327{
d30c7209 328 struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
21d00436
SG
329 int baud_divisor;
330
331 /*
332 * We copy the code from above because it is already horribly messy.
333 * Trying to refactor to nicely remove the duplication doesn't seem
334 * feasible. The better fix is to move all users of this driver to
335 * driver model.
336 */
03c6f176
MV
337 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
338 CONFIG_BAUDRATE);
6e780c7a
SG
339 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
340 serial_dout(&com_port->mcr, UART_MCRVAL);
17fa0326 341 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
6e780c7a
SG
342
343 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
344 serial_dout(&com_port->dll, baud_divisor & 0xff);
345 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
346 serial_dout(&com_port->lcr, UART_LCRVAL);
21d00436
SG
347}
348
d30c7209 349static inline int NS16550_read_baud_divisor(struct ns16550 *com_port)
c4448bdc
SG
350{
351 int ret;
352
353 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
354 ret = serial_din(&com_port->dll) & 0xff;
355 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
356 serial_dout(&com_port->lcr, UART_LCRVAL);
357
358 return ret;
359}
360
21d00436
SG
361static inline void _debug_uart_putc(int ch)
362{
d30c7209 363 struct ns16550 *com_port = (struct ns16550 *)CONFIG_DEBUG_UART_BASE;
21d00436 364
c4448bdc
SG
365 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
366#ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
367 if (!NS16550_read_baud_divisor(com_port))
368 return;
369#endif
370 }
6e780c7a 371 serial_dout(&com_port->thr, ch);
21d00436
SG
372}
373
374DEBUG_UART_FUNCS
375
376#endif
377
2e2c514a 378#if CONFIG_IS_ENABLED(DM_SERIAL)
12e431b2
SG
379static int ns16550_serial_putc(struct udevice *dev, const char ch)
380{
d30c7209 381 struct ns16550 *const com_port = dev_get_priv(dev);
12e431b2
SG
382
383 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
384 return -EAGAIN;
385 serial_out(ch, &com_port->thr);
386
387 /*
388 * Call watchdog_reset() upon newline. This is done here in putc
389 * since the environment code uses a single puts() to print the complete
390 * environment upon "printenv". So we can't put this watchdog call
391 * in puts().
392 */
393 if (ch == '\n')
394 WATCHDOG_RESET();
395
396 return 0;
397}
398
399static int ns16550_serial_pending(struct udevice *dev, bool input)
400{
d30c7209 401 struct ns16550 *const com_port = dev_get_priv(dev);
12e431b2
SG
402
403 if (input)
4dbf9bed 404 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
12e431b2 405 else
4dbf9bed 406 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
12e431b2
SG
407}
408
409static int ns16550_serial_getc(struct udevice *dev)
410{
d30c7209 411 struct ns16550 *const com_port = dev_get_priv(dev);
7fded0ce
SR
412
413 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
12e431b2
SG
414 return -EAGAIN;
415
7fded0ce 416 return serial_in(&com_port->rbr);
12e431b2
SG
417}
418
419static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
420{
d30c7209 421 struct ns16550 *const com_port = dev_get_priv(dev);
8a8d24bd 422 struct ns16550_plat *plat = com_port->plat;
12e431b2
SG
423 int clock_divisor;
424
425 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
426
2d6bf754 427 ns16550_setbrg(com_port, clock_divisor);
12e431b2
SG
428
429 return 0;
430}
431
9ad3b049
SG
432static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
433{
d30c7209 434 struct ns16550 *const com_port = dev_get_priv(dev);
9ad3b049
SG
435 int lcr_val = UART_LCR_WLS_8;
436 uint parity = SERIAL_GET_PARITY(serial_config);
437 uint bits = SERIAL_GET_BITS(serial_config);
438 uint stop = SERIAL_GET_STOP(serial_config);
439
440 /*
441 * only parity config is implemented, check if other serial settings
442 * are the default one.
443 */
444 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
445 return -ENOTSUPP; /* not supported in driver*/
446
447 switch (parity) {
448 case SERIAL_PAR_NONE:
449 /* no bits to add */
450 break;
451 case SERIAL_PAR_ODD:
452 lcr_val |= UART_LCR_PEN;
453 break;
454 case SERIAL_PAR_EVEN:
455 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
456 break;
457 default:
458 return -ENOTSUPP; /* not supported in driver*/
459 }
460
461 serial_out(lcr_val, &com_port->lcr);
462 return 0;
463}
464
50bf7d03
AS
465static int ns16550_serial_getinfo(struct udevice *dev,
466 struct serial_device_info *info)
467{
d30c7209 468 struct ns16550 *const com_port = dev_get_priv(dev);
8a8d24bd 469 struct ns16550_plat *plat = com_port->plat;
50bf7d03
AS
470
471 info->type = SERIAL_CHIP_16550_COMPATIBLE;
472#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
473 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
474#else
475 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
476#endif
477 info->addr = plat->base;
478 info->reg_width = plat->reg_width;
479 info->reg_shift = plat->reg_shift;
480 info->reg_offset = plat->reg_offset;
5db92a0e
AS
481 info->clock = plat->clock;
482
50bf7d03
AS
483 return 0;
484}
485
09bd0840 486static int ns16550_serial_assign_base(struct ns16550_plat *plat, fdt_addr_t base)
720f9e1f 487{
9e6ce621 488 if (base == FDT_ADDR_T_NONE)
720f9e1f
WW
489 return -EINVAL;
490
491#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
9e6ce621 492 plat->base = base;
720f9e1f 493#else
9e6ce621 494 plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
720f9e1f
WW
495#endif
496
497 return 0;
498}
720f9e1f 499
12e431b2
SG
500int ns16550_serial_probe(struct udevice *dev)
501{
0fd3d911 502 struct ns16550_plat *plat = dev_get_plat(dev);
d30c7209 503 struct ns16550 *const com_port = dev_get_priv(dev);
b051eecb 504 struct reset_ctl_bulk reset_bulk;
9e6ce621 505 fdt_addr_t addr;
b051eecb
LFT
506 int ret;
507
9e6ce621
BM
508 /*
509 * If we are on PCI bus, either directly attached to a PCI root port,
caa4daa2 510 * or via a PCI bridge, assign plat->base before probing hardware.
9e6ce621
BM
511 */
512 if (device_is_on_pci_bus(dev)) {
513 addr = devfdt_get_addr_pci(dev);
514 ret = ns16550_serial_assign_base(plat, addr);
515 if (ret)
516 return ret;
517 }
720f9e1f 518
b051eecb
LFT
519 ret = reset_get_bulk(dev, &reset_bulk);
520 if (!ret)
521 reset_deassert_bulk(&reset_bulk);
12e431b2 522
c69cda25 523 com_port->plat = dev_get_plat(dev);
2d6bf754 524 ns16550_init(com_port, -1);
12e431b2
SG
525
526 return 0;
527}
528
79fd9281
MV
529#if CONFIG_IS_ENABLED(OF_CONTROL)
530enum {
531 PORT_NS16550 = 0,
0b060eef 532 PORT_JZ4780,
79fd9281
MV
533};
534#endif
535
414cc151 536#if CONFIG_IS_ENABLED(OF_REAL)
d1998a9f 537int ns16550_serial_of_to_plat(struct udevice *dev)
12e431b2 538{
0fd3d911 539 struct ns16550_plat *plat = dev_get_plat(dev);
0b060eef 540 const u32 port_type = dev_get_driver_data(dev);
9e6ce621 541 fdt_addr_t addr;
021abf69
MY
542 struct clk clk;
543 int err;
12e431b2 544
9e6ce621
BM
545 addr = dev_read_addr(dev);
546 err = ns16550_serial_assign_base(plat, addr);
547 if (err && !device_is_on_pci_bus(dev))
548 return err;
549
3d40479f
PT
550 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
551 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
4e720779 552 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
50fce1d5
PB
553
554 err = clk_get_by_index(dev, 0, &clk);
555 if (!err) {
556 err = clk_get_rate(&clk);
557 if (!IS_ERR_VALUE(err))
558 plat->clock = err;
ab895d6a 559 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
50fce1d5
PB
560 debug("ns16550 failed to get clock\n");
561 return err;
562 }
563
564 if (!plat->clock)
3d40479f
PT
565 plat->clock = dev_read_u32_default(dev, "clock-frequency",
566 CONFIG_SYS_NS16550_CLK);
384b62c0
BM
567 if (!plat->clock)
568 plat->clock = CONFIG_SYS_NS16550_CLK;
8e62d32e
TC
569 if (!plat->clock) {
570 debug("ns16550 clock not defined\n");
571 return -EINVAL;
572 }
12e431b2 573
17fa0326 574 plat->fcr = UART_FCR_DEFVAL;
0b060eef
MV
575 if (port_type == PORT_JZ4780)
576 plat->fcr |= UART_FCR_UME;
65f83802 577
12e431b2
SG
578 return 0;
579}
11c1a878 580#endif
12e431b2
SG
581
582const struct dm_serial_ops ns16550_serial_ops = {
583 .putc = ns16550_serial_putc,
584 .pending = ns16550_serial_pending,
585 .getc = ns16550_serial_getc,
586 .setbrg = ns16550_serial_setbrg,
50bf7d03
AS
587 .setconfig = ns16550_serial_setconfig,
588 .getinfo = ns16550_serial_getinfo,
12e431b2 589};
8e62d32e 590
414cc151 591#if CONFIG_IS_ENABLED(OF_REAL)
cc4228f9
TC
592/*
593 * Please consider existing compatible strings before adding a new
594 * one to keep this table compact. Or you may add a generic "ns16550"
595 * compatible string to your dts.
596 */
8e62d32e 597static const struct udevice_id ns16550_serial_ids[] = {
79fd9281
MV
598 { .compatible = "ns16550", .data = PORT_NS16550 },
599 { .compatible = "ns16550a", .data = PORT_NS16550 },
0b060eef 600 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
79fd9281
MV
601 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
602 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
8e62d32e
TC
603 {}
604};
414cc151 605#endif /* OF_REAL */
8e62d32e 606
b7e29834 607#if CONFIG_IS_ENABLED(SERIAL_PRESENT)
6f8c351e
AG
608
609/* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
610#if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
8e62d32e
TC
611U_BOOT_DRIVER(ns16550_serial) = {
612 .name = "ns16550_serial",
613 .id = UCLASS_SERIAL,
414cc151 614#if CONFIG_IS_ENABLED(OF_REAL)
8e62d32e 615 .of_match = ns16550_serial_ids,
d1998a9f 616 .of_to_plat = ns16550_serial_of_to_plat,
8a8d24bd 617 .plat_auto = sizeof(struct ns16550_plat),
8e62d32e 618#endif
d30c7209 619 .priv_auto = sizeof(struct ns16550),
8e62d32e
TC
620 .probe = ns16550_serial_probe,
621 .ops = &ns16550_serial_ops,
46879196 622#if !CONFIG_IS_ENABLED(OF_CONTROL)
b7e5a643 623 .flags = DM_FLAG_PRE_RELOC,
46879196 624#endif
8e62d32e 625};
addf358b 626
bdf8fd76
SG
627DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3328_uart)
628DM_DRIVER_ALIAS(ns16550_serial, rockchip_rk3368_uart)
629DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
b7e29834 630#endif
6f8c351e
AG
631#endif /* SERIAL_PRESENT */
632
12e431b2 633#endif /* CONFIG_DM_SERIAL */