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serial: lpuart: Enable IPG clock
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
427eba70 2/*
1edc5688 3 * Copyright 2019 NXP
427eba70 4 * Copyright 2013 Freescale Semiconductor, Inc.
427eba70
AW
5 */
6
7#include <common.h>
2f8a6db5 8#include <clock_legacy.h>
8f5b6299 9#include <clk.h>
fdbae099 10#include <dm.h>
c40d612b 11#include <fsl_lpuart.h>
f7ae49fc 12#include <log.h>
427eba70 13#include <watchdog.h>
401d1c4f 14#include <asm/global_data.h>
427eba70
AW
15#include <asm/io.h>
16#include <serial.h>
336d4615 17#include <dm/device_compat.h>
cd93d625 18#include <linux/bitops.h>
427eba70
AW
19#include <linux/compiler.h>
20#include <asm/arch/imx-regs.h>
21#include <asm/arch/clock.h>
22
47f1bfca
BM
23#define US1_TDRE (1 << 7)
24#define US1_RDRF (1 << 5)
25#define US1_OR (1 << 3)
26#define UC2_TE (1 << 3)
27#define UC2_RE (1 << 2)
28#define CFIFO_TXFLUSH (1 << 7)
29#define CFIFO_RXFLUSH (1 << 6)
30#define SFIFO_RXOF (1 << 2)
31#define SFIFO_RXUF (1 << 0)
427eba70 32
6209e14c
JL
33#define STAT_LBKDIF (1 << 31)
34#define STAT_RXEDGIF (1 << 30)
35#define STAT_TDRE (1 << 23)
36#define STAT_RDRF (1 << 21)
37#define STAT_IDLE (1 << 20)
38#define STAT_OR (1 << 19)
39#define STAT_NF (1 << 18)
40#define STAT_FE (1 << 17)
41#define STAT_PF (1 << 16)
42#define STAT_MA1F (1 << 15)
43#define STAT_MA2F (1 << 14)
44#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
47f1bfca 45 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
6209e14c
JL
46
47#define CTRL_TE (1 << 19)
48#define CTRL_RE (1 << 18)
49
cdc16f61
YL
50#define FIFO_RXFLUSH BIT(14)
51#define FIFO_TXFLUSH BIT(15)
52#define FIFO_TXSIZE_MASK 0x70
53#define FIFO_TXSIZE_OFF 4
54#define FIFO_RXSIZE_MASK 0x7
55#define FIFO_RXSIZE_OFF 0
6209e14c 56#define FIFO_TXFE 0x80
c32449a1 57#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
126f8849
PF
58#define FIFO_RXFE 0x08
59#else
6209e14c 60#define FIFO_RXFE 0x40
126f8849 61#endif
6209e14c 62
cdc16f61 63#define WATER_TXWATER_OFF 0
6209e14c
JL
64#define WATER_RXWATER_OFF 16
65
427eba70
AW
66DECLARE_GLOBAL_DATA_PTR;
67
c40d612b
PF
68#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
69#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
70
7edf5c45
PF
71enum lpuart_devtype {
72 DEV_VF610 = 1,
73 DEV_LS1021A,
126f8849 74 DEV_MX7ULP,
c32449a1
GB
75 DEV_IMX8,
76 DEV_IMXRT,
7edf5c45
PF
77};
78
8a8d24bd 79struct lpuart_serial_plat {
c40d612b 80 void *reg;
7edf5c45 81 enum lpuart_devtype devtype;
c40d612b 82 ulong flags;
fdbae099
BM
83};
84
c40d612b
PF
85static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
86{
87 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
88 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
89 *(u32 *)val = in_be32(addr);
90 else
91 *(u32 *)val = in_le32(addr);
92 }
93}
94
95static void lpuart_write32(u32 flags, u32 *addr, u32 val)
96{
97 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
98 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
99 out_be32(addr, val);
100 else
101 out_le32(addr, val);
102 }
103}
104
105
c40d612b 106u32 __weak get_lpuart_clk(void)
427eba70 107{
2f8a6db5 108 return get_board_sys_clk();
c40d612b
PF
109}
110
af325e95 111#if CONFIG_IS_ENABLED(CLK)
8f5b6299
PF
112static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
113{
114 struct clk per_clk;
115 ulong rate;
116 int ret;
117
118 ret = clk_get_by_name(dev, "per", &per_clk);
119 if (ret) {
120 dev_err(dev, "Failed to get per clk: %d\n", ret);
121 return ret;
122 }
123
124 rate = clk_get_rate(&per_clk);
125 if ((long)rate <= 0) {
126 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
127 return ret;
128 }
129 *clk = rate;
130 return 0;
131}
132#else
133static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
134{ return -ENOSYS; }
135#endif
136
c40d612b
PF
137static bool is_lpuart32(struct udevice *dev)
138{
0fd3d911 139 struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b
PF
140
141 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
142}
143
8f5b6299 144static void _lpuart_serial_setbrg(struct udevice *dev,
c40d612b
PF
145 int baudrate)
146{
8a8d24bd 147 struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b 148 struct lpuart_fsl *base = plat->reg;
8f5b6299 149 u32 clk;
427eba70 150 u16 sbr;
8f5b6299
PF
151 int ret;
152
af325e95 153 if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299
PF
154 ret = get_lpuart_clk_rate(dev, &clk);
155 if (ret)
156 return;
157 } else {
158 clk = get_lpuart_clk();
159 }
427eba70 160
6ca13b12 161 sbr = (u16)(clk / (16 * baudrate));
427eba70 162
47f1bfca 163 /* place adjustment later - n/32 BRFA */
427eba70
AW
164 __raw_writeb(sbr >> 8, &base->ubdh);
165 __raw_writeb(sbr & 0xff, &base->ubdl);
166}
167
8a8d24bd 168static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
427eba70 169{
c40d612b 170 struct lpuart_fsl *base = plat->reg;
1138bbe0
T
171 if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
172 return -EAGAIN;
427eba70 173
a3db78d8 174 barrier();
427eba70
AW
175
176 return __raw_readb(&base->ud);
177}
178
1138bbe0 179static int _lpuart_serial_putc(struct lpuart_serial_plat *plat,
c40d612b 180 const char c)
427eba70 181{
c40d612b
PF
182 struct lpuart_fsl *base = plat->reg;
183
1138bbe0
T
184 if (!(__raw_readb(&base->us1) & US1_TDRE))
185 return -EAGAIN;
427eba70
AW
186
187 __raw_writeb(c, &base->ud);
1138bbe0 188 return 0;
427eba70
AW
189}
190
47f1bfca 191/* Test whether a character is in the RX buffer */
8a8d24bd 192static int _lpuart_serial_tstc(struct lpuart_serial_plat *plat)
427eba70 193{
c40d612b
PF
194 struct lpuart_fsl *base = plat->reg;
195
427eba70
AW
196 if (__raw_readb(&base->urcfifo) == 0)
197 return 0;
198
199 return 1;
200}
201
202/*
203 * Initialise the serial port with the given baudrate. The settings
204 * are always 8 data bits, no parity, 1 stop bit, no start bits.
205 */
8f5b6299 206static int _lpuart_serial_init(struct udevice *dev)
427eba70 207{
8a8d24bd 208 struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b 209 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
427eba70
AW
210 u8 ctrl;
211
212 ctrl = __raw_readb(&base->uc2);
213 ctrl &= ~UC2_RE;
214 ctrl &= ~UC2_TE;
215 __raw_writeb(ctrl, &base->uc2);
216
217 __raw_writeb(0, &base->umodem);
218 __raw_writeb(0, &base->uc1);
219
89e69fd4
SA
220 /* Disable FIFO and flush buffer */
221 __raw_writeb(0x0, &base->upfifo);
222 __raw_writeb(0x0, &base->utwfifo);
223 __raw_writeb(0x1, &base->urwfifo);
224 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
225
427eba70 226 /* provide data bits, parity, stop bit, etc */
8f5b6299 227 _lpuart_serial_setbrg(dev, gd->baudrate);
427eba70
AW
228
229 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
230
231 return 0;
232}
233
8f5b6299 234static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
7edf5c45
PF
235 int baudrate)
236{
8a8d24bd 237 struct lpuart_serial_plat *plat = dev_get_plat(dev);
7edf5c45
PF
238 struct lpuart_fsl_reg32 *base = plat->reg;
239 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
8f5b6299
PF
240 u32 clk;
241 int ret;
242
af325e95 243 if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299
PF
244 ret = get_lpuart_clk_rate(dev, &clk);
245 if (ret)
246 return;
247 } else {
248 clk = get_lpuart_clk();
249 }
7edf5c45
PF
250
251 baud_diff = baudrate;
252 osr = 0;
253 sbr = 0;
254
255 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
256 tmp_sbr = (clk / (baudrate * tmp_osr));
257
258 if (tmp_sbr == 0)
259 tmp_sbr = 1;
260
261 /*calculate difference in actual buad w/ current values */
262 tmp_diff = (clk / (tmp_osr * tmp_sbr));
263 tmp_diff = tmp_diff - baudrate;
264
265 /* select best values between sbr and sbr+1 */
266 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
267 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
268 tmp_sbr++;
269 }
270
271 if (tmp_diff <= baud_diff) {
272 baud_diff = tmp_diff;
273 osr = tmp_osr;
274 sbr = tmp_sbr;
275 }
276 }
277
278 /*
279 * TODO: handle buadrate outside acceptable rate
280 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
281 * {
282 * Unacceptable baud rate difference of more than 3%
283 * return kStatus_LPUART_BaudrateNotSupport;
284 * }
285 */
286 tmp = in_le32(&base->baud);
287
288 if ((osr > 3) && (osr < 8))
289 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
290
291 tmp &= ~LPUART_BAUD_OSR_MASK;
292 tmp |= LPUART_BAUD_OSR(osr-1);
293
294 tmp &= ~LPUART_BAUD_SBR_MASK;
295 tmp |= LPUART_BAUD_SBR(sbr);
296
297 /* explicitly disable 10 bit mode & set 1 stop bit */
298 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
299
300 out_le32(&base->baud, tmp);
301}
302
8f5b6299 303static void _lpuart32_serial_setbrg(struct udevice *dev,
c40d612b 304 int baudrate)
6209e14c 305{
8a8d24bd 306 struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b 307 struct lpuart_fsl_reg32 *base = plat->reg;
8f5b6299 308 u32 clk;
6209e14c 309 u32 sbr;
8f5b6299
PF
310 int ret;
311
af325e95 312 if (CONFIG_IS_ENABLED(CLK)) {
8f5b6299
PF
313 ret = get_lpuart_clk_rate(dev, &clk);
314 if (ret)
315 return;
316 } else {
317 clk = get_lpuart_clk();
318 }
6209e14c 319
6ca13b12 320 sbr = (clk / (16 * baudrate));
6209e14c 321
47f1bfca 322 /* place adjustment later - n/32 BRFA */
c40d612b 323 lpuart_write32(plat->flags, &base->baud, sbr);
6209e14c
JL
324}
325
8a8d24bd 326static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
6209e14c 327{
c40d612b 328 struct lpuart_fsl_reg32 *base = plat->reg;
7edf5c45 329 u32 stat, val;
6209e14c 330
c40d612b 331 lpuart_read32(plat->flags, &base->stat, &stat);
1138bbe0 332 if ((stat & STAT_RDRF) == 0) {
c40d612b 333 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
1138bbe0 334 return -EAGAIN;
6209e14c
JL
335 }
336
7edf5c45 337 lpuart_read32(plat->flags, &base->data, &val);
c40d612b 338
a2bbfc54
SD
339 lpuart_read32(plat->flags, &base->stat, &stat);
340 if (stat & STAT_OR)
341 lpuart_write32(plat->flags, &base->stat, STAT_OR);
7edf5c45
PF
342
343 return val & 0x3ff;
6209e14c
JL
344}
345
1138bbe0 346static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
c40d612b 347 const char c)
6209e14c 348{
c40d612b
PF
349 struct lpuart_fsl_reg32 *base = plat->reg;
350 u32 stat;
351
1138bbe0
T
352 lpuart_read32(plat->flags, &base->stat, &stat);
353 if (!(stat & STAT_TDRE))
354 return -EAGAIN;
6209e14c 355
c40d612b 356 lpuart_write32(plat->flags, &base->data, c);
1138bbe0 357 return 0;
6209e14c
JL
358}
359
47f1bfca 360/* Test whether a character is in the RX buffer */
8a8d24bd 361static int _lpuart32_serial_tstc(struct lpuart_serial_plat *plat)
6209e14c 362{
c40d612b
PF
363 struct lpuart_fsl_reg32 *base = plat->reg;
364 u32 water;
365
366 lpuart_read32(plat->flags, &base->water, &water);
367
368 if ((water >> 24) == 0)
6209e14c
JL
369 return 0;
370
371 return 1;
372}
373
374/*
375 * Initialise the serial port with the given baudrate. The settings
376 * are always 8 data bits, no parity, 1 stop bit, no start bits.
377 */
8f5b6299 378static int _lpuart32_serial_init(struct udevice *dev)
6209e14c 379{
8a8d24bd 380 struct lpuart_serial_plat *plat = dev_get_plat(dev);
c40d612b 381 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
cdc16f61 382 u32 val, tx_fifo_size;
6209e14c 383
cdc16f61
YL
384 lpuart_read32(plat->flags, &base->ctrl, &val);
385 val &= ~CTRL_RE;
386 val &= ~CTRL_TE;
387 lpuart_write32(plat->flags, &base->ctrl, val);
6209e14c 388
c40d612b 389 lpuart_write32(plat->flags, &base->modir, 0);
cdc16f61
YL
390
391 lpuart_read32(plat->flags, &base->fifo, &val);
392 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
393 /* Set the TX water to half of FIFO size */
394 if (tx_fifo_size > 1)
395 tx_fifo_size = tx_fifo_size >> 1;
396
397 /* Set RX water to 0, to be triggered by any receive data */
398 lpuart_write32(plat->flags, &base->water,
399 (tx_fifo_size << WATER_TXWATER_OFF));
400
401 /* Enable TX and RX FIFO */
402 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
403 lpuart_write32(plat->flags, &base->fifo, val);
6209e14c 404
c40d612b 405 lpuart_write32(plat->flags, &base->match, 0);
6209e14c 406
c32449a1
GB
407 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
408 plat->devtype == DEV_IMXRT) {
8f5b6299 409 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
7edf5c45
PF
410 } else {
411 /* provide data bits, parity, stop bit, etc */
8f5b6299 412 _lpuart32_serial_setbrg(dev, gd->baudrate);
7edf5c45 413 }
6209e14c 414
c40d612b 415 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
6209e14c
JL
416
417 return 0;
418}
419
c40d612b 420static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
fdbae099 421{
8a8d24bd 422 struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099 423
7edf5c45 424 if (is_lpuart32(dev)) {
c32449a1
GB
425 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
426 plat->devtype == DEV_IMXRT)
8f5b6299 427 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
7edf5c45 428 else
8f5b6299 429 _lpuart32_serial_setbrg(dev, baudrate);
7edf5c45 430 } else {
8f5b6299 431 _lpuart_serial_setbrg(dev, baudrate);
7edf5c45 432 }
fdbae099
BM
433
434 return 0;
435}
436
c40d612b 437static int lpuart_serial_getc(struct udevice *dev)
fdbae099 438{
0fd3d911 439 struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099 440
c40d612b
PF
441 if (is_lpuart32(dev))
442 return _lpuart32_serial_getc(plat);
443
444 return _lpuart_serial_getc(plat);
fdbae099
BM
445}
446
c40d612b 447static int lpuart_serial_putc(struct udevice *dev, const char c)
fdbae099 448{
0fd3d911 449 struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099 450
c40d612b 451 if (is_lpuart32(dev))
1138bbe0 452 return _lpuart32_serial_putc(plat, c);
fdbae099 453
1138bbe0 454 return _lpuart_serial_putc(plat, c);
fdbae099
BM
455}
456
c40d612b 457static int lpuart_serial_pending(struct udevice *dev, bool input)
fdbae099 458{
0fd3d911 459 struct lpuart_serial_plat *plat = dev_get_plat(dev);
fdbae099 460 struct lpuart_fsl *reg = plat->reg;
c40d612b
PF
461 struct lpuart_fsl_reg32 *reg32 = plat->reg;
462 u32 stat;
463
464 if (is_lpuart32(dev)) {
465 if (input) {
466 return _lpuart32_serial_tstc(plat);
467 } else {
468 lpuart_read32(plat->flags, &reg32->stat, &stat);
469 return stat & STAT_TDRE ? 0 : 1;
470 }
471 }
fdbae099
BM
472
473 if (input)
c40d612b 474 return _lpuart_serial_tstc(plat);
fdbae099 475 else
c40d612b 476 return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
fdbae099
BM
477}
478
c40d612b 479static int lpuart_serial_probe(struct udevice *dev)
fdbae099 480{
55631db8
GB
481#if CONFIG_IS_ENABLED(CLK)
482 struct clk per_clk;
cc7df0b9 483 struct clk ipg_clk;
55631db8
GB
484 int ret;
485
486 ret = clk_get_by_name(dev, "per", &per_clk);
487 if (!ret) {
488 ret = clk_enable(&per_clk);
489 if (ret) {
cc7df0b9 490 dev_err(dev, "Failed to enable per clk: %d\n", ret);
55631db8
GB
491 return ret;
492 }
493 } else {
289dd9f0 494 debug("%s: Failed to get per clk: %d\n", __func__, ret);
55631db8 495 }
cc7df0b9
YL
496
497 ret = clk_get_by_name(dev, "ipg", &ipg_clk);
498 if (!ret) {
499 ret = clk_enable(&ipg_clk);
500 if (ret) {
501 dev_err(dev, "Failed to enable ipg clk: %d\n", ret);
502 return ret;
503 }
504 } else {
505 debug("%s: Failed to get ipg clk: %d\n", __func__, ret);
506 }
55631db8
GB
507#endif
508
c40d612b 509 if (is_lpuart32(dev))
8f5b6299 510 return _lpuart32_serial_init(dev);
c40d612b 511 else
8f5b6299 512 return _lpuart_serial_init(dev);
fdbae099 513}
427eba70 514
d1998a9f 515static int lpuart_serial_of_to_plat(struct udevice *dev)
fdbae099 516{
0fd3d911 517 struct lpuart_serial_plat *plat = dev_get_plat(dev);
7edf5c45 518 const void *blob = gd->fdt_blob;
da409ccc 519 int node = dev_of_offset(dev);
fdbae099
BM
520 fdt_addr_t addr;
521
2548493a 522 addr = dev_read_addr(dev);
fdbae099
BM
523 if (addr == FDT_ADDR_T_NONE)
524 return -EINVAL;
525
c40d612b
PF
526 plat->reg = (void *)addr;
527 plat->flags = dev_get_driver_data(dev);
fdbae099 528
1edc5688
VS
529 if (fdtdec_get_bool(blob, node, "little-endian"))
530 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
531
7edf5c45
PF
532 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
533 plat->devtype = DEV_LS1021A;
534 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
535 plat->devtype = DEV_MX7ULP;
536 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
537 plat->devtype = DEV_VF610;
126f8849
PF
538 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
539 plat->devtype = DEV_IMX8;
c32449a1
GB
540 else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
541 plat->devtype = DEV_IMXRT;
7edf5c45 542
fdbae099
BM
543 return 0;
544}
545
fdbae099
BM
546static const struct dm_serial_ops lpuart_serial_ops = {
547 .putc = lpuart_serial_putc,
548 .pending = lpuart_serial_pending,
549 .getc = lpuart_serial_getc,
550 .setbrg = lpuart_serial_setbrg,
551};
552
553static const struct udevice_id lpuart_serial_ids[] = {
c40d612b
PF
554 { .compatible = "fsl,ls1021a-lpuart", .data =
555 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
c9bf9af9
MW
556 { .compatible = "fsl,ls1028a-lpuart",
557 .data = LPUART_FLAG_REGMAP_32BIT_REG },
7edf5c45
PF
558 { .compatible = "fsl,imx7ulp-lpuart",
559 .data = LPUART_FLAG_REGMAP_32BIT_REG },
c40d612b 560 { .compatible = "fsl,vf610-lpuart"},
126f8849
PF
561 { .compatible = "fsl,imx8qm-lpuart",
562 .data = LPUART_FLAG_REGMAP_32BIT_REG },
c32449a1
GB
563 { .compatible = "fsl,imxrt-lpuart",
564 .data = LPUART_FLAG_REGMAP_32BIT_REG },
fdbae099
BM
565 { }
566};
567
568U_BOOT_DRIVER(serial_lpuart) = {
569 .name = "serial_lpuart",
570 .id = UCLASS_SERIAL,
571 .of_match = lpuart_serial_ids,
d1998a9f 572 .of_to_plat = lpuart_serial_of_to_plat,
8a8d24bd 573 .plat_auto = sizeof(struct lpuart_serial_plat),
fdbae099
BM
574 .probe = lpuart_serial_probe,
575 .ops = &lpuart_serial_ops,
fdbae099 576};