[people/ms/u-boot.git] / drivers / serial / serial_mpc8xx.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <commproc.h>
#include <command.h>
#include <serial.h>
#include <watchdog.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
#define	SMC_INDEX	0
#define PROFF_SMC	PROFF_SMC1
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1
#define IOPINS		0xc0

#elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
#define SMC_INDEX	1
#define PROFF_SMC	PROFF_SMC2
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC2
#define IOPINS		0xc00

#endif /* CONFIG_8xx_CONS_SMCx */

struct serialbuffer {
	cbd_t	rxbd;		/* Rx BD */
	cbd_t	txbd;		/* Tx BD */
	uint	rxindex;	/* index for next character to read */
	uchar	rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	uchar	txbuf;	/* tx buffers */
};

static void serial_setdivisor(cpm8xx_t __iomem *cp)
{
	int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;

	if (divisor / 16 > 0x1000) {
		/* bad divisor, assume 50MHz clock and 9600 baud */
		divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
	}

	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;

	if (divisor <= 0x1000)
		out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN);
	else
		out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN |
			 CPM_BRG_DIV16);
}

/*
 * Minimal serial functions needed to use one of the SMC ports
 * as serial console interface.
 */

static void smc_setbrg(void)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t __iomem *cp = &(im->im_cpm);

	/* Set up the baud rate generator.
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SMCx
	 */

	out_be32(&cp->cp_simode, 0);

	serial_setdivisor(cp);
}

static int smc_init(void)
{
	immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	smc_t __iomem *sp;
	smc_uart_t __iomem *up;
	cpm8xx_t __iomem *cp = &(im->im_cpm);
	struct serialbuffer __iomem *rtx;

	/* initialize pointers to SMC */

	sp = cp->cp_smc + SMC_INDEX;
	up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
	/* Disable relocation */
	out_be16(&up->smc_rpbase, 0);

	/* Disable transmitter/receiver. */
	clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA. */
	out_be32(&im->im_siu_conf.sc_sdcr, 1);

	/* clear error conditions */
	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);

	/* clear SDMA interrupt mask */
	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);

	/* Use Port B for SMCx instead of other functions. */
	setbits_be32(&cp->cp_pbpar, IOPINS);
	clrbits_be32(&cp->cp_pbdir, IOPINS);
	clrbits_be16(&cp->cp_pbodr, IOPINS);

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
	out_be16(&rtx->rxbd.cbd_sc, 0);

	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
	out_be16(&rtx->txbd.cbd_sc, 0);

	/* Set up the uart parameters in the parameter ram. */
	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	out_8(&up->smc_rfcr, SMC_EB);
	out_8(&up->smc_tfcr, SMC_EB);

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 */
	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);

	/* Mask all interrupts and remove anything pending.
	*/
	out_8(&sp->smc_smcm, 0);
	out_8(&sp->smc_smce, 0xff);

	/* Set up the baud rate generator */
	smc_setbrg();

	/* Make the first buffer the only buffer. */
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);

	/* single/multi character receive. */
	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	out_be32(&rtx->rxindex, 0);

	/* Initialize Tx/Rx parameters.	*/
	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)	/* wait if cp is busy */
		;

	out_be16(&cp->cp_cpcr,
		 mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG);

	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)	/* wait if cp is busy */
		;

	/* Enable transmitter/receiver.	*/
	setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);

	return 0;
}

static void smc_putc(const char c)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	if (c == '\n')
		smc_putc('\r');

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	/* Wait for last character to go. */
	out_8(&rtx->txbuf, c);
	out_be16(&rtx->txbd.cbd_datlen, 1);
	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);

	while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
		WATCHDOG_RESET();
}

static void smc_puts(const char *s)
{
	while (*s)
		smc_putc(*s++);
}

static int smc_getc(void)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;
	unsigned char  c;
	uint rxindex;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	/* Wait for character to show up. */
	while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
		WATCHDOG_RESET();

	/* the characters are read one by one,
	 * use the rxindex to know the next char to deliver
	 */
	rxindex = in_be32(&rtx->rxindex);
	c = in_8(rtx->rxbuf + rxindex);
	rxindex++;

	/* check if all char are readout, then make prepare for next receive */
	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
		rxindex = 0;
		setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
	}
	out_be32(&rtx->rxindex, rxindex);
	return c;
}

static int smc_tstc(void)
{
	immap_t	__iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR;
	cpm8xx_t	__iomem *cpmp = &(im->im_cpm);
	struct serialbuffer	__iomem *rtx;

	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];

	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
}

struct serial_device serial_smc_device = {
	.name	= "serial_smc",
	.start	= smc_init,
	.stop	= NULL,
	.setbrg	= smc_setbrg,
	.getc	= smc_getc,
	.tstc	= smc_tstc,
	.putc	= smc_putc,
	.puts	= smc_puts,
};

__weak struct serial_device *default_serial_console(void)
{
	return &serial_smc_device;
}

void mpc8xx_serial_initialize(void)
{
	serial_register(&serial_smc_device);
}
Commit	Line	Data
907208c4 CL	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <commproc.h>
	10	#include <command.h>
	11	#include <serial.h>
	12	#include <watchdog.h>
	13	#include <linux/compiler.h>
	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
907208c4 CL	17	#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
	18	#define SMC_INDEX 0
	19	#define PROFF_SMC PROFF_SMC1
	20	#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
ba3da734	21	#define IOPINS 0xc0
907208c4 CL	22
	23	#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
	24	#define SMC_INDEX 1
	25	#define PROFF_SMC PROFF_SMC2
	26	#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
ba3da734	27	#define IOPINS 0xc00
907208c4 CL	28
	29	#endif /* CONFIG_8xx_CONS_SMCx */
	30
ba3da734	31	struct serialbuffer {
907208c4 CL	32	cbd_t rxbd; /* Rx BD */
	33	cbd_t txbd; /* Tx BD */
	34	uint rxindex; /* index for next character to read */
ba3da734 CL	35	uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	36	uchar txbuf; /* tx buffers */
	37	};
907208c4	38
ba3da734	39	static void serial_setdivisor(cpm8xx_t __iomem *cp)
907208c4	40	{
70fd0710	41	int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate;
907208c4	42
70fd0710	43	if (divisor / 16 > 0x1000) {
907208c4	44	/* bad divisor, assume 50MHz clock and 9600 baud */
70fd0710	45	divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600;
907208c4 CL	46	}
907208c4 CL	47
907208c4	48	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
907208c4	49
ba3da734 CL	50	if (divisor <= 0x1000)
	51	out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) \| CPM_BRG_EN);
	52	else
	53	out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) \| CPM_BRG_EN \|
	54	CPM_BRG_DIV16);
907208c4 CL	55	}
	56
	57	/*
	58	* Minimal serial functions needed to use one of the SMC ports
	59	* as serial console interface.
	60	*/
	61
70fd0710	62	static void smc_setbrg(void)
907208c4	63	{
ba3da734 CL	64	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
ba3da734 CL	65	cpm8xx_t __iomem *cp = &(im->im_cpm);
907208c4 CL	66
	67	/* Set up the baud rate generator.
	68	* See 8xx_io/commproc.c for details.
	69	*
	70	* Wire BRG1 to SMCx
	71	*/
	72
ba3da734	73	out_be32(&cp->cp_simode, 0);
907208c4 CL	74
	75	serial_setdivisor(cp);
	76	}
	77
70fd0710	78	static int smc_init(void)
907208c4	79	{
ba3da734 CL	80	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	81	smc_t __iomem *sp;
	82	smc_uart_t __iomem *up;
	83	cpm8xx_t __iomem *cp = &(im->im_cpm);
	84	struct serialbuffer __iomem *rtx;
907208c4 CL	85
	86	/* initialize pointers to SMC */
	87
ba3da734 CL	88	sp = cp->cp_smc + SMC_INDEX;
ba3da734 CL	89	up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC];
907208c4	90	/* Disable relocation */
ba3da734	91	out_be16(&up->smc_rpbase, 0);
907208c4 CL	92
907208c4 CL	93	/* Disable transmitter/receiver. */
ba3da734	94	clrbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4 CL	95
907208c4 CL	96	/* Enable SDMA. */
ba3da734	97	out_be32(&im->im_siu_conf.sc_sdcr, 1);
907208c4 CL	98
907208c4 CL	99	/* clear error conditions */
ba3da734	100	out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR);
907208c4 CL	101
907208c4 CL	102	/* clear SDMA interrupt mask */
ba3da734	103	out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR);
907208c4	104
ba3da734 CL	105	/* Use Port B for SMCx instead of other functions. */
	106	setbits_be32(&cp->cp_pbpar, IOPINS);
	107	clrbits_be32(&cp->cp_pbdir, IOPINS);
	108	clrbits_be16(&cp->cp_pbodr, IOPINS);
907208c4 CL	109
	110	/* Set the physical address of the host memory buffers in
	111	* the buffer descriptors.
	112	*/
ba3da734	113	rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE];
907208c4 CL	114	/* Allocate space for two buffer descriptors in the DP ram.
	115	* For now, this address seems OK, but it may have to
	116	* change with newer versions of the firmware.
	117	* damm: allocating space after the two buffers for rx/tx data
	118	*/
	119
ba3da734 CL	120	out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf);
ba3da734 CL	121	out_be16(&rtx->rxbd.cbd_sc, 0);
907208c4	122
ba3da734 CL	123	out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf);
ba3da734 CL	124	out_be16(&rtx->txbd.cbd_sc, 0);
907208c4 CL	125
907208c4 CL	126	/* Set up the uart parameters in the parameter ram. */
ba3da734 CL	127	out_be16(&up->smc_rbase, CPM_SERIAL_BASE);
	128	out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t));
	129	out_8(&up->smc_rfcr, SMC_EB);
	130	out_8(&up->smc_tfcr, SMC_EB);
907208c4 CL	131
	132	/* Set UART mode, 8 bit, no parity, one stop.
	133	* Enable receive and transmit.
	134	*/
ba3da734	135	out_be16(&sp->smc_smcmr, smcr_mk_clen(9) \| SMCMR_SM_UART);
907208c4 CL	136
	137	/* Mask all interrupts and remove anything pending.
	138	*/
ba3da734 CL	139	out_8(&sp->smc_smcm, 0);
ba3da734 CL	140	out_8(&sp->smc_smce, 0xff);
907208c4 CL	141
907208c4 CL	142	/* Set up the baud rate generator */
70fd0710	143	smc_setbrg();
907208c4 CL	144
907208c4 CL	145	/* Make the first buffer the only buffer. */
ba3da734 CL	146	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP);
ba3da734 CL	147	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY \| BD_SC_WRAP);
907208c4 CL	148
907208c4 CL	149	/* single/multi character receive. */
ba3da734 CL	150	out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN);
	151	out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE);
	152	out_be32(&rtx->rxindex, 0);
907208c4 CL	153
907208c4 CL	154	/* Initialize Tx/Rx parameters. */
ba3da734 CL	155	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
ba3da734 CL	156	;
907208c4	157
ba3da734 CL	158	out_be16(&cp->cp_cpcr,
ba3da734 CL	159	mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) \| CPM_CR_FLG);
907208c4	160
ba3da734 CL	161	while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */
ba3da734 CL	162	;
907208c4 CL	163
907208c4 CL	164	/* Enable transmitter/receiver. */
ba3da734	165	setbits_be16(&sp->smc_smcmr, SMCMR_REN \| SMCMR_TEN);
907208c4	166
70fd0710	167	return 0;
907208c4 CL	168	}
907208c4 CL	169
70fd0710	170	static void smc_putc(const char c)
907208c4	171	{
ba3da734 CL	172	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	173	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	174	struct serialbuffer __iomem *rtx;
907208c4 CL	175
907208c4 CL	176	if (c == '\n')
70fd0710	177	smc_putc('\r');
907208c4	178
ba3da734	179	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4 CL	180
907208c4 CL	181	/* Wait for last character to go. */
ba3da734 CL	182	out_8(&rtx->txbuf, c);
	183	out_be16(&rtx->txbd.cbd_datlen, 1);
	184	setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
907208c4	185
ba3da734	186	while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
70fd0710	187	WATCHDOG_RESET();
907208c4 CL	188	}
907208c4 CL	189
70fd0710	190	static void smc_puts(const char *s)
907208c4	191	{
70fd0710 CL	192	while (*s)
70fd0710 CL	193	smc_putc(*s++);
907208c4 CL	194	}
907208c4 CL	195
70fd0710	196	static int smc_getc(void)
907208c4	197	{
ba3da734 CL	198	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	199	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	200	struct serialbuffer __iomem *rtx;
907208c4	201	unsigned char c;
ba3da734	202	uint rxindex;
907208c4	203
ba3da734	204	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4 CL	205
907208c4 CL	206	/* Wait for character to show up. */
ba3da734	207	while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
70fd0710	208	WATCHDOG_RESET();
907208c4 CL	209
	210	/* the characters are read one by one,
	211	* use the rxindex to know the next char to deliver
	212	*/
ba3da734 CL	213	rxindex = in_be32(&rtx->rxindex);
	214	c = in_8(rtx->rxbuf + rxindex);
	215	rxindex++;
907208c4 CL	216
907208c4 CL	217	/* check if all char are readout, then make prepare for next receive */
ba3da734 CL	218	if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) {
	219	rxindex = 0;
	220	setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY);
907208c4	221	}
ba3da734	222	out_be32(&rtx->rxindex, rxindex);
70fd0710	223	return c;
907208c4 CL	224	}
907208c4 CL	225
70fd0710	226	static int smc_tstc(void)
907208c4	227	{
ba3da734 CL	228	immap_t __iomem im = (immap_t __iomem )CONFIG_SYS_IMMR;
	229	cpm8xx_t __iomem *cpmp = &(im->im_cpm);
	230	struct serialbuffer __iomem *rtx;
907208c4	231
ba3da734	232	rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE];
907208c4	233
ba3da734	234	return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY);
907208c4 CL	235	}
907208c4 CL	236
70fd0710	237	struct serial_device serial_smc_device = {
907208c4 CL	238	.name = "serial_smc",
	239	.start = smc_init,
	240	.stop = NULL,
	241	.setbrg = smc_setbrg,
	242	.getc = smc_getc,
	243	.tstc = smc_tstc,
	244	.putc = smc_putc,
	245	.puts = smc_puts,
	246	};
	247
	248	__weak struct serial_device *default_serial_console(void)
	249	{
	250	return &serial_smc_device;
	251	}
	252
	253	void mpc8xx_serial_initialize(void)
	254	{
	255	serial_register(&serial_smc_device);
	256	}