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Commit | Line | Data |
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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * ARM Ltd. | |
7 | * Philippe Robin, <philippe.robin@arm.com> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
48d0192f | 28 | /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ |
3d3befa7 WD |
29 | |
30 | #include <common.h> | |
8b616edb | 31 | #include <watchdog.h> |
249d5219 | 32 | #include <asm/io.h> |
20c9226c | 33 | #include "serial_pl01x.h" |
3d3befa7 | 34 | |
20c9226c AE |
35 | /* |
36 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 | |
37 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 | |
38 | * Versatile PB has four UARTs. | |
39 | */ | |
3d3befa7 | 40 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
6705d81e WD |
41 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
42 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) | |
3d3befa7 | 43 | |
20c9226c AE |
44 | static void pl01x_putc (int portnum, char c); |
45 | static int pl01x_getc (int portnum); | |
46 | static int pl01x_tstc (int portnum); | |
249d5219 MW |
47 | unsigned int baudrate = CONFIG_BAUDRATE; |
48 | DECLARE_GLOBAL_DATA_PTR; | |
3d3befa7 | 49 | |
72d5e44c RV |
50 | static struct pl01x_regs *pl01x_get_regs(int portnum) |
51 | { | |
52 | return (struct pl01x_regs *) port[portnum]; | |
53 | } | |
54 | ||
48d0192f | 55 | #ifdef CONFIG_PL010_SERIAL |
3d3befa7 WD |
56 | |
57 | int serial_init (void) | |
58 | { | |
72d5e44c | 59 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
42dfe7a1 WD |
60 | unsigned int divisor; |
61 | ||
249d5219 | 62 | /* First, disable everything */ |
72d5e44c | 63 | writel(0, ®s->pl010_cr); |
42dfe7a1 | 64 | |
249d5219 MW |
65 | /* Set baud rate */ |
66 | switch (baudrate) { | |
42dfe7a1 WD |
67 | case 9600: |
68 | divisor = UART_PL010_BAUD_9600; | |
69 | break; | |
70 | ||
71 | case 19200: | |
72 | divisor = UART_PL010_BAUD_9600; | |
73 | break; | |
74 | ||
75 | case 38400: | |
76 | divisor = UART_PL010_BAUD_38400; | |
77 | break; | |
78 | ||
79 | case 57600: | |
80 | divisor = UART_PL010_BAUD_57600; | |
81 | break; | |
82 | ||
83 | case 115200: | |
84 | divisor = UART_PL010_BAUD_115200; | |
85 | break; | |
86 | ||
87 | default: | |
88 | divisor = UART_PL010_BAUD_38400; | |
89 | } | |
90 | ||
72d5e44c RV |
91 | writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); |
92 | writel(divisor & 0xff, ®s->pl010_lcrl); | |
42dfe7a1 | 93 | |
249d5219 | 94 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
72d5e44c | 95 | writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh); |
42dfe7a1 | 96 | |
249d5219 | 97 | /* Finally, enable the UART */ |
72d5e44c | 98 | writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); |
42dfe7a1 | 99 | |
20c9226c | 100 | return 0; |
3d3befa7 WD |
101 | } |
102 | ||
48d0192f | 103 | #endif /* CONFIG_PL010_SERIAL */ |
20c9226c | 104 | |
48d0192f | 105 | #ifdef CONFIG_PL011_SERIAL |
20c9226c AE |
106 | |
107 | int serial_init (void) | |
108 | { | |
72d5e44c | 109 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
20c9226c AE |
110 | unsigned int temp; |
111 | unsigned int divider; | |
112 | unsigned int remainder; | |
113 | unsigned int fraction; | |
910f1ae3 JR |
114 | unsigned int lcr; |
115 | ||
116 | #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT | |
117 | /* Empty RX fifo if necessary */ | |
118 | if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { | |
119 | while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) | |
120 | readl(®s->dr); | |
121 | } | |
122 | #endif | |
20c9226c | 123 | |
249d5219 | 124 | /* First, disable everything */ |
72d5e44c | 125 | writel(0, ®s->pl011_cr); |
20c9226c AE |
126 | |
127 | /* | |
249d5219 MW |
128 | * Set baud rate |
129 | * | |
130 | * IBRD = UART_CLK / (16 * BAUD_RATE) | |
131 | * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) | |
20c9226c | 132 | */ |
249d5219 | 133 | temp = 16 * baudrate; |
20c9226c AE |
134 | divider = CONFIG_PL011_CLOCK / temp; |
135 | remainder = CONFIG_PL011_CLOCK % temp; | |
249d5219 | 136 | temp = (8 * remainder) / baudrate; |
20c9226c AE |
137 | fraction = (temp >> 1) + (temp & 1); |
138 | ||
72d5e44c RV |
139 | writel(divider, ®s->pl011_ibrd); |
140 | writel(fraction, ®s->pl011_fbrd); | |
20c9226c | 141 | |
249d5219 | 142 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
910f1ae3 JR |
143 | lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; |
144 | writel(lcr, ®s->pl011_lcrh); | |
145 | ||
146 | #ifdef CONFIG_PL011_SERIAL_RLCR | |
147 | { | |
148 | int i; | |
149 | ||
150 | /* | |
151 | * Program receive line control register after waiting | |
152 | * 10 bus cycles. Delay be writing to readonly register | |
153 | * 10 times | |
154 | */ | |
155 | for (i = 0; i < 10; i++) | |
156 | writel(lcr, ®s->fr); | |
157 | ||
158 | writel(lcr, ®s->pl011_rlcr); | |
84dee301 MP |
159 | /* lcrh needs to be set again for change to be effective */ |
160 | writel(lcr, ®s->pl011_lcrh); | |
910f1ae3 JR |
161 | } |
162 | #endif | |
249d5219 | 163 | /* Finally, enable the UART */ |
72d5e44c RV |
164 | writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, |
165 | ®s->pl011_cr); | |
20c9226c AE |
166 | |
167 | return 0; | |
168 | } | |
169 | ||
48d0192f | 170 | #endif /* CONFIG_PL011_SERIAL */ |
20c9226c | 171 | |
42dfe7a1 | 172 | void serial_putc (const char c) |
3d3befa7 WD |
173 | { |
174 | if (c == '\n') | |
20c9226c | 175 | pl01x_putc (CONSOLE_PORT, '\r'); |
3d3befa7 | 176 | |
20c9226c | 177 | pl01x_putc (CONSOLE_PORT, c); |
3d3befa7 WD |
178 | } |
179 | ||
42dfe7a1 | 180 | void serial_puts (const char *s) |
3d3befa7 WD |
181 | { |
182 | while (*s) { | |
183 | serial_putc (*s++); | |
184 | } | |
185 | } | |
186 | ||
42dfe7a1 | 187 | int serial_getc (void) |
3d3befa7 | 188 | { |
20c9226c | 189 | return pl01x_getc (CONSOLE_PORT); |
3d3befa7 WD |
190 | } |
191 | ||
42dfe7a1 | 192 | int serial_tstc (void) |
3d3befa7 | 193 | { |
20c9226c | 194 | return pl01x_tstc (CONSOLE_PORT); |
3d3befa7 WD |
195 | } |
196 | ||
42dfe7a1 | 197 | void serial_setbrg (void) |
3d3befa7 | 198 | { |
96baa4c3 LW |
199 | struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT); |
200 | ||
249d5219 | 201 | baudrate = gd->baudrate; |
96baa4c3 LW |
202 | /* |
203 | * Flush FIFO and wait for non-busy before changing baudrate to avoid | |
204 | * crap in console | |
205 | */ | |
206 | while (!(readl(®s->fr) & UART_PL01x_FR_TXFE)) | |
207 | WATCHDOG_RESET(); | |
208 | while (readl(®s->fr) & UART_PL01x_FR_BUSY) | |
209 | WATCHDOG_RESET(); | |
249d5219 | 210 | serial_init(); |
3d3befa7 WD |
211 | } |
212 | ||
20c9226c | 213 | static void pl01x_putc (int portnum, char c) |
3d3befa7 | 214 | { |
72d5e44c RV |
215 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
216 | ||
42dfe7a1 | 217 | /* Wait until there is space in the FIFO */ |
72d5e44c | 218 | while (readl(®s->fr) & UART_PL01x_FR_TXFF) |
8b616edb | 219 | WATCHDOG_RESET(); |
42dfe7a1 WD |
220 | |
221 | /* Send the character */ | |
72d5e44c | 222 | writel(c, ®s->dr); |
3d3befa7 WD |
223 | } |
224 | ||
20c9226c | 225 | static int pl01x_getc (int portnum) |
3d3befa7 | 226 | { |
72d5e44c | 227 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
42dfe7a1 WD |
228 | unsigned int data; |
229 | ||
230 | /* Wait until there is data in the FIFO */ | |
72d5e44c | 231 | while (readl(®s->fr) & UART_PL01x_FR_RXFE) |
8b616edb | 232 | WATCHDOG_RESET(); |
42dfe7a1 | 233 | |
72d5e44c | 234 | data = readl(®s->dr); |
42dfe7a1 WD |
235 | |
236 | /* Check for an error flag */ | |
237 | if (data & 0xFFFFFF00) { | |
238 | /* Clear the error */ | |
72d5e44c | 239 | writel(0xFFFFFFFF, ®s->ecr); |
42dfe7a1 WD |
240 | return -1; |
241 | } | |
242 | ||
243 | return (int) data; | |
3d3befa7 WD |
244 | } |
245 | ||
20c9226c | 246 | static int pl01x_tstc (int portnum) |
3d3befa7 | 247 | { |
72d5e44c RV |
248 | struct pl01x_regs *regs = pl01x_get_regs(portnum); |
249 | ||
8b616edb | 250 | WATCHDOG_RESET(); |
72d5e44c | 251 | return !(readl(®s->fr) & UART_PL01x_FR_RXFE); |
3d3befa7 | 252 | } |