]>
Commit | Line | Data |
---|---|---|
3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * ARM Ltd. | |
7 | * Philippe Robin, <philippe.robin@arm.com> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | /* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ | |
29 | /* Should be fairly simple to make it work with the PL010 as well */ | |
30 | ||
31 | #include <common.h> | |
8b616edb | 32 | #include <watchdog.h> |
3d3befa7 | 33 | |
20c9226c | 34 | #if defined(CFG_PL010_SERIAL) || defined(CFG_PL011_SERIAL) |
3d3befa7 | 35 | |
20c9226c | 36 | #include "serial_pl01x.h" |
3d3befa7 WD |
37 | |
38 | #define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) | |
39 | #define IO_READ(addr) (*(volatile unsigned int *)(addr)) | |
40 | ||
20c9226c AE |
41 | /* |
42 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 | |
43 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 | |
44 | * Versatile PB has four UARTs. | |
45 | */ | |
3d3befa7 WD |
46 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
47 | #define baudRate CONFIG_BAUDRATE | |
6705d81e WD |
48 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
49 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) | |
3d3befa7 | 50 | |
20c9226c AE |
51 | static void pl01x_putc (int portnum, char c); |
52 | static int pl01x_getc (int portnum); | |
53 | static int pl01x_tstc (int portnum); | |
3d3befa7 | 54 | |
20c9226c | 55 | #ifdef CFG_PL010_SERIAL |
3d3befa7 WD |
56 | |
57 | int serial_init (void) | |
58 | { | |
42dfe7a1 WD |
59 | unsigned int divisor; |
60 | ||
61 | /* | |
62 | ** First, disable everything. | |
63 | */ | |
64 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); | |
65 | ||
66 | /* | |
67 | ** Set baud rate | |
68 | ** | |
69 | */ | |
70 | switch (baudRate) { | |
71 | case 9600: | |
72 | divisor = UART_PL010_BAUD_9600; | |
73 | break; | |
74 | ||
75 | case 19200: | |
76 | divisor = UART_PL010_BAUD_9600; | |
77 | break; | |
78 | ||
79 | case 38400: | |
80 | divisor = UART_PL010_BAUD_38400; | |
81 | break; | |
82 | ||
83 | case 57600: | |
84 | divisor = UART_PL010_BAUD_57600; | |
85 | break; | |
86 | ||
87 | case 115200: | |
88 | divisor = UART_PL010_BAUD_115200; | |
89 | break; | |
90 | ||
91 | default: | |
92 | divisor = UART_PL010_BAUD_38400; | |
93 | } | |
94 | ||
95 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, | |
96 | ((divisor & 0xf00) >> 8)); | |
97 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); | |
98 | ||
99 | /* | |
100 | ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. | |
101 | */ | |
102 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, | |
103 | (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); | |
104 | ||
105 | /* | |
106 | ** Finally, enable the UART | |
107 | */ | |
108 | IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); | |
109 | ||
20c9226c | 110 | return 0; |
3d3befa7 WD |
111 | } |
112 | ||
20c9226c AE |
113 | #endif /* CFG_PL010_SERIAL */ |
114 | ||
115 | #ifdef CFG_PL011_SERIAL | |
116 | ||
117 | int serial_init (void) | |
118 | { | |
119 | unsigned int temp; | |
120 | unsigned int divider; | |
121 | unsigned int remainder; | |
122 | unsigned int fraction; | |
123 | ||
124 | /* | |
125 | ** First, disable everything. | |
126 | */ | |
127 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); | |
128 | ||
129 | /* | |
130 | ** Set baud rate | |
131 | ** | |
132 | ** IBRD = UART_CLK / (16 * BAUD_RATE) | |
133 | ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) | |
134 | */ | |
135 | temp = 16 * baudRate; | |
136 | divider = CONFIG_PL011_CLOCK / temp; | |
137 | remainder = CONFIG_PL011_CLOCK % temp; | |
138 | temp = (8 * remainder) / baudRate; | |
139 | fraction = (temp >> 1) + (temp & 1); | |
140 | ||
141 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); | |
142 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); | |
143 | ||
144 | /* | |
145 | ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. | |
146 | */ | |
147 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, | |
148 | (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); | |
149 | ||
150 | /* | |
151 | ** Finally, enable the UART | |
152 | */ | |
153 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, | |
154 | (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | | |
155 | UART_PL011_CR_RXE)); | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
160 | #endif /* CFG_PL011_SERIAL */ | |
161 | ||
42dfe7a1 | 162 | void serial_putc (const char c) |
3d3befa7 WD |
163 | { |
164 | if (c == '\n') | |
20c9226c | 165 | pl01x_putc (CONSOLE_PORT, '\r'); |
3d3befa7 | 166 | |
20c9226c | 167 | pl01x_putc (CONSOLE_PORT, c); |
3d3befa7 WD |
168 | } |
169 | ||
42dfe7a1 | 170 | void serial_puts (const char *s) |
3d3befa7 WD |
171 | { |
172 | while (*s) { | |
173 | serial_putc (*s++); | |
174 | } | |
175 | } | |
176 | ||
42dfe7a1 | 177 | int serial_getc (void) |
3d3befa7 | 178 | { |
20c9226c | 179 | return pl01x_getc (CONSOLE_PORT); |
3d3befa7 WD |
180 | } |
181 | ||
42dfe7a1 | 182 | int serial_tstc (void) |
3d3befa7 | 183 | { |
20c9226c | 184 | return pl01x_tstc (CONSOLE_PORT); |
3d3befa7 WD |
185 | } |
186 | ||
42dfe7a1 | 187 | void serial_setbrg (void) |
3d3befa7 WD |
188 | { |
189 | } | |
190 | ||
20c9226c | 191 | static void pl01x_putc (int portnum, char c) |
3d3befa7 | 192 | { |
42dfe7a1 | 193 | /* Wait until there is space in the FIFO */ |
8b616edb SW |
194 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) |
195 | WATCHDOG_RESET(); | |
42dfe7a1 WD |
196 | |
197 | /* Send the character */ | |
198 | IO_WRITE (port[portnum] + UART_PL01x_DR, c); | |
3d3befa7 WD |
199 | } |
200 | ||
20c9226c | 201 | static int pl01x_getc (int portnum) |
3d3befa7 | 202 | { |
42dfe7a1 WD |
203 | unsigned int data; |
204 | ||
205 | /* Wait until there is data in the FIFO */ | |
8b616edb SW |
206 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) |
207 | WATCHDOG_RESET(); | |
42dfe7a1 WD |
208 | |
209 | data = IO_READ (port[portnum] + UART_PL01x_DR); | |
210 | ||
211 | /* Check for an error flag */ | |
212 | if (data & 0xFFFFFF00) { | |
213 | /* Clear the error */ | |
214 | IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); | |
215 | return -1; | |
216 | } | |
217 | ||
218 | return (int) data; | |
3d3befa7 WD |
219 | } |
220 | ||
20c9226c | 221 | static int pl01x_tstc (int portnum) |
3d3befa7 | 222 | { |
8b616edb | 223 | WATCHDOG_RESET(); |
42dfe7a1 WD |
224 | return !(IO_READ (port[portnum] + UART_PL01x_FR) & |
225 | UART_PL01x_FR_RXFE); | |
3d3befa7 WD |
226 | } |
227 | ||
228 | #endif |