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dd2c9e6a MK |
1 | /* |
2 | * (C) Copyright 2009 SAMSUNG Electronics | |
3 | * Minkyu Kang <mk7.kang@samsung.com> | |
4 | * Heungjun Kim <riverful.kim@samsung.com> | |
5 | * | |
6 | * based on drivers/serial/s3c64xx.c | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
dd2c9e6a MK |
9 | */ |
10 | ||
11 | #include <common.h> | |
73e256c2 SG |
12 | #include <dm.h> |
13 | #include <errno.h> | |
d4ec8f08 | 14 | #include <fdtdec.h> |
6c768ca7 | 15 | #include <linux/compiler.h> |
dd2c9e6a MK |
16 | #include <asm/io.h> |
17 | #include <asm/arch/uart.h> | |
18 | #include <asm/arch/clk.h> | |
19 | #include <serial.h> | |
20 | ||
29565326 JR |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
73e256c2 SG |
23 | #define RX_FIFO_COUNT_SHIFT 0 |
24 | #define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT) | |
25 | #define RX_FIFO_FULL (1 << 8) | |
26 | #define TX_FIFO_COUNT_SHIFT 16 | |
27 | #define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT) | |
28 | #define TX_FIFO_FULL (1 << 24) | |
ffbff1dd | 29 | |
d4ec8f08 | 30 | /* Information about a serial port */ |
73e256c2 SG |
31 | struct s5p_serial_platdata { |
32 | struct s5p_uart *reg; /* address of registers in physical memory */ | |
d4ec8f08 | 33 | u8 port_id; /* uart port number */ |
73e256c2 | 34 | }; |
dd2c9e6a MK |
35 | |
36 | /* | |
46a3b5c8 | 37 | * The coefficient, used to calculate the baudrate on S5P UARTs is |
dd2c9e6a MK |
38 | * calculated as |
39 | * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT | |
40 | * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, | |
41 | * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: | |
42 | */ | |
43 | static const int udivslot[] = { | |
44 | 0, | |
45 | 0x0080, | |
46 | 0x0808, | |
47 | 0x0888, | |
48 | 0x2222, | |
49 | 0x4924, | |
50 | 0x4a52, | |
51 | 0x54aa, | |
52 | 0x5555, | |
53 | 0xd555, | |
54 | 0xd5d5, | |
55 | 0xddd5, | |
56 | 0xdddd, | |
57 | 0xdfdd, | |
58 | 0xdfdf, | |
59 | 0xffdf, | |
60 | }; | |
61 | ||
73e256c2 | 62 | int s5p_serial_setbrg(struct udevice *dev, int baudrate) |
dd2c9e6a | 63 | { |
73e256c2 SG |
64 | struct s5p_serial_platdata *plat = dev->platdata; |
65 | struct s5p_uart *const uart = plat->reg; | |
66 | u32 uclk = get_uart_clk(plat->port_id); | |
dd2c9e6a MK |
67 | u32 val; |
68 | ||
f70409af | 69 | val = uclk / baudrate; |
dd2c9e6a MK |
70 | |
71 | writel(val / 16 - 1, &uart->ubrdiv); | |
1628cfc4 | 72 | |
e0617c62 | 73 | if (s5p_uart_divslot()) |
1628cfc4 MK |
74 | writew(udivslot[val % 16], &uart->rest.slot); |
75 | else | |
76 | writeb(val % 16, &uart->rest.value); | |
73e256c2 SG |
77 | |
78 | return 0; | |
dd2c9e6a MK |
79 | } |
80 | ||
73e256c2 | 81 | static int s5p_serial_probe(struct udevice *dev) |
dd2c9e6a | 82 | { |
73e256c2 SG |
83 | struct s5p_serial_platdata *plat = dev->platdata; |
84 | struct s5p_uart *const uart = plat->reg; | |
dd2c9e6a | 85 | |
e6252fab IS |
86 | /* enable FIFOs, auto clear Rx FIFO */ |
87 | writel(0x3, &uart->ufcon); | |
dd2c9e6a MK |
88 | writel(0, &uart->umcon); |
89 | /* 8N1 */ | |
90 | writel(0x3, &uart->ulcon); | |
91 | /* No interrupts, no DMA, pure polling */ | |
92 | writel(0x245, &uart->ucon); | |
93 | ||
dd2c9e6a MK |
94 | return 0; |
95 | } | |
96 | ||
73e256c2 | 97 | static int serial_err_check(const struct s5p_uart *const uart, int op) |
dd2c9e6a | 98 | { |
94003226 MK |
99 | unsigned int mask; |
100 | ||
101 | /* | |
102 | * UERSTAT | |
103 | * Break Detect [3] | |
104 | * Frame Err [2] : receive operation | |
105 | * Parity Err [1] : receive operation | |
106 | * Overrun Err [0] : receive operation | |
107 | */ | |
108 | if (op) | |
109 | mask = 0x8; | |
110 | else | |
111 | mask = 0xf; | |
dd2c9e6a | 112 | |
94003226 | 113 | return readl(&uart->uerstat) & mask; |
dd2c9e6a MK |
114 | } |
115 | ||
73e256c2 | 116 | static int s5p_serial_getc(struct udevice *dev) |
dd2c9e6a | 117 | { |
73e256c2 SG |
118 | struct s5p_serial_platdata *plat = dev->platdata; |
119 | struct s5p_uart *const uart = plat->reg; | |
d4ec8f08 | 120 | |
73e256c2 SG |
121 | if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK)) |
122 | return -EAGAIN; | |
dd2c9e6a | 123 | |
73e256c2 | 124 | serial_err_check(uart, 0); |
1a4106dd | 125 | return (int)(readb(&uart->urxh) & 0xff); |
dd2c9e6a MK |
126 | } |
127 | ||
73e256c2 | 128 | static int s5p_serial_putc(struct udevice *dev, const char ch) |
dd2c9e6a | 129 | { |
73e256c2 SG |
130 | struct s5p_serial_platdata *plat = dev->platdata; |
131 | struct s5p_uart *const uart = plat->reg; | |
dd2c9e6a | 132 | |
73e256c2 SG |
133 | if (readl(&uart->ufstat) & TX_FIFO_FULL) |
134 | return -EAGAIN; | |
dd2c9e6a | 135 | |
73e256c2 SG |
136 | writeb(ch, &uart->utxh); |
137 | serial_err_check(uart, 1); | |
dd2c9e6a | 138 | |
73e256c2 | 139 | return 0; |
dd2c9e6a MK |
140 | } |
141 | ||
73e256c2 | 142 | static int s5p_serial_pending(struct udevice *dev, bool input) |
dd2c9e6a | 143 | { |
73e256c2 SG |
144 | struct s5p_serial_platdata *plat = dev->platdata; |
145 | struct s5p_uart *const uart = plat->reg; | |
146 | uint32_t ufstat = readl(&uart->ufstat); | |
dd2c9e6a | 147 | |
73e256c2 SG |
148 | if (input) |
149 | return (ufstat & RX_FIFO_COUNT_MASK) >> RX_FIFO_COUNT_SHIFT; | |
150 | else | |
151 | return (ufstat & TX_FIFO_COUNT_MASK) >> TX_FIFO_COUNT_SHIFT; | |
90bad891 | 152 | } |
dd2c9e6a | 153 | |
73e256c2 | 154 | static int s5p_serial_ofdata_to_platdata(struct udevice *dev) |
d4ec8f08 | 155 | { |
73e256c2 SG |
156 | struct s5p_serial_platdata *plat = dev->platdata; |
157 | fdt_addr_t addr; | |
d4ec8f08 | 158 | |
73e256c2 SG |
159 | addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); |
160 | if (addr == FDT_ADDR_T_NONE) | |
161 | return -EINVAL; | |
d4ec8f08 | 162 | |
73e256c2 SG |
163 | plat->reg = (struct s5p_uart *)addr; |
164 | plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1); | |
d4ec8f08 RS |
165 | |
166 | return 0; | |
167 | } | |
d4ec8f08 | 168 | |
73e256c2 SG |
169 | static const struct dm_serial_ops s5p_serial_ops = { |
170 | .putc = s5p_serial_putc, | |
171 | .pending = s5p_serial_pending, | |
172 | .getc = s5p_serial_getc, | |
173 | .setbrg = s5p_serial_setbrg, | |
174 | }; | |
b4980515 | 175 | |
73e256c2 SG |
176 | static const struct udevice_id s5p_serial_ids[] = { |
177 | { .compatible = "samsung,exynos4210-uart" }, | |
178 | { } | |
179 | }; | |
180 | ||
181 | U_BOOT_DRIVER(serial_s5p) = { | |
182 | .name = "serial_s5p", | |
183 | .id = UCLASS_SERIAL, | |
184 | .of_match = s5p_serial_ids, | |
185 | .ofdata_to_platdata = s5p_serial_ofdata_to_platdata, | |
186 | .platdata_auto_alloc_size = sizeof(struct s5p_serial_platdata), | |
187 | .probe = s5p_serial_probe, | |
188 | .ops = &s5p_serial_ops, | |
189 | .flags = DM_FLAG_PRE_RELOC, | |
190 | }; |