[people/ms/u-boot.git] / drivers / serial / serial_sh.c

/*
 * SuperH SCIF device driver.
 * Copyright (C) 2013  Renesas Electronics Corporation
 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
 * Copyright (C) 2002 - 2008  Paul Mundt
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <errno.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <serial.h>
#include <linux/compiler.h>
#include <dm/platform_data/serial_sh.h>
#include "serial_sh.h"

#if defined(CONFIG_CPU_SH7760) || \
	defined(CONFIG_CPU_SH7780) || \
	defined(CONFIG_CPU_SH7785) || \
	defined(CONFIG_CPU_SH7786)
static int scif_rxfill(struct uart_port *port)
{
	return sci_in(port, SCRFDR) & 0xff;
}
#elif defined(CONFIG_CPU_SH7763)
static int scif_rxfill(struct uart_port *port)
{
	if ((port->mapbase == 0xffe00000) ||
	    (port->mapbase == 0xffe08000)) {
		/* SCIF0/1*/
		return sci_in(port, SCRFDR) & 0xff;
	} else {
		/* SCIF2 */
		return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
	}
}
#elif defined(CONFIG_ARCH_SH7372)
static int scif_rxfill(struct uart_port *port)
{
	if (port->type == PORT_SCIFA)
		return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
	else
		return sci_in(port, SCRFDR);
}
#else
static int scif_rxfill(struct uart_port *port)
{
	return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
}
#endif

static void sh_serial_init_generic(struct uart_port *port)
{
	sci_out(port, SCSCR , SCSCR_INIT(port));
	sci_out(port, SCSCR , SCSCR_INIT(port));
	sci_out(port, SCSMR, 0);
	sci_out(port, SCSMR, 0);
	sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
	sci_in(port, SCFCR);
	sci_out(port, SCFCR, 0);
}

static void
sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
{
	if (port->clk_mode == EXT_CLK) {
		unsigned short dl = DL_VALUE(baudrate, clk);
		sci_out(port, DL, dl);
		/* Need wait: Clock * 1/dl * 1/16 */
		udelay((1000000 * dl * 16 / clk) * 1000 + 1);
	} else {
		sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
	}
}

static void handle_error(struct uart_port *port)
{
	sci_in(port, SCxSR);
	sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
	sci_in(port, SCLSR);
	sci_out(port, SCLSR, 0x00);
}

static int serial_raw_putc(struct uart_port *port, const char c)
{
	/* Tx fifo is empty */
	if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
		return -EAGAIN;

	sci_out(port, SCxTDR, c);
	sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));

	return 0;
}

static int serial_rx_fifo_level(struct uart_port *port)
{
	return scif_rxfill(port);
}

static int sh_serial_tstc_generic(struct uart_port *port)
{
	if (sci_in(port, SCxSR) & SCIF_ERRORS) {
		handle_error(port);
		return 0;
	}

	return serial_rx_fifo_level(port) ? 1 : 0;
}

static int serial_getc_check(struct uart_port *port)
{
	unsigned short status;

	status = sci_in(port, SCxSR);

	if (status & SCIF_ERRORS)
		handle_error(port);
	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
		handle_error(port);
	return status & (SCIF_DR | SCxSR_RDxF(port));
}

static int sh_serial_getc_generic(struct uart_port *port)
{
	unsigned short status;
	char ch;

	if (!serial_getc_check(port))
		return -EAGAIN;

	ch = sci_in(port, SCxRDR);
	status = sci_in(port, SCxSR);

	sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));

	if (status & SCIF_ERRORS)
		handle_error(port);

	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
		handle_error(port);

	return ch;
}

#ifdef CONFIG_DM_SERIAL

static int sh_serial_pending(struct udevice *dev, bool input)
{
	struct uart_port *priv = dev_get_priv(dev);

	return sh_serial_tstc_generic(priv);
}

static int sh_serial_putc(struct udevice *dev, const char ch)
{
	struct uart_port *priv = dev_get_priv(dev);

	return serial_raw_putc(priv, ch);
}

static int sh_serial_getc(struct udevice *dev)
{
	struct uart_port *priv = dev_get_priv(dev);

	return sh_serial_getc_generic(priv);
}

static int sh_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct sh_serial_platdata *plat = dev_get_platdata(dev);
	struct uart_port *priv = dev_get_priv(dev);

	sh_serial_setbrg_generic(priv, plat->clk, baudrate);

	return 0;
}

static int sh_serial_probe(struct udevice *dev)
{
	struct sh_serial_platdata *plat = dev_get_platdata(dev);
	struct uart_port *priv = dev_get_priv(dev);

	priv->membase	= (unsigned char *)plat->base;
	priv->mapbase	= plat->base;
	priv->type	= plat->type;
	priv->clk_mode	= plat->clk_mode;

	sh_serial_init_generic(priv);

	return 0;
}

static const struct dm_serial_ops sh_serial_ops = {
	.putc = sh_serial_putc,
	.pending = sh_serial_pending,
	.getc = sh_serial_getc,
	.setbrg = sh_serial_setbrg,
};

U_BOOT_DRIVER(serial_sh) = {
	.name	= "serial_sh",
	.id	= UCLASS_SERIAL,
	.probe	= sh_serial_probe,
	.ops	= &sh_serial_ops,
	.flags	= DM_FLAG_PRE_RELOC,
	.priv_auto_alloc_size = sizeof(struct uart_port),
};

#else /* CONFIG_DM_SERIAL */

#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE	SCIF0_BASE
#elif defined(CONFIG_CONS_SCIF1)
# define SCIF_BASE	SCIF1_BASE
#elif defined(CONFIG_CONS_SCIF2)
# define SCIF_BASE	SCIF2_BASE
#elif defined(CONFIG_CONS_SCIF3)
# define SCIF_BASE	SCIF3_BASE
#elif defined(CONFIG_CONS_SCIF4)
# define SCIF_BASE	SCIF4_BASE
#elif defined(CONFIG_CONS_SCIF5)
# define SCIF_BASE	SCIF5_BASE
#elif defined(CONFIG_CONS_SCIF6)
# define SCIF_BASE	SCIF6_BASE
#elif defined(CONFIG_CONS_SCIF7)
# define SCIF_BASE	SCIF7_BASE
#else
# error "Default SCIF doesn't set....."
#endif

#if defined(CONFIG_SCIF_A)
	#define SCIF_BASE_PORT	PORT_SCIFA
#else
	#define SCIF_BASE_PORT	PORT_SCIF
#endif

static struct uart_port sh_sci = {
	.membase	= (unsigned char *)SCIF_BASE,
	.mapbase	= SCIF_BASE,
	.type		= SCIF_BASE_PORT,
#ifdef CONFIG_SCIF_USE_EXT_CLK
	.clk_mode =	EXT_CLK,
#endif
};

static void sh_serial_setbrg(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	struct uart_port *port = &sh_sci;

	sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
}

static int sh_serial_init(void)
{
	struct uart_port *port = &sh_sci;

	sh_serial_init_generic(port);
	serial_setbrg();

	return 0;
}

static void sh_serial_putc(const char c)
{
	struct uart_port *port = &sh_sci;

	if (c == '\n') {
		while (1) {
			if  (serial_raw_putc(port, '\r') != -EAGAIN)
				break;
		}
	}
	while (1) {
		if  (serial_raw_putc(port, c) != -EAGAIN)
			break;
	}
}

static int sh_serial_tstc(void)
{
	struct uart_port *port = &sh_sci;

	return sh_serial_tstc_generic(port);
}

static int sh_serial_getc(void)
{
	struct uart_port *port = &sh_sci;
	int ch;

	while (1) {
		ch = sh_serial_getc_generic(port);
		if (ch != -EAGAIN)
			break;
	}

	return ch;
}

static struct serial_device sh_serial_drv = {
	.name	= "sh_serial",
	.start	= sh_serial_init,
	.stop	= NULL,
	.setbrg	= sh_serial_setbrg,
	.putc	= sh_serial_putc,
	.puts	= default_serial_puts,
	.getc	= sh_serial_getc,
	.tstc	= sh_serial_tstc,
};

void sh_serial_initialize(void)
{
	serial_register(&sh_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &sh_serial_drv;
}
#endif /* CONFIG_DM_SERIAL */
Commit	Line	Data
0b135cfc NI	1	/*
0b135cfc NI	2	* SuperH SCIF device driver.
48ca882c	3	* Copyright (C) 2013 Renesas Electronics Corporation
59088e4a	4	* Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
3f6c8e36	5	* Copyright (C) 2002 - 2008 Paul Mundt
61fb15c5	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
0b135cfc NI	8	*/
	9
	10	#include <common.h>
59088e4a NI	11	#include <errno.h>
59088e4a NI	12	#include <dm.h>
fc83c927	13	#include <asm/io.h>
0b135cfc	14	#include <asm/processor.h>
8bdd7efa MV	15	#include <serial.h>
8bdd7efa MV	16	#include <linux/compiler.h>
59088e4a NI	17	#include <dm/platform_data/serial_sh.h>
59088e4a NI	18	#include "serial_sh.h"
0b135cfc	19
3f6c8e36 NI	20	#if defined(CONFIG_CPU_SH7760) \|\| \
	21	defined(CONFIG_CPU_SH7780) \|\| \
	22	defined(CONFIG_CPU_SH7785) \|\| \
	23	defined(CONFIG_CPU_SH7786)
	24	static int scif_rxfill(struct uart_port *port)
	25	{
	26	return sci_in(port, SCRFDR) & 0xff;
	27	}
	28	#elif defined(CONFIG_CPU_SH7763)
	29	static int scif_rxfill(struct uart_port *port)
0b135cfc	30	{
3f6c8e36	31	if ((port->mapbase == 0xffe00000) \|\|
59088e4a	32	(port->mapbase == 0xffe08000)) {
3f6c8e36 NI	33	/* SCIF0/1*/
	34	return sci_in(port, SCRFDR) & 0xff;
	35	} else {
	36	/* SCIF2 */
	37	return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
	38	}
	39	}
	40	#elif defined(CONFIG_ARCH_SH7372)
	41	static int scif_rxfill(struct uart_port *port)
	42	{
	43	if (port->type == PORT_SCIFA)
	44	return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
	45	else
	46	return sci_in(port, SCRFDR);
	47	}
3ecff1d7	48	#else
3f6c8e36 NI	49	static int scif_rxfill(struct uart_port *port)
	50	{
	51	return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
	52	}
3ecff1d7	53	#endif
3f6c8e36	54
59088e4a	55	static void sh_serial_init_generic(struct uart_port *port)
3f6c8e36	56	{
59088e4a NI	57	sci_out(port, SCSCR , SCSCR_INIT(port));
	58	sci_out(port, SCSCR , SCSCR_INIT(port));
	59	sci_out(port, SCSMR, 0);
	60	sci_out(port, SCSMR, 0);
	61	sci_out(port, SCFCR, SCFCR_RFRST\|SCFCR_TFRST);
	62	sci_in(port, SCFCR);
	63	sci_out(port, SCFCR, 0);
0b135cfc NI	64	}
0b135cfc NI	65
59088e4a NI	66	static void
59088e4a NI	67	sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
7c791b3f	68	{
59088e4a NI	69	if (port->clk_mode == EXT_CLK) {
	70	unsigned short dl = DL_VALUE(baudrate, clk);
	71	sci_out(port, DL, dl);
89f99a62	72	/* Need wait: Clock * 1/dl * 1/16 */
59088e4a NI	73	udelay((1000000 * dl * 16 / clk) * 1000 + 1);
	74	} else {
	75	sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
	76	}
7c791b3f TK	77	}
7c791b3f TK	78
59088e4a	79	static void handle_error(struct uart_port *port)
0b135cfc	80	{
59088e4a NI	81	sci_in(port, SCxSR);
	82	sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
	83	sci_in(port, SCLSR);
	84	sci_out(port, SCLSR, 0x00);
	85	}
	86
	87	static int serial_raw_putc(struct uart_port *port, const char c)
	88	{
	89	/* Tx fifo is empty */
	90	if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
	91	return -EAGAIN;
0b135cfc	92
59088e4a NI	93	sci_out(port, SCxTDR, c);
	94	sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
	95
	96	return 0;
0b135cfc NI	97	}
0b135cfc NI	98
59088e4a	99	static int serial_rx_fifo_level(struct uart_port *port)
0b135cfc	100	{
59088e4a	101	return scif_rxfill(port);
0b135cfc NI	102	}
0b135cfc NI	103
59088e4a	104	static int sh_serial_tstc_generic(struct uart_port *port)
0b135cfc	105	{
59088e4a NI	106	if (sci_in(port, SCxSR) & SCIF_ERRORS) {
59088e4a NI	107	handle_error(port);
7c791b3f TK	108	return 0;
	109	}
	110
59088e4a	111	return serial_rx_fifo_level(port) ? 1 : 0;
0b135cfc NI	112	}
0b135cfc NI	113
59088e4a	114	static int serial_getc_check(struct uart_port *port)
08c5fabe	115	{
0b135cfc NI	116	unsigned short status;
0b135cfc NI	117
59088e4a	118	status = sci_in(port, SCxSR);
0b135cfc	119
3f6c8e36	120	if (status & SCIF_ERRORS)
59088e4a NI	121	handle_error(port);
	122	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
	123	handle_error(port);
	124	return status & (SCIF_DR \| SCxSR_RDxF(port));
0b135cfc NI	125	}
0b135cfc NI	126
59088e4a	127	static int sh_serial_getc_generic(struct uart_port *port)
0b135cfc	128	{
08c5fabe	129	unsigned short status;
0b135cfc	130	char ch;
ab09f433	131
59088e4a NI	132	if (!serial_getc_check(port))
59088e4a NI	133	return -EAGAIN;
0b135cfc	134
59088e4a NI	135	ch = sci_in(port, SCxRDR);
59088e4a NI	136	status = sci_in(port, SCxSR);
0b135cfc	137
59088e4a	138	sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
0b135cfc	139
3f6c8e36	140	if (status & SCIF_ERRORS)
59088e4a NI	141	handle_error(port);
	142
	143	if (sci_in(port, SCLSR) & SCxSR_ORER(port))
	144	handle_error(port);
	145
	146	return ch;
	147	}
	148
	149	#ifdef CONFIG_DM_SERIAL
	150
	151	static int sh_serial_pending(struct udevice *dev, bool input)
	152	{
	153	struct uart_port *priv = dev_get_priv(dev);
	154
	155	return sh_serial_tstc_generic(priv);
	156	}
	157
	158	static int sh_serial_putc(struct udevice *dev, const char ch)
	159	{
	160	struct uart_port *priv = dev_get_priv(dev);
	161
	162	return serial_raw_putc(priv, ch);
	163	}
	164
	165	static int sh_serial_getc(struct udevice *dev)
	166	{
	167	struct uart_port *priv = dev_get_priv(dev);
	168
	169	return sh_serial_getc_generic(priv);
	170	}
	171
	172	static int sh_serial_setbrg(struct udevice *dev, int baudrate)
	173	{
	174	struct sh_serial_platdata *plat = dev_get_platdata(dev);
	175	struct uart_port *priv = dev_get_priv(dev);
	176
	177	sh_serial_setbrg_generic(priv, plat->clk, baudrate);
	178
	179	return 0;
	180	}
	181
	182	static int sh_serial_probe(struct udevice *dev)
	183	{
	184	struct sh_serial_platdata *plat = dev_get_platdata(dev);
	185	struct uart_port *priv = dev_get_priv(dev);
	186
	187	priv->membase = (unsigned char *)plat->base;
	188	priv->mapbase = plat->base;
	189	priv->type = plat->type;
	190	priv->clk_mode = plat->clk_mode;
	191
	192	sh_serial_init_generic(priv);
	193
	194	return 0;
	195	}
	196
	197	static const struct dm_serial_ops sh_serial_ops = {
	198	.putc = sh_serial_putc,
	199	.pending = sh_serial_pending,
	200	.getc = sh_serial_getc,
	201	.setbrg = sh_serial_setbrg,
	202	};
	203
	204	U_BOOT_DRIVER(serial_sh) = {
205	.name = "serial_sh",
206	.id = UCLASS_SERIAL,
207	.probe = sh_serial_probe,
208	.ops = &sh_serial_ops,
209	.flags = DM_FLAG_PRE_RELOC,
210	.priv_auto_alloc_size = sizeof(struct uart_port),
211	};
212
213	#else /* CONFIG_DM_SERIAL */
214
215	#if defined(CONFIG_CONS_SCIF0)
216	# define SCIF_BASE SCIF0_BASE
217	#elif defined(CONFIG_CONS_SCIF1)
218	# define SCIF_BASE SCIF1_BASE
219	#elif defined(CONFIG_CONS_SCIF2)
220	# define SCIF_BASE SCIF2_BASE
221	#elif defined(CONFIG_CONS_SCIF3)
222	# define SCIF_BASE SCIF3_BASE
223	#elif defined(CONFIG_CONS_SCIF4)
224	# define SCIF_BASE SCIF4_BASE
225	#elif defined(CONFIG_CONS_SCIF5)
226	# define SCIF_BASE SCIF5_BASE
227	#elif defined(CONFIG_CONS_SCIF6)
228	# define SCIF_BASE SCIF6_BASE
229	#elif defined(CONFIG_CONS_SCIF7)
230	# define SCIF_BASE SCIF7_BASE
231	#else
232	# error "Default SCIF doesn't set....."
233	#endif
234
235	#if defined(CONFIG_SCIF_A)
236	#define SCIF_BASE_PORT PORT_SCIFA
237	#else
238	#define SCIF_BASE_PORT PORT_SCIF
239	#endif
240
241	static struct uart_port sh_sci = {
242	.membase = (unsigned char *)SCIF_BASE,
243	.mapbase = SCIF_BASE,
244	.type = SCIF_BASE_PORT,
245	#ifdef CONFIG_SCIF_USE_EXT_CLK
246	.clk_mode = EXT_CLK,
247	#endif
248	};
249
250	static void sh_serial_setbrg(void)
251	{
252	DECLARE_GLOBAL_DATA_PTR;
253	struct uart_port *port = &sh_sci;
254
255	sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
256	}
257
258	static int sh_serial_init(void)
259	{
260	struct uart_port *port = &sh_sci;
261
262	sh_serial_init_generic(port);
263	serial_setbrg();
264
265	return 0;
266	}
267
268	static void sh_serial_putc(const char c)
269	{
270	struct uart_port *port = &sh_sci;
271
272	if (c == '\n') {
273	while (1) {
274	if (serial_raw_putc(port, '\r') != -EAGAIN)
275	break;
276	}
277	}
278	while (1) {
279	if (serial_raw_putc(port, c) != -EAGAIN)
280	break;
281	}
282	}
283
284	static int sh_serial_tstc(void)
285	{
286	struct uart_port *port = &sh_sci;
287
288	return sh_serial_tstc_generic(port);
289	}
290
291	static int sh_serial_getc(void)
292	{
293	struct uart_port *port = &sh_sci;
294	int ch;
295
296	while (1) {
297	ch = sh_serial_getc_generic(port);
298	if (ch != -EAGAIN)
299	break;
300	}
0b135cfc	301
08c5fabe	302	return ch;
0b135cfc	303	}
8bdd7efa	304
8bdd7efa MV	305	static struct serial_device sh_serial_drv = {
	306	.name = "sh_serial",
	307	.start = sh_serial_init,
	308	.stop = NULL,
	309	.setbrg = sh_serial_setbrg,
	310	.putc = sh_serial_putc,
ec3fd689	311	.puts = default_serial_puts,
8bdd7efa MV	312	.getc = sh_serial_getc,
	313	.tstc = sh_serial_tstc,
	314	};
	315
	316	void sh_serial_initialize(void)
	317	{
	318	serial_register(&sh_serial_drv);
	319	}
	320
	321	__weak struct serial_device *default_serial_console(void)
	322	{
	323	return &sh_serial_drv;
	324	}
59088e4a	325	#endif /* CONFIG_DM_SERIAL */