projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3f6c8e36 NI |
1 | /* |
| 2 | * Copy and modify from linux/drivers/serial/sh-sci.h | |
| 3 | */ | |
| 4 | ||
| 59088e4a NI |
5 | #include <dm/platform_data/serial_sh.h> |
| 6 | ||
| 3f6c8e36 NI |
7 | struct uart_port { |
| 8 | unsigned long iobase; /* in/out[bwl] */ | |
| 9 | unsigned char *membase; /* read/write[bwl] */ | |
| 10 | unsigned long mapbase; /* for ioremap */ | |
| 59088e4a NI |
11 | enum sh_serial_type type; /* port type */ |
| 12 | enum sh_clk_mode clk_mode; /* clock mode */ | |
| 3f6c8e36 NI |
13 | }; |
| 14 | ||
| 3f6c8e36 NI |
15 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 16 | #include <asm/regs306x.h> | |
| 17 | #endif | |
| 18 | #if defined(CONFIG_H8S2678) | |
| 19 | #include <asm/regs267x.h> | |
| 20 | #endif | |
| 21 | ||
| 22 | #if defined(CONFIG_CPU_SH7706) || \ | |
| 23 | defined(CONFIG_CPU_SH7707) || \ | |
| 24 | defined(CONFIG_CPU_SH7708) || \ | |
| 25 | defined(CONFIG_CPU_SH7709) | |
| 26 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ | |
| 27 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
| 28 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 29 | #elif defined(CONFIG_CPU_SH7705) | |
| 30 | # define SCIF0 0xA4400000 | |
| 31 | # define SCIF2 0xA4410000 | |
| 32 | # define SCSMR_Ir 0xA44A0000 | |
| 33 | # define IRDA_SCIF SCIF0 | |
| 34 | # define SCPCR 0xA4000116 | |
| 35 | # define SCPDR 0xA4000136 | |
| 36 | ||
| 37 | /* Set the clock source, | |
| 38 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
| 39 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
| 40 | */ | |
| 41 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
| 42 | #elif defined(CONFIG_CPU_SH7720) || \ | |
| 43 | defined(CONFIG_CPU_SH7721) || \ | |
| 44 | defined(CONFIG_ARCH_SH7367) || \ | |
| 45 | defined(CONFIG_ARCH_SH7377) || \ | |
| c3d6a357 | 46 | defined(CONFIG_ARCH_SH7372) || \ |
| d61678e0 HS |
47 | defined(CONFIG_SH73A0) || \ |
| 48 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
49 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 50 | # define PORT_PTCR 0xA405011EUL | |
| 51 | # define PORT_PVCR 0xA4050122UL | |
| 52 | # define SCIF_ORER 0x0200 /* overrun error bit */ | |
| 53 | #elif defined(CONFIG_SH_RTS7751R2D) | |
| 54 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ | |
| 55 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 56 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 57 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 58 | #elif defined(CONFIG_CPU_SH7750) || \ | |
| 59 | defined(CONFIG_CPU_SH7750R) || \ | |
| 60 | defined(CONFIG_CPU_SH7750S) || \ | |
| 61 | defined(CONFIG_CPU_SH7091) || \ | |
| 62 | defined(CONFIG_CPU_SH7751) || \ | |
| 63 | defined(CONFIG_CPU_SH7751R) | |
| 64 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ | |
| 65 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 66 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 67 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
| 68 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
| 69 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) | |
| 70 | #elif defined(CONFIG_CPU_SH7760) | |
| 71 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ | |
| 72 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
| 73 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
| 74 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 75 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 76 | #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) | |
| 77 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | |
| 78 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 79 | # define PACR 0xa4050100 | |
| 80 | # define PBCR 0xa4050102 | |
| 81 | # define SCSCR_INIT(port) 0x3B | |
| 82 | #elif defined(CONFIG_CPU_SH7343) | |
| 83 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
| 84 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
| 85 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
| 86 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
| 87 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
| 88 | #elif defined(CONFIG_CPU_SH7722) | |
| 89 | # define PADR 0xA4050120 | |
| 99057064 | 90 | # undef PSDR |
| 3f6c8e36 NI |
91 | # define PSDR 0xA405013e |
| 92 | # define PWDR 0xA4050166 | |
| 93 | # define PSCR 0xA405011E | |
| 94 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 95 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 96 | #elif defined(CONFIG_CPU_SH7366) | |
| 97 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 98 | # define SCSPTR0 SCPDR0 | |
| 99 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 100 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 101 | #elif defined(CONFIG_CPU_SH7723) | |
| 102 | # define SCSPTR0 0xa4050160 | |
| 103 | # define SCSPTR1 0xa405013e | |
| 104 | # define SCSPTR2 0xa4050160 | |
| 105 | # define SCSPTR3 0xa405013e | |
| 106 | # define SCSPTR4 0xa4050128 | |
| 107 | # define SCSPTR5 0xa4050128 | |
| 108 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 109 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 110 | #elif defined(CONFIG_CPU_SH7724) | |
| 111 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 112 | # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ | |
| 113 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
| 114 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) | |
| 2a57e7ec NI |
115 | #elif defined(CONFIG_CPU_SH7734) |
| 116 | # define SCSPTR0 0xFFE40020 | |
| 117 | # define SCSPTR1 0xFFE41020 | |
| 118 | # define SCSPTR2 0xFFE42020 | |
| 119 | # define SCSPTR3 0xFFE43020 | |
| 120 | # define SCSPTR4 0xFFE44020 | |
| 121 | # define SCSPTR5 0xFFE45020 | |
| 122 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 123 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 3f6c8e36 NI |
124 | #elif defined(CONFIG_CPU_SH4_202) |
| 125 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | |
| 126 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 127 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 128 | #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) | |
| 129 | # define SCIF_BASE_ADDR 0x01030000 | |
| 130 | # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) | |
| 131 | # define SCIF_PTR2_OFFS 0x0000020 | |
| 132 | # define SCIF_LSR2_OFFS 0x0000024 | |
| 133 | # define SCSPTR\ | |
| 134 | ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | |
| 135 | # define SCLSR2\ | |
| 136 | ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
| 137 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ | |
| 138 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 139 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 140 | # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) | |
| 141 | #elif defined(CONFIG_H8S2678) | |
| 142 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 143 | # define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port)) | |
| f3bf212a YS |
144 | #elif defined(CONFIG_CPU_SH7757) || \ |
| 145 | defined(CONFIG_CPU_SH7752) || \ | |
| 146 | defined(CONFIG_CPU_SH7753) | |
| 3f6c8e36 NI |
147 | # define SCSPTR0 0xfe4b0020 |
| 148 | # define SCSPTR1 0xfe4b0020 | |
| 149 | # define SCSPTR2 0xfe4b0020 | |
| 150 | # define SCIF_ORER 0x0001 | |
| 151 | # define SCSCR_INIT(port) 0x38 | |
| 152 | # define SCIF_ONLY | |
| 153 | #elif defined(CONFIG_CPU_SH7763) | |
| 154 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 155 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
| 156 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ | |
| 157 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 158 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 159 | #elif defined(CONFIG_CPU_SH7770) | |
| 160 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
| 161 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
| 162 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
| 163 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 164 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
| 165 | #elif defined(CONFIG_CPU_SH7780) | |
| 166 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 167 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
| 168 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 169 | ||
| 170 | #if defined(CONFIG_SH_SH2007) | |
| 171 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ | |
| 172 | # define SCSCR_INIT(port) 0x38 | |
| 173 | #else | |
| 174 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ | |
| 175 | # define SCSCR_INIT(port) 0x3a | |
| 176 | #endif | |
| 177 | ||
| 178 | #elif defined(CONFIG_CPU_SH7785) || \ | |
| 179 | defined(CONFIG_CPU_SH7786) | |
| 180 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | |
| 181 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
| 182 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
| 183 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
| 184 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
| 185 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
| 186 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 187 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 188 | #elif defined(CONFIG_CPU_SH7201) || \ | |
| 189 | defined(CONFIG_CPU_SH7203) || \ | |
| 190 | defined(CONFIG_CPU_SH7206) || \ | |
| 7fbeb642 PE |
191 | defined(CONFIG_CPU_SH7263) || \ |
| 192 | defined(CONFIG_CPU_SH7264) | |
| 3f6c8e36 NI |
193 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
| 194 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
| 195 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
| 196 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
| 197 | # if defined(CONFIG_CPU_SH7201) | |
| 198 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ | |
| 199 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ | |
| 200 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | |
| 201 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | |
| 202 | # endif | |
| 203 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 99744b7e PE |
204 | #elif defined(CONFIG_CPU_SH7269) |
| 205 | # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ | |
| 206 | # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ | |
| 207 | # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ | |
| 208 | # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ | |
| 209 | # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ | |
| 210 | # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ | |
| 211 | # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ | |
| 212 | # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ | |
| 213 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 3f6c8e36 NI |
214 | #elif defined(CONFIG_CPU_SH7619) |
| 215 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
| 216 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
| 217 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
| 218 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 219 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 220 | #elif defined(CONFIG_CPU_SHX3) | |
| 221 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
| 222 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
| 223 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
| 224 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
| 225 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 226 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 2f972a3c | 227 | #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ |
| 6f107e4c | 228 | defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \ |
| 167ee838 | 229 | defined(CONFIG_R8A7794) || defined(CONFIG_RCAR_GEN3) |
| 53be7bf2 VB |
230 | # if defined(CONFIG_SCIF_A) |
| 231 | # define SCIF_ORER 0x0200 | |
| 232 | # else | |
| 233 | # define SCIF_ORER 0x0001 | |
| 234 | # endif | |
| 2cbb17c0 VB |
235 | # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) |
| 236 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ | |
| 3f6c8e36 NI |
237 | #else |
| 238 | # error CPU subtype not defined | |
| 239 | #endif | |
| 240 | ||
| 241 | /* SCSCR */ | |
| 242 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
| 243 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
| 244 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
| 245 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
| 246 | #if defined(CONFIG_CPU_SH7750) || \ | |
| 247 | defined(CONFIG_CPU_SH7091) || \ | |
| 248 | defined(CONFIG_CPU_SH7750R) || \ | |
| 249 | defined(CONFIG_CPU_SH7722) || \ | |
| 2a57e7ec | 250 | defined(CONFIG_CPU_SH7734) || \ |
| 3f6c8e36 NI |
251 | defined(CONFIG_CPU_SH7750S) || \ |
| 252 | defined(CONFIG_CPU_SH7751) || \ | |
| 253 | defined(CONFIG_CPU_SH7751R) || \ | |
| 254 | defined(CONFIG_CPU_SH7763) || \ | |
| 255 | defined(CONFIG_CPU_SH7780) || \ | |
| 256 | defined(CONFIG_CPU_SH7785) || \ | |
| 257 | defined(CONFIG_CPU_SH7786) || \ | |
| 258 | defined(CONFIG_CPU_SHX3) | |
| 259 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ | |
| 260 | #elif defined(CONFIG_CPU_SH7724) | |
| 261 | #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) | |
| 262 | #else | |
| 263 | #define SCI_CTRL_FLAGS_REIE 0 | |
| 264 | #endif | |
| 265 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 266 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 267 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
| 268 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
| 269 | ||
| 270 | /* SCxSR SCI */ | |
| 271 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 272 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 273 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 274 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 275 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 276 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 277 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 278 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 279 | ||
| 280 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
| 281 | ||
| 282 | /* SCxSR SCIF */ | |
| 283 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 284 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 285 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 286 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 287 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 288 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 289 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 290 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 291 | ||
| 292 | #if defined(CONFIG_CPU_SH7705) || \ | |
| 293 | defined(CONFIG_CPU_SH7720) || \ | |
| 294 | defined(CONFIG_CPU_SH7721) || \ | |
| 295 | defined(CONFIG_ARCH_SH7367) || \ | |
| 296 | defined(CONFIG_ARCH_SH7377) || \ | |
| c3d6a357 | 297 | defined(CONFIG_ARCH_SH7372) || \ |
| d61678e0 HS |
298 | defined(CONFIG_SH73A0) || \ |
| 299 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
300 | # define SCIF_ORER 0x0200 |
| 301 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
| 302 | # define SCIF_RFDC_MASK 0x007f | |
| 303 | # define SCIF_TXROOM_MAX 64 | |
| 304 | #elif defined(CONFIG_CPU_SH7763) | |
| 305 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
| 306 | # define SCIF_RFDC_MASK 0x007f | |
| 307 | # define SCIF_TXROOM_MAX 64 | |
| 308 | /* SH7763 SCIF2 support */ | |
| 309 | # define SCIF2_RFDC_MASK 0x001f | |
| 310 | # define SCIF2_TXROOM_MAX 16 | |
| 6f107e4c | 311 | #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ |
| a3cc41b4 | 312 | defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) |
| 48ca882c | 313 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| 53be7bf2 VB |
314 | # if defined(CONFIG_SCIF_A) |
| 315 | # define SCIF_RFDC_MASK 0x007f | |
| 316 | # else | |
| 317 | # define SCIF_RFDC_MASK 0x001f | |
| 318 | # endif | |
| 3f6c8e36 NI |
319 | #else |
| 320 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
| 321 | # define SCIF_RFDC_MASK 0x001f | |
| 322 | # define SCIF_TXROOM_MAX 16 | |
| 323 | #endif | |
| 324 | ||
| 325 | #ifndef SCIF_ORER | |
| 326 | #define SCIF_ORER 0x0000 | |
| 327 | #endif | |
| 328 | ||
| 329 | #define SCxSR_TEND(port)\ | |
| 330 | (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | |
| 331 | #define SCxSR_ERRORS(port)\ | |
| 332 | (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
| 333 | #define SCxSR_RDxF(port)\ | |
| 334 | (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
| 335 | #define SCxSR_TDxE(port)\ | |
| 336 | (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 337 | #define SCxSR_FER(port)\ | |
| 338 | (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 339 | #define SCxSR_PER(port)\ | |
| 340 | (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 341 | #define SCxSR_BRK(port)\ | |
| 342 | ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| 343 | #define SCxSR_ORER(port)\ | |
| 344 | (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) | |
| 345 | ||
| 346 | #if defined(CONFIG_CPU_SH7705) || \ | |
| 347 | defined(CONFIG_CPU_SH7720) || \ | |
| 348 | defined(CONFIG_CPU_SH7721) || \ | |
| 349 | defined(CONFIG_ARCH_SH7367) || \ | |
| 350 | defined(CONFIG_ARCH_SH7377) || \ | |
| c3d6a357 | 351 | defined(CONFIG_ARCH_SH7372) || \ |
| d61678e0 HS |
352 | defined(CONFIG_SH73A0) || \ |
| 353 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
354 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
| 355 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | |
| 356 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | |
| 357 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | |
| 358 | #else | |
| 359 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | |
| 360 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 361 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 362 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 363 | #endif | |
| 364 | ||
| 365 | /* SCFCR */ | |
| 366 | #define SCFCR_RFRST 0x0002 | |
| 367 | #define SCFCR_TFRST 0x0004 | |
| 368 | #define SCFCR_TCRST 0x4000 | |
| 369 | #define SCFCR_MCE 0x0008 | |
| 370 | ||
| 371 | #define SCI_MAJOR 204 | |
| 372 | #define SCI_MINOR_START 8 | |
| 373 | ||
| 374 | /* Generic serial flags */ | |
| 375 | #define SCI_RX_THROTTLE 0x0000001 | |
| 376 | ||
| 377 | #define SCI_MAGIC 0xbabeface | |
| 378 | ||
| 379 | /* | |
| 380 | * Events are used to schedule things to happen at timer-interrupt | |
| 381 | * time, instead of at rs interrupt time. | |
| 382 | */ | |
| 383 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
| 384 | ||
| 385 | #define SCI_IN(size, offset)\ | |
| 386 | if ((size) == 8) {\ | |
| 387 | return readb(port->membase + (offset));\ | |
| 388 | } else {\ | |
| 389 | return readw(port->membase + (offset));\ | |
| 390 | } | |
| 391 | #define SCI_OUT(size, offset, value)\ | |
| 392 | if ((size) == 8) {\ | |
| 393 | writeb(value, port->membase + (offset));\ | |
| 394 | } else if ((size) == 16) {\ | |
| 395 | writew(value, port->membase + (offset));\ | |
| 396 | } | |
| 397 | ||
| 398 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
| 399 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ | |
| 400 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ | |
| 401 | SCI_IN(scif_size, scif_offset)\ | |
| 402 | } else { /* PORT_SCI or PORT_SCIFA */\ | |
| 403 | SCI_IN(sci_size, sci_offset);\ | |
| 404 | }\ | |
| 405 | }\ | |
| 406 | static inline void sci_##name##_out(struct uart_port *port,\ | |
| 407 | unsigned int value) {\ | |
| 408 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ | |
| 409 | SCI_OUT(scif_size, scif_offset, value)\ | |
| 410 | } else { /* PORT_SCI or PORT_SCIFA */\ | |
| 411 | SCI_OUT(sci_size, sci_offset, value);\ | |
| 412 | }\ | |
| 413 | } | |
| 414 | ||
| 415 | #ifdef CONFIG_H8300 | |
| 416 | /* h8300 don't have SCIF */ | |
| 417 | #define CPU_SCIF_FNS(name) \ | |
| 418 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ | |
| 419 | return 0;\ | |
| 420 | }\ | |
| 421 | static inline void sci_##name##_out(struct uart_port *port,\ | |
| 422 | unsigned int value) {\ | |
| 423 | } | |
| 424 | #else | |
| 425 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
| 426 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ | |
| 427 | SCI_IN(scif_size, scif_offset);\ | |
| 428 | }\ | |
| 429 | static inline void sci_##name##_out(struct uart_port *port,\ | |
| 430 | unsigned int value) {\ | |
| 431 | SCI_OUT(scif_size, scif_offset, value);\ | |
| 432 | } | |
| 433 | #endif | |
| 434 | ||
| 435 | #define CPU_SCI_FNS(name, sci_offset, sci_size)\ | |
| 436 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ | |
| 437 | SCI_IN(sci_size, sci_offset);\ | |
| 438 | }\ | |
| 439 | static inline void sci_##name##_out(struct uart_port *port,\ | |
| 440 | unsigned int value) {\ | |
| 441 | SCI_OUT(sci_size, sci_offset, value);\ | |
| 442 | } | |
| 443 | ||
| 7d236662 | 444 | #if defined(CONFIG_CPU_SH3) || \ |
| 3f6c8e36 NI |
445 | defined(CONFIG_ARCH_SH7367) || \ |
| 446 | defined(CONFIG_ARCH_SH7377) || \ | |
| c3d6a357 | 447 | defined(CONFIG_ARCH_SH7372) || \ |
| d61678e0 HS |
448 | defined(CONFIG_SH73A0) || \ |
| 449 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
450 | #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) |
| 451 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ | |
| 452 | sh4_sci_offset, sh4_sci_size, \ | |
| 453 | sh3_scif_offset, sh3_scif_size, \ | |
| 454 | sh4_scif_offset, sh4_scif_size, \ | |
| 455 | h8_sci_offset, h8_sci_size) \ | |
| 456 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ | |
| 457 | sh4_scif_offset, sh4_scif_size) | |
| 458 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ | |
| 459 | sh4_scif_offset, sh4_scif_size) \ | |
| 460 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 461 | #elif defined(CONFIG_CPU_SH7705) || \ | |
| 462 | defined(CONFIG_CPU_SH7720) || \ | |
| 463 | defined(CONFIG_CPU_SH7721) || \ | |
| 464 | defined(CONFIG_ARCH_SH7367) || \ | |
| c3d6a357 NI |
465 | defined(CONFIG_ARCH_SH7377) || \ |
| 466 | defined(CONFIG_SH73A0) | |
| 3f6c8e36 NI |
467 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| 468 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| d61678e0 HS |
469 | #elif defined(CONFIG_ARCH_SH7372) || \ |
| 470 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
471 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ |
| 472 | sh4_scifb_offset, sh4_scifb_size) \ | |
| 473 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
| 474 | sh4_scifb_offset, sh4_scifb_size) | |
| 475 | #define SCIF_FNS(name, scif_offset, scif_size) \ | |
| 476 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| 477 | #else | |
| 478 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ | |
| 479 | sh4_sci_offset, sh4_sci_size, \ | |
| 480 | sh3_scif_offset, sh3_scif_size,\ | |
| 481 | sh4_scif_offset, sh4_scif_size, \ | |
| 482 | h8_sci_offset, h8_sci_size) \ | |
| 483 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ | |
| 484 | sh3_scif_offset, sh3_scif_size) | |
| 485 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ | |
| 486 | sh4_scif_offset, sh4_scif_size) \ | |
| 487 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
| 488 | #endif | |
| 489 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 490 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ | |
| 491 | sh4_sci_offset, sh4_sci_size, \ | |
| 492 | sh3_scif_offset, sh3_scif_size,\ | |
| 493 | sh4_scif_offset, sh4_scif_size, \ | |
| 494 | h8_sci_offset, h8_sci_size) \ | |
| 495 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
| 496 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ | |
| 497 | sh4_scif_offset, sh4_scif_size) \ | |
| 498 | CPU_SCIF_FNS(name) | |
| 499 | #elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724) | |
| 500 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
| 501 | sh4_scif_offset, sh4_scif_size) \ | |
| 502 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ | |
| 503 | sh4_scif_offset, sh4_scif_size) | |
| 504 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
| 505 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 506 | #else | |
| 507 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ | |
| 508 | sh4_sci_offset, sh4_sci_size, \ | |
| 509 | sh3_scif_offset, sh3_scif_size,\ | |
| 510 | sh4_scif_offset, sh4_scif_size, \ | |
| 511 | h8_sci_offset, h8_sci_size) \ | |
| 512 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ | |
| 513 | sh4_scif_offset, sh4_scif_size) | |
| 514 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ | |
| 515 | sh4_scif_offset, sh4_scif_size) \ | |
| 516 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 517 | #endif | |
| 518 | ||
| 519 | #if defined(CONFIG_CPU_SH7705) || \ | |
| 520 | defined(CONFIG_CPU_SH7720) || \ | |
| 521 | defined(CONFIG_CPU_SH7721) || \ | |
| 522 | defined(CONFIG_ARCH_SH7367) || \ | |
| c3d6a357 NI |
523 | defined(CONFIG_ARCH_SH7377) || \ |
| 524 | defined(CONFIG_SH73A0) | |
| 3f6c8e36 NI |
525 | |
| 526 | SCIF_FNS(SCSMR, 0x00, 16) | |
| 527 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 528 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 529 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 530 | SCIF_FNS(SCFER, 0x10, 16) | |
| 531 | SCIF_FNS(SCxSR, 0x14, 16) | |
| 532 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 533 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 534 | SCIF_FNS(SCxTDR, 0x20, 8) | |
| 535 | SCIF_FNS(SCxRDR, 0x24, 8) | |
| 536 | SCIF_FNS(SCLSR, 0x00, 0) | |
| 59088e4a | 537 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| d61678e0 HS |
538 | #elif defined(CONFIG_ARCH_SH7372) || \ |
| 539 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
540 | SCIF_FNS(SCSMR, 0x00, 16) |
| 541 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 542 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 543 | SCIF_FNS(SCTDSR, 0x0c, 16) | |
| 544 | SCIF_FNS(SCFER, 0x10, 16) | |
| 545 | SCIF_FNS(SCxSR, 0x14, 16) | |
| 546 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 547 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 548 | SCIF_FNS(SCTFDR, 0x38, 16) | |
| 549 | SCIF_FNS(SCRFDR, 0x3c, 16) | |
| 550 | SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) | |
| 551 | SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) | |
| 552 | SCIF_FNS(SCLSR, 0x00, 0) | |
| 59088e4a | 553 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| 3f6c8e36 NI |
554 | #elif defined(CONFIG_CPU_SH7723) ||\ |
| 555 | defined(CONFIG_CPU_SH7724) | |
| 556 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | |
| 557 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | |
| 558 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | |
| 559 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | |
| 560 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | |
| 561 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | |
| 562 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) | |
| 563 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 564 | SCIF_FNS(SCFER, 0x10, 16) | |
| 565 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 566 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 567 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 59088e4a | 568 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| 6f107e4c | 569 | #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ |
| 53be7bf2 VB |
570 | defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) |
| 571 | /* SCIFA and SCIF register offsets and size */ | |
| 572 | SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) | |
| 573 | SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) | |
| 574 | SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0) | |
| 575 | SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0) | |
| 576 | SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0) | |
| 577 | SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0) | |
| 578 | SCIF_FNS(SCFCR, 0, 0, 0x18, 16) | |
| 579 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) | |
| 580 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | |
| 581 | SCIF_FNS(DL, 0, 0, 0x30, 16) | |
| 582 | SCIF_FNS(CKS, 0, 0, 0x34, 16) | |
| 583 | #if defined(CONFIG_SCIF_A) | |
| 584 | SCIF_FNS(SCLSR, 0, 0, 0x14, 16) | |
| 585 | #else | |
| 586 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) | |
| 587 | #endif | |
| 3f6c8e36 NI |
588 | #else |
| 589 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
| 590 | /* name off sz off sz off sz off sz off sz*/ | |
| 591 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
| 592 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
| 593 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
| 594 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
| 595 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
| 596 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
| 597 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
| 598 | #if defined(CONFIG_CPU_SH7760) || \ | |
| 599 | defined(CONFIG_CPU_SH7780) || \ | |
| 600 | defined(CONFIG_CPU_SH7785) || \ | |
| 601 | defined(CONFIG_CPU_SH7786) | |
| 602 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) | |
| 603 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | |
| 604 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 605 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 606 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| 607 | #elif defined(CONFIG_CPU_SH7763) | |
| 608 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) | |
| 609 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | |
| 610 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) | |
| 611 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | |
| 612 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 613 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 614 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| 615 | #else | |
| 59088e4a | 616 | |
| 3f6c8e36 NI |
617 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| 618 | #if defined(CONFIG_CPU_SH7722) | |
| 619 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | |
| 620 | #else | |
| 621 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | |
| 622 | #endif | |
| 59088e4a NI |
623 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
| 624 | #endif | |
| 59088e4a | 625 | SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ |
| 3f6c8e36 | 626 | #endif |
| 3f6c8e36 NI |
627 | #define sci_in(port, reg) sci_##reg##_in(port) |
| 628 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
| 629 | ||
| 630 | /* H8/300 series SCI pins assignment */ | |
| 631 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 632 | static const struct __attribute__((packed)) { | |
| 633 | int port; /* GPIO port no */ | |
| 634 | unsigned short rx, tx; /* GPIO bit no */ | |
| 635 | } h8300_sci_pins[] = { | |
| 636 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 637 | { /* SCI0 */ | |
| 638 | .port = H8300_GPIO_P9, | |
| 639 | .rx = H8300_GPIO_B2, | |
| 640 | .tx = H8300_GPIO_B0, | |
| 641 | }, | |
| 642 | { /* SCI1 */ | |
| 643 | .port = H8300_GPIO_P9, | |
| 644 | .rx = H8300_GPIO_B3, | |
| 645 | .tx = H8300_GPIO_B1, | |
| 646 | }, | |
| 647 | { /* SCI2 */ | |
| 648 | .port = H8300_GPIO_PB, | |
| 649 | .rx = H8300_GPIO_B7, | |
| 650 | .tx = H8300_GPIO_B6, | |
| 651 | } | |
| 652 | #elif defined(CONFIG_H8S2678) | |
| 653 | { /* SCI0 */ | |
| 654 | .port = H8300_GPIO_P3, | |
| 655 | .rx = H8300_GPIO_B2, | |
| 656 | .tx = H8300_GPIO_B0, | |
| 657 | }, | |
| 658 | { /* SCI1 */ | |
| 659 | .port = H8300_GPIO_P3, | |
| 660 | .rx = H8300_GPIO_B3, | |
| 661 | .tx = H8300_GPIO_B1, | |
| 662 | }, | |
| 663 | { /* SCI2 */ | |
| 664 | .port = H8300_GPIO_P5, | |
| 665 | .rx = H8300_GPIO_B1, | |
| 666 | .tx = H8300_GPIO_B0, | |
| 667 | } | |
| 668 | #endif | |
| 669 | }; | |
| 670 | #endif | |
| 671 | ||
| 672 | #if defined(CONFIG_CPU_SH7706) || \ | |
| 673 | defined(CONFIG_CPU_SH7707) || \ | |
| 674 | defined(CONFIG_CPU_SH7708) || \ | |
| 675 | defined(CONFIG_CPU_SH7709) | |
| 676 | static inline int sci_rxd_in(struct uart_port *port) | |
| 677 | { | |
| 678 | if (port->mapbase == 0xfffffe80) | |
| 679 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
| 680 | return 1; | |
| 681 | } | |
| 682 | #elif defined(CONFIG_CPU_SH7750) || \ | |
| 683 | defined(CONFIG_CPU_SH7751) || \ | |
| 684 | defined(CONFIG_CPU_SH7751R) || \ | |
| 685 | defined(CONFIG_CPU_SH7750R) || \ | |
| 686 | defined(CONFIG_CPU_SH7750S) || \ | |
| 687 | defined(CONFIG_CPU_SH7091) | |
| 688 | static inline int sci_rxd_in(struct uart_port *port) | |
| 689 | { | |
| 690 | if (port->mapbase == 0xffe00000) | |
| 691 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
| 692 | return 1; | |
| 693 | } | |
| 694 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 695 | static inline int sci_rxd_in(struct uart_port *port) | |
| 696 | { | |
| 697 | int ch = (port->mapbase - SMR0) >> 3; | |
| 698 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
| 699 | } | |
| 700 | #else /* default case for non-SCI processors */ | |
| 701 | static inline int sci_rxd_in(struct uart_port *port) | |
| 702 | { | |
| 703 | return 1; | |
| 704 | } | |
| 705 | #endif | |
| 706 | ||
| 707 | /* | |
| 708 | * Values for the BitRate Register (SCBRR) | |
| 709 | * | |
| 710 | * The values are actually divisors for a frequency which can | |
| 711 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
| 712 | * clock source. This driver assumes the internal clock is used; | |
| 713 | * to support using an external clock source, config options or | |
| 714 | * possibly command-line options would need to be added. | |
| 715 | * | |
| 716 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
| 717 | * the SCSMR register would also need to be set to non-zero values. | |
| 718 | * | |
| 719 | * -- Greg Banks 27Feb2000 | |
| 720 | * | |
| 721 | * Answer: The SCBRR register is only eight bits, and the value in | |
| 722 | * it gets larger with lower baud rates. At around 2400 (depending on | |
| 723 | * the peripherial module clock) you run out of bits. However the | |
| 724 | * lower two bits of SCSMR allow the module clock to be divided down, | |
| 725 | * scaling the value which is needed in SCBRR. | |
| 726 | * | |
| 727 | * -- Stuart Menefy - 23 May 2000 | |
| 728 | * | |
| 729 | * I meant, why would anyone bother with bitrates below 2400. | |
| 730 | * | |
| 731 | * -- Greg Banks - 7Jul2000 | |
| 732 | * | |
| 733 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
| 734 | * tape reader as a console! | |
| 735 | * | |
| 736 | * -- Mitch Davis - 15 Jul 2000 | |
| 737 | */ | |
| 738 | ||
| 739 | #if (defined(CONFIG_CPU_SH7780) || \ | |
| 740 | defined(CONFIG_CPU_SH7785) || \ | |
| 741 | defined(CONFIG_CPU_SH7786)) && \ | |
| 742 | !defined(CONFIG_SH_SH2007) | |
| 743 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | |
| 744 | #elif defined(CONFIG_CPU_SH7705) || \ | |
| 745 | defined(CONFIG_CPU_SH7720) || \ | |
| 746 | defined(CONFIG_CPU_SH7721) || \ | |
| 747 | defined(CONFIG_ARCH_SH7367) || \ | |
| 748 | defined(CONFIG_ARCH_SH7377) || \ | |
| c3d6a357 | 749 | defined(CONFIG_ARCH_SH7372) || \ |
| d61678e0 HS |
750 | defined(CONFIG_SH73A0) || \ |
| 751 | defined(CONFIG_R8A7740) | |
| 3f6c8e36 NI |
752 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
| 753 | #elif defined(CONFIG_CPU_SH7723) ||\ | |
| 754 | defined(CONFIG_CPU_SH7724) | |
| 59088e4a | 755 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
| 3f6c8e36 | 756 | { |
| 59088e4a | 757 | if (port->type == PORT_SCIF) |
| 3f6c8e36 NI |
758 | return (clk+16*bps)/(32*bps)-1; |
| 759 | else | |
| 760 | return ((clk*2)+16*bps)/(16*bps)-1; | |
| 761 | } | |
| 59088e4a | 762 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) |
| 3f6c8e36 NI |
763 | #elif defined(__H8300H__) || defined(__H8300S__) |
| 764 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) | |
| 6f107e4c | 765 | #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \ |
| a3cc41b4 | 766 | defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) |
| 53022c31 | 767 | #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ |
| 53be7bf2 VB |
768 | #if defined(CONFIG_SCIF_A) |
| 769 | #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ | |
| 770 | #else | |
| 771 | #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ | |
| 772 | #endif | |
| 3f6c8e36 NI |
773 | #else /* Generic SH */ |
| 774 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
| 775 | #endif | |
| 59088e4a NI |
776 | |
| 777 | #ifndef DL_VALUE | |
| 778 | #define DL_VALUE(bps, clk) 0 | |
| 779 | #endif |