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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
6a12cebd | 2 | /* |
3bc599c9 PC |
3 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. | |
6a12cebd VM |
5 | */ |
6 | ||
ae74de0d PC |
7 | #ifndef _SERIAL_STM32_ |
8 | #define _SERIAL_STM32_ | |
6a12cebd | 9 | |
60a996ba PC |
10 | #define CR1_OFFSET(x) (x ? 0x0c : 0x00) |
11 | #define CR3_OFFSET(x) (x ? 0x14 : 0x08) | |
12 | #define BRR_OFFSET(x) (x ? 0x08 : 0x0c) | |
13 | #define ISR_OFFSET(x) (x ? 0x00 : 0x1c) | |
7b3b74d3 PC |
14 | |
15 | #define ICR_OFFSET 0x20 | |
bc709a41 | 16 | |
60a996ba PC |
17 | /* |
18 | * STM32F4 has one Data Register (DR) for received or transmitted | |
19 | * data, so map Receive Data Register (RDR) and Transmit Data | |
20 | * Register (TDR) at the same offset | |
21 | */ | |
22 | #define RDR_OFFSET(x) (x ? 0x04 : 0x24) | |
23 | #define TDR_OFFSET(x) (x ? 0x04 : 0x28) | |
24 | ||
25 | struct stm32_uart_info { | |
26 | u8 uart_enable_bit; /* UART_CR1_UE */ | |
27 | bool stm32f4; /* true for STM32F4, false otherwise */ | |
2a7ecc53 | 28 | bool has_fifo; |
60a996ba PC |
29 | }; |
30 | ||
6c30f15b PC |
31 | struct stm32_uart_info stm32f4_info = { |
32 | .stm32f4 = true, | |
33 | .uart_enable_bit = 13, | |
6c30f15b PC |
34 | .has_fifo = false, |
35 | }; | |
36 | ||
2a7ecc53 | 37 | struct stm32_uart_info stm32f7_info = { |
60a996ba PC |
38 | .uart_enable_bit = 0, |
39 | .stm32f4 = false, | |
95a07721 | 40 | .has_fifo = true, |
2a7ecc53 PC |
41 | }; |
42 | ||
43 | struct stm32_uart_info stm32h7_info = { | |
44 | .uart_enable_bit = 0, | |
45 | .stm32f4 = false, | |
2a7ecc53 | 46 | .has_fifo = true, |
6a12cebd VM |
47 | }; |
48 | ||
122b2d47 PC |
49 | /* Information about a serial port */ |
50 | struct stm32x7_serial_platdata { | |
60a996ba PC |
51 | fdt_addr_t base; /* address of registers in physical memory */ |
52 | struct stm32_uart_info *uart_info; | |
27265cee | 53 | unsigned long int clock_rate; |
122b2d47 | 54 | }; |
6a12cebd | 55 | |
2a7ecc53 | 56 | #define USART_CR1_FIFOEN BIT(29) |
bc709a41 | 57 | #define USART_CR1_M1 BIT(28) |
2a52a952 | 58 | #define USART_CR1_OVER8 BIT(15) |
bc709a41 PD |
59 | #define USART_CR1_M0 BIT(12) |
60 | #define USART_CR1_PCE BIT(10) | |
61 | #define USART_CR1_PS BIT(9) | |
2a52a952 PC |
62 | #define USART_CR1_TE BIT(3) |
63 | #define USART_CR1_RE BIT(2) | |
6a12cebd | 64 | |
2a52a952 | 65 | #define USART_CR3_OVRDIS BIT(12) |
6c0c3ce8 | 66 | |
be1a6f77 PC |
67 | #define USART_ISR_TXE BIT(7) |
68 | #define USART_ISR_RXNE BIT(5) | |
69 | #define USART_ISR_ORE BIT(3) | |
bc709a41 | 70 | #define USART_ISR_PE BIT(0) |
6a12cebd | 71 | |
2a52a952 | 72 | #define USART_BRR_F_MASK GENMASK(7, 0) |
6a12cebd | 73 | #define USART_BRR_M_SHIFT 4 |
2a52a952 | 74 | #define USART_BRR_M_MASK GENMASK(15, 4) |
6a12cebd | 75 | |
be1a6f77 | 76 | #define USART_ICR_ORECF BIT(3) |
bc709a41 PD |
77 | #define USART_ICR_PCECF BIT(0) |
78 | ||
6a12cebd | 79 | #endif |