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6a12cebd | 1 | /* |
3bc599c9 PC |
2 | * Copyright (C) 2016, STMicroelectronics - All Rights Reserved |
3 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. | |
6a12cebd VM |
4 | * |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
ae74de0d PC |
8 | #ifndef _SERIAL_STM32_ |
9 | #define _SERIAL_STM32_ | |
6a12cebd | 10 | |
60a996ba PC |
11 | #define CR1_OFFSET(x) (x ? 0x0c : 0x00) |
12 | #define CR3_OFFSET(x) (x ? 0x14 : 0x08) | |
13 | #define BRR_OFFSET(x) (x ? 0x08 : 0x0c) | |
14 | #define ISR_OFFSET(x) (x ? 0x00 : 0x1c) | |
15 | /* | |
16 | * STM32F4 has one Data Register (DR) for received or transmitted | |
17 | * data, so map Receive Data Register (RDR) and Transmit Data | |
18 | * Register (TDR) at the same offset | |
19 | */ | |
20 | #define RDR_OFFSET(x) (x ? 0x04 : 0x24) | |
21 | #define TDR_OFFSET(x) (x ? 0x04 : 0x28) | |
22 | ||
23 | struct stm32_uart_info { | |
24 | u8 uart_enable_bit; /* UART_CR1_UE */ | |
25 | bool stm32f4; /* true for STM32F4, false otherwise */ | |
26 | bool has_overrun_disable; | |
2a7ecc53 | 27 | bool has_fifo; |
60a996ba PC |
28 | }; |
29 | ||
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30 | struct stm32_uart_info stm32f4_info = { |
31 | .stm32f4 = true, | |
32 | .uart_enable_bit = 13, | |
33 | .has_overrun_disable = false, | |
34 | .has_fifo = false, | |
35 | }; | |
36 | ||
2a7ecc53 | 37 | struct stm32_uart_info stm32f7_info = { |
60a996ba PC |
38 | .uart_enable_bit = 0, |
39 | .stm32f4 = false, | |
40 | .has_overrun_disable = true, | |
2a7ecc53 PC |
41 | .has_fifo = false, |
42 | }; | |
43 | ||
44 | struct stm32_uart_info stm32h7_info = { | |
45 | .uart_enable_bit = 0, | |
46 | .stm32f4 = false, | |
47 | .has_overrun_disable = true, | |
48 | .has_fifo = true, | |
6a12cebd VM |
49 | }; |
50 | ||
122b2d47 PC |
51 | /* Information about a serial port */ |
52 | struct stm32x7_serial_platdata { | |
60a996ba PC |
53 | fdt_addr_t base; /* address of registers in physical memory */ |
54 | struct stm32_uart_info *uart_info; | |
27265cee | 55 | unsigned long int clock_rate; |
122b2d47 | 56 | }; |
6a12cebd | 57 | |
2a7ecc53 | 58 | #define USART_CR1_FIFOEN BIT(29) |
2a52a952 PC |
59 | #define USART_CR1_OVER8 BIT(15) |
60 | #define USART_CR1_TE BIT(3) | |
61 | #define USART_CR1_RE BIT(2) | |
6a12cebd | 62 | |
2a52a952 | 63 | #define USART_CR3_OVRDIS BIT(12) |
6c0c3ce8 | 64 | |
2a52a952 PC |
65 | #define USART_SR_FLAG_RXNE BIT(5) |
66 | #define USART_SR_FLAG_TXE BIT(7) | |
6a12cebd | 67 | |
2a52a952 | 68 | #define USART_BRR_F_MASK GENMASK(7, 0) |
6a12cebd | 69 | #define USART_BRR_M_SHIFT 4 |
2a52a952 | 70 | #define USART_BRR_M_MASK GENMASK(15, 4) |
6a12cebd VM |
71 | |
72 | #endif |