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Commit | Line | Data |
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7f368553 | 1 | /* |
4e3d8406 MY |
2 | * Copyright (C) 2012-2015 Panasonic Corporation |
3 | * Copyright (C) 2015-2016 Socionext Inc. | |
4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
7f368553 | 5 | * |
7f368553 MY |
6 | * SPDX-License-Identifier: GPL-2.0+ |
7 | */ | |
8 | ||
9d922450 | 9 | #include <dm.h> |
f6e7f07c | 10 | #include <linux/io.h> |
325b708a | 11 | #include <linux/serial_reg.h> |
b37a1cce | 12 | #include <linux/sizes.h> |
1221ce45 | 13 | #include <linux/errno.h> |
7f368553 | 14 | #include <serial.h> |
625177d2 | 15 | #include <fdtdec.h> |
7f368553 | 16 | |
7f368553 MY |
17 | /* |
18 | * Note: Register map is slightly different from that of 16550. | |
19 | */ | |
20 | struct uniphier_serial { | |
d0c47b3e MY |
21 | u32 rx; /* In: Receive buffer */ |
22 | #define tx rx /* Out: Transmit buffer */ | |
23 | u32 ier; /* Interrupt Enable Register */ | |
24 | u32 iir; /* In: Interrupt ID Register */ | |
25 | u32 char_fcr; /* Charactor / FIFO Control Register */ | |
26 | u32 lcr_mcr; /* Line/Modem Control Register */ | |
27 | #define LCR_SHIFT 8 | |
28 | #define LCR_MASK (0xff << (LCR_SHIFT)) | |
29 | u32 lsr; /* In: Line Status Register */ | |
30 | u32 msr; /* In: Modem Status Register */ | |
31 | u32 __rsv0; | |
32 | u32 __rsv1; | |
33 | u32 dlr; /* Divisor Latch Register */ | |
7f368553 MY |
34 | }; |
35 | ||
d064cbff MY |
36 | struct uniphier_serial_private_data { |
37 | struct uniphier_serial __iomem *membase; | |
6d99cfae | 38 | unsigned int uartclk; |
d064cbff MY |
39 | }; |
40 | ||
41 | #define uniphier_serial_port(dev) \ | |
42 | ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase | |
7f368553 | 43 | |
d9bc8fd1 | 44 | static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) |
7f368553 | 45 | { |
6d99cfae | 46 | struct uniphier_serial_private_data *priv = dev_get_priv(dev); |
d064cbff | 47 | struct uniphier_serial __iomem *port = uniphier_serial_port(dev); |
7f368553 MY |
48 | const unsigned int mode_x_div = 16; |
49 | unsigned int divisor; | |
7f368553 | 50 | |
6d99cfae | 51 | divisor = DIV_ROUND_CLOSEST(priv->uartclk, mode_x_div * baudrate); |
7f368553 | 52 | |
d0c47b3e | 53 | writel(divisor, &port->dlr); |
7f368553 | 54 | |
d064cbff | 55 | return 0; |
7f368553 MY |
56 | } |
57 | ||
d064cbff | 58 | static int uniphier_serial_getc(struct udevice *dev) |
7f368553 | 59 | { |
d064cbff | 60 | struct uniphier_serial __iomem *port = uniphier_serial_port(dev); |
7f368553 | 61 | |
d0c47b3e | 62 | if (!(readl(&port->lsr) & UART_LSR_DR)) |
d064cbff | 63 | return -EAGAIN; |
7f368553 | 64 | |
d0c47b3e | 65 | return readl(&port->rx); |
7f368553 MY |
66 | } |
67 | ||
d064cbff | 68 | static int uniphier_serial_putc(struct udevice *dev, const char c) |
7f368553 | 69 | { |
d064cbff | 70 | struct uniphier_serial __iomem *port = uniphier_serial_port(dev); |
7f368553 | 71 | |
d0c47b3e | 72 | if (!(readl(&port->lsr) & UART_LSR_THRE)) |
d064cbff | 73 | return -EAGAIN; |
7f368553 | 74 | |
d0c47b3e | 75 | writel(c, &port->tx); |
d064cbff MY |
76 | |
77 | return 0; | |
7f368553 MY |
78 | } |
79 | ||
bb72148b MY |
80 | static int uniphier_serial_pending(struct udevice *dev, bool input) |
81 | { | |
82 | struct uniphier_serial __iomem *port = uniphier_serial_port(dev); | |
83 | ||
84 | if (input) | |
d0c47b3e | 85 | return readl(&port->lsr) & UART_LSR_DR; |
bb72148b | 86 | else |
d0c47b3e | 87 | return !(readl(&port->lsr) & UART_LSR_THRE); |
bb72148b MY |
88 | } |
89 | ||
d9bc8fd1 | 90 | static int uniphier_serial_probe(struct udevice *dev) |
d064cbff | 91 | { |
6d99cfae | 92 | DECLARE_GLOBAL_DATA_PTR; |
d064cbff | 93 | struct uniphier_serial_private_data *priv = dev_get_priv(dev); |
099cf77c | 94 | struct uniphier_serial __iomem *port; |
6d99cfae | 95 | fdt_addr_t base; |
6d99cfae | 96 | u32 tmp; |
7f368553 | 97 | |
a821c4af | 98 | base = devfdt_get_addr(dev); |
b37a1cce MY |
99 | if (base == FDT_ADDR_T_NONE) |
100 | return -EINVAL; | |
6d99cfae | 101 | |
4e3d8406 | 102 | port = devm_ioremap(dev, base, SZ_64); |
099cf77c | 103 | if (!port) |
d064cbff | 104 | return -ENOMEM; |
7f368553 | 105 | |
099cf77c MY |
106 | priv->membase = port; |
107 | ||
e160f7d4 | 108 | priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), |
6d99cfae MY |
109 | "clock-frequency", 0); |
110 | ||
099cf77c MY |
111 | tmp = readl(&port->lcr_mcr); |
112 | tmp &= ~LCR_MASK; | |
113 | tmp |= UART_LCR_WLEN8 << LCR_SHIFT; | |
114 | writel(tmp, &port->lcr_mcr); | |
115 | ||
d064cbff MY |
116 | return 0; |
117 | } | |
118 | ||
625177d2 | 119 | static const struct udevice_id uniphier_uart_of_match[] = { |
6462cded MY |
120 | { .compatible = "socionext,uniphier-uart" }, |
121 | { /* sentinel */ } | |
d064cbff MY |
122 | }; |
123 | ||
d064cbff MY |
124 | static const struct dm_serial_ops uniphier_serial_ops = { |
125 | .setbrg = uniphier_serial_setbrg, | |
126 | .getc = uniphier_serial_getc, | |
127 | .putc = uniphier_serial_putc, | |
bb72148b | 128 | .pending = uniphier_serial_pending, |
d064cbff MY |
129 | }; |
130 | ||
131 | U_BOOT_DRIVER(uniphier_serial) = { | |
6d99cfae | 132 | .name = "uniphier-uart", |
d064cbff | 133 | .id = UCLASS_SERIAL, |
6d99cfae | 134 | .of_match = uniphier_uart_of_match, |
d064cbff | 135 | .probe = uniphier_serial_probe, |
d064cbff | 136 | .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data), |
d064cbff | 137 | .ops = &uniphier_serial_ops, |
d064cbff | 138 | }; |