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194846f3 MS |
1 | /* |
2 | * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> | |
3 | * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
194846f3 MS |
6 | */ |
7 | ||
59da82ef | 8 | #include <clk.h> |
194846f3 | 9 | #include <common.h> |
42800ffa SG |
10 | #include <debug_uart.h> |
11 | #include <dm.h> | |
c54c0a4c | 12 | #include <errno.h> |
c9416b92 | 13 | #include <fdtdec.h> |
194846f3 MS |
14 | #include <watchdog.h> |
15 | #include <asm/io.h> | |
16 | #include <linux/compiler.h> | |
17 | #include <serial.h> | |
bf834950 | 18 | #include <asm/arch/hardware.h> |
194846f3 | 19 | |
c9416b92 MS |
20 | DECLARE_GLOBAL_DATA_PTR; |
21 | ||
6cd0f2a6 | 22 | #define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ |
42800ffa | 23 | #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ |
194846f3 MS |
24 | #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
25 | ||
26 | #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ | |
27 | #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ | |
28 | #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ | |
29 | #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ | |
30 | ||
31 | #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ | |
32 | ||
194846f3 | 33 | struct uart_zynq { |
a2425e62 MS |
34 | u32 control; /* 0x0 - Control Register [8:0] */ |
35 | u32 mode; /* 0x4 - Mode Register [10:0] */ | |
194846f3 | 36 | u32 reserved1[4]; |
a2425e62 | 37 | u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ |
194846f3 | 38 | u32 reserved2[4]; |
a2425e62 MS |
39 | u32 channel_sts; /* 0x2c - Channel Status [11:0] */ |
40 | u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ | |
41 | u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ | |
194846f3 MS |
42 | }; |
43 | ||
42800ffa SG |
44 | struct zynq_uart_priv { |
45 | struct uart_zynq *regs; | |
bf834950 MS |
46 | }; |
47 | ||
194846f3 | 48 | /* Set up the baud rate in gd struct */ |
c54c0a4c SG |
49 | static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, |
50 | unsigned long clock, unsigned long baud) | |
194846f3 MS |
51 | { |
52 | /* Calculation results. */ | |
53 | unsigned int calc_bauderror, bdiv, bgen; | |
54 | unsigned long calc_baud = 0; | |
194846f3 | 55 | |
04bc5c93 | 56 | /* Covering case where input clock is so slow */ |
c54c0a4c SG |
57 | if (clock < 1000000 && baud > 4800) |
58 | baud = 4800; | |
04bc5c93 | 59 | |
194846f3 MS |
60 | /* master clock |
61 | * Baud rate = ------------------ | |
62 | * bgen * (bdiv + 1) | |
63 | * | |
64 | * Find acceptable values for baud generation. | |
65 | */ | |
66 | for (bdiv = 4; bdiv < 255; bdiv++) { | |
67 | bgen = clock / (baud * (bdiv + 1)); | |
68 | if (bgen < 2 || bgen > 65535) | |
69 | continue; | |
70 | ||
71 | calc_baud = clock / (bgen * (bdiv + 1)); | |
72 | ||
73 | /* | |
74 | * Use first calculated baudrate with | |
75 | * an acceptable (<3%) error | |
76 | */ | |
77 | if (baud > calc_baud) | |
78 | calc_bauderror = baud - calc_baud; | |
79 | else | |
80 | calc_bauderror = calc_baud - baud; | |
81 | if (((calc_bauderror * 100) / baud) < 3) | |
82 | break; | |
83 | } | |
84 | ||
85 | writel(bdiv, ®s->baud_rate_divider); | |
86 | writel(bgen, ®s->baud_rate_gen); | |
87 | } | |
88 | ||
c54c0a4c SG |
89 | /* Initialize the UART, with...some settings. */ |
90 | static void _uart_zynq_serial_init(struct uart_zynq *regs) | |
91 | { | |
194846f3 MS |
92 | /* RX/TX enabled & reset */ |
93 | writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ | |
94 | ZYNQ_UART_CR_RXRST, ®s->control); | |
95 | writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ | |
c54c0a4c SG |
96 | } |
97 | ||
c54c0a4c SG |
98 | static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) |
99 | { | |
6cd0f2a6 | 100 | if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) |
c54c0a4c SG |
101 | return -EAGAIN; |
102 | ||
103 | writel(c, ®s->tx_rx_fifo); | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
42800ffa | 108 | int zynq_serial_setbrg(struct udevice *dev, int baudrate) |
194846f3 | 109 | { |
42800ffa | 110 | struct zynq_uart_priv *priv = dev_get_priv(dev); |
59da82ef | 111 | unsigned long clock; |
194846f3 | 112 | |
59da82ef MS |
113 | int ret; |
114 | struct clk clk; | |
115 | ||
116 | ret = clk_get_by_index(dev, 0, &clk); | |
117 | if (ret < 0) { | |
118 | dev_err(dev, "failed to get clock\n"); | |
119 | return ret; | |
120 | } | |
121 | ||
122 | clock = clk_get_rate(&clk); | |
123 | if (IS_ERR_VALUE(clock)) { | |
124 | dev_err(dev, "failed to get rate\n"); | |
125 | return clock; | |
126 | } | |
127 | debug("%s: CLK %ld\n", __func__, clock); | |
128 | ||
129 | ret = clk_enable(&clk); | |
130 | if (ret && ret != -ENOSYS) { | |
131 | dev_err(dev, "failed to enable clock\n"); | |
132 | return ret; | |
133 | } | |
781745bd | 134 | |
42800ffa | 135 | _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); |
194846f3 | 136 | |
42800ffa | 137 | return 0; |
194846f3 MS |
138 | } |
139 | ||
42800ffa | 140 | static int zynq_serial_probe(struct udevice *dev) |
194846f3 | 141 | { |
42800ffa | 142 | struct zynq_uart_priv *priv = dev_get_priv(dev); |
194846f3 | 143 | |
42800ffa | 144 | _uart_zynq_serial_init(priv->regs); |
194846f3 | 145 | |
42800ffa | 146 | return 0; |
194846f3 MS |
147 | } |
148 | ||
42800ffa | 149 | static int zynq_serial_getc(struct udevice *dev) |
194846f3 | 150 | { |
42800ffa SG |
151 | struct zynq_uart_priv *priv = dev_get_priv(dev); |
152 | struct uart_zynq *regs = priv->regs; | |
153 | ||
154 | if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) | |
155 | return -EAGAIN; | |
194846f3 | 156 | |
194846f3 MS |
157 | return readl(®s->tx_rx_fifo); |
158 | } | |
159 | ||
42800ffa SG |
160 | static int zynq_serial_putc(struct udevice *dev, const char ch) |
161 | { | |
162 | struct zynq_uart_priv *priv = dev_get_priv(dev); | |
194846f3 | 163 | |
42800ffa SG |
164 | return _uart_zynq_serial_putc(priv->regs, ch); |
165 | } | |
194846f3 | 166 | |
42800ffa | 167 | static int zynq_serial_pending(struct udevice *dev, bool input) |
c9416b92 | 168 | { |
42800ffa SG |
169 | struct zynq_uart_priv *priv = dev_get_priv(dev); |
170 | struct uart_zynq *regs = priv->regs; | |
c9416b92 | 171 | |
42800ffa SG |
172 | if (input) |
173 | return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); | |
174 | else | |
175 | return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); | |
176 | } | |
c9416b92 | 177 | |
42800ffa SG |
178 | static int zynq_serial_ofdata_to_platdata(struct udevice *dev) |
179 | { | |
180 | struct zynq_uart_priv *priv = dev_get_priv(dev); | |
c9416b92 | 181 | |
a821c4af | 182 | priv->regs = (struct uart_zynq *)devfdt_get_addr(dev); |
c9416b92 | 183 | |
42800ffa | 184 | return 0; |
c9416b92 | 185 | } |
51d8102f | 186 | |
42800ffa SG |
187 | static const struct dm_serial_ops zynq_serial_ops = { |
188 | .putc = zynq_serial_putc, | |
189 | .pending = zynq_serial_pending, | |
190 | .getc = zynq_serial_getc, | |
191 | .setbrg = zynq_serial_setbrg, | |
192 | }; | |
193 | ||
194 | static const struct udevice_id zynq_serial_ids[] = { | |
195 | { .compatible = "xlnx,xuartps" }, | |
196 | { .compatible = "cdns,uart-r1p8" }, | |
a2533183 | 197 | { .compatible = "cdns,uart-r1p12" }, |
42800ffa SG |
198 | { } |
199 | }; | |
200 | ||
6bf87dac | 201 | U_BOOT_DRIVER(serial_zynq) = { |
42800ffa SG |
202 | .name = "serial_zynq", |
203 | .id = UCLASS_SERIAL, | |
204 | .of_match = zynq_serial_ids, | |
205 | .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, | |
206 | .priv_auto_alloc_size = sizeof(struct zynq_uart_priv), | |
207 | .probe = zynq_serial_probe, | |
208 | .ops = &zynq_serial_ops, | |
209 | .flags = DM_FLAG_PRE_RELOC, | |
210 | }; | |
c54c0a4c SG |
211 | |
212 | #ifdef CONFIG_DEBUG_UART_ZYNQ | |
80dc9997 | 213 | static inline void _debug_uart_init(void) |
c54c0a4c SG |
214 | { |
215 | struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; | |
216 | ||
217 | _uart_zynq_serial_init(regs); | |
218 | _uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, | |
219 | CONFIG_BAUDRATE); | |
220 | } | |
221 | ||
222 | static inline void _debug_uart_putc(int ch) | |
223 | { | |
224 | struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; | |
225 | ||
226 | while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) | |
227 | WATCHDOG_RESET(); | |
228 | } | |
229 | ||
230 | DEBUG_UART_FUNCS | |
231 | ||
232 | #endif |