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3d3befa7 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * ARM Ltd. | |
7 | * Philippe Robin, <philippe.robin@arm.com> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | /* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ | |
29 | /* Should be fairly simple to make it work with the PL010 as well */ | |
30 | ||
31 | #include <common.h> | |
32 | ||
33 | #ifdef CFG_PL011_SERIAL | |
34 | ||
35 | #include "serial_pl011.h" | |
36 | ||
37 | #define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) | |
38 | #define IO_READ(addr) (*(volatile unsigned int *)(addr)) | |
39 | ||
40 | /* | |
42dfe7a1 | 41 | * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 |
3d3befa7 WD |
42 | * Versatile PB has four UARTs. |
43 | */ | |
6705d81e | 44 | |
3d3befa7 WD |
45 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
46 | #define baudRate CONFIG_BAUDRATE | |
6705d81e WD |
47 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
48 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) | |
3d3befa7 | 49 | |
42dfe7a1 WD |
50 | static void pl011_putc (int portnum, char c); |
51 | static int pl011_getc (int portnum); | |
52 | static int pl011_tstc (int portnum); | |
3d3befa7 WD |
53 | |
54 | ||
55 | int serial_init (void) | |
56 | { | |
42dfe7a1 WD |
57 | unsigned int temp; |
58 | unsigned int divider; | |
59 | unsigned int remainder; | |
60 | unsigned int fraction; | |
61 | ||
62 | /* | |
63 | ** First, disable everything. | |
64 | */ | |
65 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); | |
66 | ||
67 | /* | |
68 | ** Set baud rate | |
69 | ** | |
70 | ** IBRD = UART_CLK / (16 * BAUD_RATE) | |
71 | ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) | |
72 | */ | |
42dfe7a1 | 73 | temp = 16 * baudRate; |
6705d81e WD |
74 | divider = CONFIG_PL011_CLOCK / temp; |
75 | remainder = CONFIG_PL011_CLOCK % temp; | |
42dfe7a1 WD |
76 | temp = (8 * remainder) / baudRate; |
77 | fraction = (temp >> 1) + (temp & 1); | |
42dfe7a1 WD |
78 | |
79 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); | |
80 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); | |
81 | ||
82 | /* | |
83 | ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. | |
84 | */ | |
85 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, | |
86 | (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); | |
87 | ||
88 | /* | |
89 | ** Finally, enable the UART | |
90 | */ | |
91 | IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, | |
92 | (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | | |
93 | UART_PL011_CR_RXE)); | |
94 | ||
6705d81e | 95 | return 0; |
3d3befa7 WD |
96 | } |
97 | ||
42dfe7a1 | 98 | void serial_putc (const char c) |
3d3befa7 WD |
99 | { |
100 | if (c == '\n') | |
42dfe7a1 | 101 | pl011_putc (CONSOLE_PORT, '\r'); |
3d3befa7 | 102 | |
42dfe7a1 | 103 | pl011_putc (CONSOLE_PORT, c); |
3d3befa7 WD |
104 | } |
105 | ||
42dfe7a1 | 106 | void serial_puts (const char *s) |
3d3befa7 WD |
107 | { |
108 | while (*s) { | |
109 | serial_putc (*s++); | |
110 | } | |
111 | } | |
112 | ||
42dfe7a1 | 113 | int serial_getc (void) |
3d3befa7 | 114 | { |
42dfe7a1 | 115 | return pl011_getc (CONSOLE_PORT); |
3d3befa7 WD |
116 | } |
117 | ||
42dfe7a1 | 118 | int serial_tstc (void) |
3d3befa7 | 119 | { |
42dfe7a1 | 120 | return pl011_tstc (CONSOLE_PORT); |
3d3befa7 WD |
121 | } |
122 | ||
42dfe7a1 | 123 | void serial_setbrg (void) |
3d3befa7 WD |
124 | { |
125 | } | |
126 | ||
42dfe7a1 | 127 | static void pl011_putc (int portnum, char c) |
3d3befa7 | 128 | { |
42dfe7a1 WD |
129 | /* Wait until there is space in the FIFO */ |
130 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); | |
131 | ||
132 | /* Send the character */ | |
133 | IO_WRITE (port[portnum] + UART_PL01x_DR, c); | |
3d3befa7 WD |
134 | } |
135 | ||
42dfe7a1 | 136 | static int pl011_getc (int portnum) |
3d3befa7 | 137 | { |
42dfe7a1 WD |
138 | unsigned int data; |
139 | ||
140 | /* Wait until there is data in the FIFO */ | |
141 | while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); | |
142 | ||
143 | data = IO_READ (port[portnum] + UART_PL01x_DR); | |
144 | ||
145 | /* Check for an error flag */ | |
146 | if (data & 0xFFFFFF00) { | |
147 | /* Clear the error */ | |
148 | IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); | |
149 | return -1; | |
150 | } | |
151 | ||
152 | return (int) data; | |
3d3befa7 WD |
153 | } |
154 | ||
42dfe7a1 | 155 | static int pl011_tstc (int portnum) |
3d3befa7 | 156 | { |
42dfe7a1 WD |
157 | return !(IO_READ (port[portnum] + UART_PL01x_FR) & |
158 | UART_PL01x_FR_RXFE); | |
3d3befa7 WD |
159 | } |
160 | ||
161 | #endif |