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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.c | |
3 | . This is a driver for SMSC's 91C111 single-chip Ethernet device. | |
4 | . | |
5 | . (C) Copyright 2002 | |
6 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | . Rolf Offermanns <rof@sysgo.de> | |
8 | . | |
9 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
42dfe7a1 | 10 | . Developed by Simple Network Magic Corporation (SNMC) |
fe8c2806 WD |
11 | . Copyright (C) 1996 by Erik Stahlman (ES) |
12 | . | |
13 | . This program is free software; you can redistribute it and/or modify | |
14 | . it under the terms of the GNU General Public License as published by | |
15 | . the Free Software Foundation; either version 2 of the License, or | |
16 | . (at your option) any later version. | |
17 | . | |
18 | . This program is distributed in the hope that it will be useful, | |
19 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
42dfe7a1 | 20 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
fe8c2806 WD |
21 | . GNU General Public License for more details. |
22 | . | |
23 | . You should have received a copy of the GNU General Public License | |
24 | . along with this program; if not, write to the Free Software | |
42dfe7a1 | 25 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
fe8c2806 WD |
26 | . |
27 | . Information contained in this file was obtained from the LAN91C111 | |
28 | . manual from SMC. To get a copy, if you really want one, you can find | |
29 | . information under www.smsc.com. | |
30 | . | |
31 | . | |
32 | . "Features" of the SMC chip: | |
33 | . Integrated PHY/MAC for 10/100BaseT Operation | |
34 | . Supports internal and external MII | |
35 | . Integrated 8K packet memory | |
36 | . EEPROM interface for configuration | |
37 | . | |
38 | . Arguments: | |
42dfe7a1 | 39 | . io = for the base address |
fe8c2806 WD |
40 | . irq = for the IRQ |
41 | . | |
42 | . author: | |
42dfe7a1 WD |
43 | . Erik Stahlman ( erik@vt.edu ) |
44 | . Daris A Nevil ( dnevil@snmc.com ) | |
fe8c2806 WD |
45 | . |
46 | . | |
47 | . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) | |
48 | . | |
49 | . Sources: | |
42dfe7a1 WD |
50 | . o SMSC LAN91C111 databook (www.smsc.com) |
51 | . o smc9194.c by Erik Stahlman | |
52 | . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) | |
fe8c2806 WD |
53 | . |
54 | . History: | |
42dfe7a1 | 55 | . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. |
fe8c2806 | 56 | . 10/17/01 Marco Hasewinkel Modify for DNP/1110 |
42dfe7a1 WD |
57 | . 07/25/01 Woojung Huh Modify for ADS Bitsy |
58 | . 04/25/01 Daris A Nevil Initial public release through SMSC | |
59 | . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 | |
fe8c2806 WD |
60 | ----------------------------------------------------------------------------*/ |
61 | ||
62 | #include <common.h> | |
63 | #include <command.h> | |
f39748ae | 64 | #include <config.h> |
fe8c2806 WD |
65 | #include "smc91111.h" |
66 | #include <net.h> | |
67 | ||
68 | #ifdef CONFIG_DRIVER_SMC91111 | |
69 | ||
70 | /* Use power-down feature of the chip */ | |
71 | #define POWER_DOWN 0 | |
72 | ||
73 | #define NO_AUTOPROBE | |
74 | ||
8bf3b005 WD |
75 | #define SMC_DEBUG 0 |
76 | ||
77 | #if SMC_DEBUG > 1 | |
fe8c2806 WD |
78 | static const char version[] = |
79 | "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; | |
8bf3b005 | 80 | #endif |
fe8c2806 | 81 | |
f39748ae WD |
82 | /* Autonegotiation timeout in seconds */ |
83 | #ifndef CONFIG_SMC_AUTONEG_TIMEOUT | |
84 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 | |
85 | #endif | |
86 | ||
fe8c2806 WD |
87 | /*------------------------------------------------------------------------ |
88 | . | |
89 | . Configuration options, for the experienced user to change. | |
90 | . | |
91 | -------------------------------------------------------------------------*/ | |
92 | ||
93 | /* | |
94 | . Wait time for memory to be free. This probably shouldn't be | |
95 | . tuned that much, as waiting for this means nothing else happens | |
96 | . in the system | |
97 | */ | |
98 | #define MEMORY_WAIT_TIME 16 | |
99 | ||
100 | ||
101 | #if (SMC_DEBUG > 2 ) | |
102 | #define PRINTK3(args...) printf(args) | |
103 | #else | |
104 | #define PRINTK3(args...) | |
105 | #endif | |
106 | ||
107 | #if SMC_DEBUG > 1 | |
108 | #define PRINTK2(args...) printf(args) | |
109 | #else | |
110 | #define PRINTK2(args...) | |
111 | #endif | |
112 | ||
113 | #ifdef SMC_DEBUG | |
114 | #define PRINTK(args...) printf(args) | |
115 | #else | |
116 | #define PRINTK(args...) | |
117 | #endif | |
118 | ||
119 | ||
120 | /*------------------------------------------------------------------------ | |
121 | . | |
42dfe7a1 | 122 | . The internal workings of the driver. If you are changing anything |
fe8c2806 WD |
123 | . here with the SMC stuff, you should have the datasheet and know |
124 | . what you are doing. | |
125 | . | |
126 | -------------------------------------------------------------------------*/ | |
127 | #define CARDNAME "LAN91C111" | |
128 | ||
129 | /* Memory sizing constant */ | |
130 | #define LAN91C111_MEMORY_MULTIPLIER (1024*2) | |
131 | ||
132 | #ifndef CONFIG_SMC91111_BASE | |
133 | #define CONFIG_SMC91111_BASE 0x20000300 | |
134 | #endif | |
135 | ||
136 | #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE | |
137 | ||
138 | #define SMC_DEV_NAME "SMC91111" | |
139 | #define SMC_PHY_ADDR 0x0000 | |
140 | #define SMC_ALLOC_MAX_TRY 5 | |
141 | #define SMC_TX_TIMEOUT 30 | |
142 | ||
143 | #define SMC_PHY_CLOCK_DELAY 1000 | |
144 | ||
145 | #define ETH_ZLEN 60 | |
146 | ||
42dfe7a1 | 147 | #ifdef CONFIG_SMC_USE_32_BIT |
fe8c2806 WD |
148 | #define USE_32_BIT 1 |
149 | #else | |
150 | #undef USE_32_BIT | |
151 | #endif | |
152 | /*----------------------------------------------------------------- | |
153 | . | |
154 | . The driver can be entered at any of the following entry points. | |
155 | . | |
156 | .------------------------------------------------------------------ */ | |
157 | ||
158 | extern int eth_init(bd_t *bd); | |
159 | extern void eth_halt(void); | |
160 | extern int eth_rx(void); | |
161 | extern int eth_send(volatile void *packet, int length); | |
162 | ||
163 | ||
fe8c2806 WD |
164 | /* |
165 | . This is called by register_netdev(). It is responsible for | |
166 | . checking the portlist for the SMC9000 series chipset. If it finds | |
167 | . one, then it will initialize the device, find the hardware information, | |
168 | . and sets up the appropriate device parameters. | |
169 | . NOTE: Interrupts are *OFF* when this procedure is called. | |
170 | . | |
171 | . NB:This shouldn't be static since it is referred to externally. | |
172 | */ | |
173 | int smc_init(void); | |
174 | ||
175 | /* | |
176 | . This is called by unregister_netdev(). It is responsible for | |
177 | . cleaning up before the driver is finally unregistered and discarded. | |
178 | */ | |
179 | void smc_destructor(void); | |
180 | ||
181 | /* | |
182 | . The kernel calls this function when someone wants to use the device, | |
183 | . typically 'ifconfig ethX up'. | |
184 | */ | |
0b97ab14 | 185 | static int smc_open(bd_t *bd); |
fe8c2806 WD |
186 | |
187 | ||
188 | /* | |
189 | . This is called by the kernel in response to 'ifconfig ethX down'. It | |
190 | . is responsible for cleaning up everything that the open routine | |
191 | . does, and maybe putting the card into a powerdown state. | |
192 | */ | |
193 | static int smc_close(void); | |
194 | ||
195 | /* | |
196 | . Configures the PHY through the MII Management interface | |
197 | */ | |
198 | #ifndef CONFIG_SMC91111_EXT_PHY | |
199 | static void smc_phy_configure(void); | |
200 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
201 | ||
202 | /* | |
203 | . This is a separate procedure to handle the receipt of a packet, to | |
204 | . leave the interrupt code looking slightly cleaner | |
205 | */ | |
206 | static int smc_rcv(void); | |
207 | ||
0b97ab14 | 208 | /* See if a MAC address is defined in the current environment. If so use it. If not |
8bde7f77 | 209 | . print a warning and set the environment and other globals with the default. |
0b97ab14 WD |
210 | . If an EEPROM is present it really should be consulted. |
211 | */ | |
212 | int smc_get_ethaddr(bd_t *bd); | |
213 | int get_rom_mac(char *v_rom_mac); | |
fe8c2806 WD |
214 | |
215 | /* | |
216 | ------------------------------------------------------------ | |
217 | . | |
218 | . Internal routines | |
219 | . | |
220 | ------------------------------------------------------------ | |
221 | */ | |
222 | ||
8bf3b005 | 223 | static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; |
fe8c2806 WD |
224 | |
225 | /* | |
226 | * This function must be called before smc_open() if you want to override | |
227 | * the default mac address. | |
228 | */ | |
229 | ||
230 | void smc_set_mac_addr(const char *addr) { | |
231 | int i; | |
232 | ||
233 | for (i=0; i < sizeof(smc_mac_addr); i++){ | |
234 | smc_mac_addr[i] = addr[i]; | |
235 | } | |
236 | } | |
237 | ||
238 | /* | |
239 | * smc_get_macaddr is no longer used. If you want to override the default | |
0b97ab14 | 240 | * mac address, call smc_get_mac_addr as a part of the board initialization. |
fe8c2806 WD |
241 | */ |
242 | ||
243 | #if 0 | |
244 | void smc_get_macaddr( byte *addr ) { | |
245 | /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ | |
8bde7f77 | 246 | unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); |
fe8c2806 WD |
247 | int i; |
248 | ||
249 | ||
8bde7f77 WD |
250 | for (i=0; i<6; i++) { |
251 | addr[0] = *(dnp1110_mac+0); | |
252 | addr[1] = *(dnp1110_mac+1); | |
253 | addr[2] = *(dnp1110_mac+2); | |
254 | addr[3] = *(dnp1110_mac+3); | |
255 | addr[4] = *(dnp1110_mac+4); | |
256 | addr[5] = *(dnp1110_mac+5); | |
257 | } | |
fe8c2806 WD |
258 | } |
259 | #endif /* 0 */ | |
260 | ||
261 | /*********************************************** | |
42dfe7a1 | 262 | * Show available memory * |
fe8c2806 WD |
263 | ***********************************************/ |
264 | void dump_memory_info(void) | |
265 | { | |
8bde7f77 WD |
266 | word mem_info; |
267 | word old_bank; | |
fe8c2806 | 268 | |
8bde7f77 | 269 | old_bank = SMC_inw(BANK_SELECT)&0xF; |
fe8c2806 | 270 | |
8bde7f77 WD |
271 | SMC_SELECT_BANK(0); |
272 | mem_info = SMC_inw( MIR_REG ); | |
273 | PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); | |
fe8c2806 | 274 | |
8bde7f77 | 275 | SMC_SELECT_BANK(old_bank); |
fe8c2806 WD |
276 | } |
277 | /* | |
278 | . A rather simple routine to print out a packet for debugging purposes. | |
279 | */ | |
280 | #if SMC_DEBUG > 2 | |
281 | static void print_packet( byte *, int ); | |
282 | #endif | |
283 | ||
284 | #define tx_done(dev) 1 | |
285 | ||
286 | ||
fe8c2806 WD |
287 | /* this does a soft reset on the device */ |
288 | static void smc_reset( void ); | |
289 | ||
290 | /* Enable Interrupts, Receive, and Transmit */ | |
291 | static void smc_enable( void ); | |
292 | ||
293 | /* this puts the device in an inactive state */ | |
294 | static void smc_shutdown( void ); | |
295 | ||
296 | /* Routines to Read and Write the PHY Registers across the | |
297 | MII Management Interface | |
298 | */ | |
299 | ||
300 | #ifndef CONFIG_SMC91111_EXT_PHY | |
301 | static word smc_read_phy_register(byte phyreg); | |
302 | static void smc_write_phy_register(byte phyreg, word phydata); | |
303 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
304 | ||
305 | ||
b56ddc63 WD |
306 | static int poll4int (byte mask, int timeout) |
307 | { | |
308 | int tmo = get_timer (0) + timeout * CFG_HZ; | |
309 | int is_timeout = 0; | |
310 | word old_bank = SMC_inw (BSR_REG); | |
311 | ||
312 | PRINTK2 ("Polling...\n"); | |
313 | SMC_SELECT_BANK (2); | |
314 | while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { | |
315 | if (get_timer (0) >= tmo) { | |
316 | is_timeout = 1; | |
317 | break; | |
318 | } | |
fe8c2806 | 319 | } |
fe8c2806 | 320 | |
b56ddc63 WD |
321 | /* restore old bank selection */ |
322 | SMC_SELECT_BANK (old_bank); | |
fe8c2806 | 323 | |
b56ddc63 WD |
324 | if (is_timeout) |
325 | return 1; | |
326 | else | |
327 | return 0; | |
fe8c2806 WD |
328 | } |
329 | ||
487778b7 | 330 | /* Only one release command at a time, please */ |
b56ddc63 | 331 | static inline void smc_wait_mmu_release_complete (void) |
487778b7 WD |
332 | { |
333 | int count = 0; | |
b56ddc63 | 334 | |
487778b7 | 335 | /* assume bank 2 selected */ |
b56ddc63 WD |
336 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
337 | udelay (1); /* Wait until not busy */ | |
338 | if (++count > 200) | |
339 | break; | |
487778b7 WD |
340 | } |
341 | } | |
342 | ||
fe8c2806 WD |
343 | /* |
344 | . Function: smc_reset( void ) | |
345 | . Purpose: | |
42dfe7a1 WD |
346 | . This sets the SMC91111 chip to its normal state, hopefully from whatever |
347 | . mess that any other DOS driver has put it in. | |
fe8c2806 WD |
348 | . |
349 | . Maybe I should reset more registers to defaults in here? SOFTRST should | |
350 | . do that for me. | |
351 | . | |
352 | . Method: | |
353 | . 1. send a SOFT RESET | |
354 | . 2. wait for it to finish | |
355 | . 3. enable autorelease mode | |
356 | . 4. reset the memory management unit | |
357 | . 5. clear all interrupts | |
358 | . | |
359 | */ | |
b56ddc63 | 360 | static void smc_reset (void) |
fe8c2806 | 361 | { |
f39748ae | 362 | PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); |
fe8c2806 WD |
363 | |
364 | /* This resets the registers mostly to defaults, but doesn't | |
365 | affect EEPROM. That seems unnecessary */ | |
b56ddc63 WD |
366 | SMC_SELECT_BANK (0); |
367 | SMC_outw (RCR_SOFTRST, RCR_REG); | |
fe8c2806 WD |
368 | |
369 | /* Setup the Configuration Register */ | |
370 | /* This is necessary because the CONFIG_REG is not affected */ | |
371 | /* by a soft reset */ | |
372 | ||
b56ddc63 | 373 | SMC_SELECT_BANK (1); |
fe8c2806 | 374 | #if defined(CONFIG_SMC91111_EXT_PHY) |
b56ddc63 | 375 | SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); |
fe8c2806 | 376 | #else |
b56ddc63 | 377 | SMC_outw (CONFIG_DEFAULT, CONFIG_REG); |
fe8c2806 WD |
378 | #endif |
379 | ||
380 | ||
381 | /* Release from possible power-down state */ | |
382 | /* Configuration register is not affected by Soft Reset */ | |
b56ddc63 | 383 | SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); |
fe8c2806 | 384 | |
b56ddc63 | 385 | SMC_SELECT_BANK (0); |
fe8c2806 WD |
386 | |
387 | /* this should pause enough for the chip to be happy */ | |
b56ddc63 | 388 | udelay (10); |
fe8c2806 WD |
389 | |
390 | /* Disable transmit and receive functionality */ | |
b56ddc63 WD |
391 | SMC_outw (RCR_CLEAR, RCR_REG); |
392 | SMC_outw (TCR_CLEAR, TCR_REG); | |
fe8c2806 WD |
393 | |
394 | /* set the control register */ | |
b56ddc63 WD |
395 | SMC_SELECT_BANK (1); |
396 | SMC_outw (CTL_DEFAULT, CTL_REG); | |
fe8c2806 WD |
397 | |
398 | /* Reset the MMU */ | |
b56ddc63 WD |
399 | SMC_SELECT_BANK (2); |
400 | smc_wait_mmu_release_complete (); | |
401 | SMC_outw (MC_RESET, MMU_CMD_REG); | |
402 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) | |
403 | udelay (1); /* Wait until not busy */ | |
fe8c2806 WD |
404 | |
405 | /* Note: It doesn't seem that waiting for the MMU busy is needed here, | |
406 | but this is a place where future chipsets _COULD_ break. Be wary | |
8bde7f77 | 407 | of issuing another MMU command right after this */ |
fe8c2806 WD |
408 | |
409 | /* Disable all interrupts */ | |
b56ddc63 | 410 | SMC_outb (0, IM_REG); |
fe8c2806 WD |
411 | } |
412 | ||
413 | /* | |
414 | . Function: smc_enable | |
415 | . Purpose: let the chip talk to the outside work | |
416 | . Method: | |
417 | . 1. Enable the transmitter | |
418 | . 2. Enable the receiver | |
419 | . 3. Enable interrupts | |
420 | */ | |
421 | static void smc_enable() | |
422 | { | |
f39748ae | 423 | PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); |
fe8c2806 WD |
424 | SMC_SELECT_BANK( 0 ); |
425 | /* see the header file for options in TCR/RCR DEFAULT*/ | |
426 | SMC_outw( TCR_DEFAULT, TCR_REG ); | |
427 | SMC_outw( RCR_DEFAULT, RCR_REG ); | |
428 | ||
429 | /* clear MII_DIS */ | |
430 | /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ | |
431 | } | |
432 | ||
433 | /* | |
434 | . Function: smc_shutdown | |
435 | . Purpose: closes down the SMC91xxx chip. | |
436 | . Method: | |
437 | . 1. zero the interrupt mask | |
438 | . 2. clear the enable receive flag | |
439 | . 3. clear the enable xmit flags | |
440 | . | |
441 | . TODO: | |
442 | . (1) maybe utilize power down mode. | |
443 | . Why not yet? Because while the chip will go into power down mode, | |
444 | . the manual says that it will wake up in response to any I/O requests | |
42dfe7a1 | 445 | . in the register space. Empirical results do not show this working. |
fe8c2806 WD |
446 | */ |
447 | static void smc_shutdown() | |
448 | { | |
f39748ae | 449 | PRINTK2(CARDNAME ": smc_shutdown\n"); |
fe8c2806 WD |
450 | |
451 | /* no more interrupts for me */ | |
452 | SMC_SELECT_BANK( 2 ); | |
453 | SMC_outb( 0, IM_REG ); | |
454 | ||
455 | /* and tell the card to stay away from that nasty outside world */ | |
456 | SMC_SELECT_BANK( 0 ); | |
457 | SMC_outb( RCR_CLEAR, RCR_REG ); | |
458 | SMC_outb( TCR_CLEAR, TCR_REG ); | |
459 | } | |
460 | ||
461 | ||
462 | /* | |
463 | . Function: smc_hardware_send_packet(struct net_device * ) | |
464 | . Purpose: | |
465 | . This sends the actual packet to the SMC9xxx chip. | |
466 | . | |
467 | . Algorithm: | |
42dfe7a1 | 468 | . First, see if a saved_skb is available. |
fe8c2806 WD |
469 | . ( this should NOT be called if there is no 'saved_skb' |
470 | . Now, find the packet number that the chip allocated | |
471 | . Point the data pointers at it in memory | |
472 | . Set the length word in the chip's memory | |
473 | . Dump the packet to chip memory | |
474 | . Check if a last byte is needed ( odd length packet ) | |
475 | . if so, set the control flag right | |
42dfe7a1 | 476 | . Tell the card to send it |
fe8c2806 | 477 | . Enable the transmit interrupt, so I know if it failed |
42dfe7a1 | 478 | . Free the kernel data if I actually sent it. |
fe8c2806 | 479 | */ |
b56ddc63 | 480 | static int smc_send_packet (volatile void *packet, int packet_length) |
fe8c2806 | 481 | { |
b56ddc63 WD |
482 | byte packet_no; |
483 | unsigned long ioaddr; | |
484 | byte *buf; | |
485 | int length; | |
486 | int numPages; | |
487 | int try = 0; | |
488 | int time_out; | |
489 | byte status; | |
518e2e1a WD |
490 | byte saved_pnr; |
491 | word saved_ptr; | |
fe8c2806 | 492 | |
518e2e1a | 493 | /* save PTR and PNR registers before manipulation */ |
b79a11cc | 494 | SMC_SELECT_BANK (2); |
518e2e1a WD |
495 | saved_pnr = SMC_inb( PN_REG ); |
496 | saved_ptr = SMC_inw( PTR_REG ); | |
fe8c2806 | 497 | |
f39748ae | 498 | PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); |
fe8c2806 WD |
499 | |
500 | length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; | |
501 | ||
502 | /* allocate memory | |
b56ddc63 WD |
503 | ** The MMU wants the number of pages to be the number of 256 bytes |
504 | ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) | |
505 | ** | |
506 | ** The 91C111 ignores the size bits, but the code is left intact | |
507 | ** for backwards and future compatibility. | |
508 | ** | |
509 | ** Pkt size for allocating is data length +6 (for additional status | |
510 | ** words, length and ctl!) | |
511 | ** | |
512 | ** If odd size then last byte is included in this header. | |
513 | */ | |
514 | numPages = ((length & 0xfffe) + 6); | |
515 | numPages >>= 8; /* Divide by 256 */ | |
516 | ||
517 | if (numPages > 7) { | |
518 | printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); | |
fe8c2806 WD |
519 | return 0; |
520 | } | |
521 | ||
522 | /* now, try to allocate the memory */ | |
b56ddc63 WD |
523 | SMC_SELECT_BANK (2); |
524 | SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); | |
fe8c2806 | 525 | |
dc7c9a1a | 526 | /* FIXME: the ALLOC_INT bit never gets set * |
42dfe7a1 WD |
527 | * so the following will always give a * |
528 | * memory allocation error. * | |
529 | * same code works in armboot though * | |
dc7c9a1a WD |
530 | * -ro |
531 | */ | |
532 | ||
fe8c2806 WD |
533 | again: |
534 | try++; | |
535 | time_out = MEMORY_WAIT_TIME; | |
536 | do { | |
b56ddc63 WD |
537 | status = SMC_inb (SMC91111_INT_REG); |
538 | if (status & IM_ALLOC_INT) { | |
fe8c2806 | 539 | /* acknowledge the interrupt */ |
b56ddc63 | 540 | SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); |
8bde7f77 | 541 | break; |
fe8c2806 | 542 | } |
b56ddc63 WD |
543 | } while (--time_out); |
544 | ||
545 | if (!time_out) { | |
546 | PRINTK2 ("%s: memory allocation, try %d failed ...\n", | |
547 | SMC_DEV_NAME, try); | |
548 | if (try < SMC_ALLOC_MAX_TRY) | |
549 | goto again; | |
550 | else | |
551 | return 0; | |
fe8c2806 WD |
552 | } |
553 | ||
b56ddc63 WD |
554 | PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", |
555 | SMC_DEV_NAME, try); | |
fe8c2806 WD |
556 | |
557 | /* I can send the packet now.. */ | |
558 | ||
559 | ioaddr = SMC_BASE_ADDRESS; | |
560 | ||
b56ddc63 | 561 | buf = (byte *) packet; |
fe8c2806 WD |
562 | |
563 | /* If I get here, I _know_ there is a packet slot waiting for me */ | |
b56ddc63 WD |
564 | packet_no = SMC_inb (AR_REG); |
565 | if (packet_no & AR_FAILED) { | |
fe8c2806 | 566 | /* or isn't there? BAD CHIP! */ |
b56ddc63 | 567 | printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); |
fe8c2806 WD |
568 | return 0; |
569 | } | |
570 | ||
571 | /* we have a packet address, so tell the card to use it */ | |
b56ddc63 | 572 | SMC_outb (packet_no, PN_REG); |
fe8c2806 | 573 | |
b79a11cc WD |
574 | /* do not write new ptr value if Write data fifo not empty */ |
575 | while ( saved_ptr & PTR_NOTEMPTY ) | |
518e2e1a WD |
576 | printf ("Write data fifo not empty!\n"); |
577 | ||
fe8c2806 | 578 | /* point to the beginning of the packet */ |
b56ddc63 | 579 | SMC_outw (PTR_AUTOINC, PTR_REG); |
fe8c2806 | 580 | |
b56ddc63 WD |
581 | PRINTK3 ("%s: Trying to xmit packet of length %x\n", |
582 | SMC_DEV_NAME, length); | |
fe8c2806 WD |
583 | |
584 | #if SMC_DEBUG > 2 | |
b56ddc63 WD |
585 | printf ("Transmitting Packet\n"); |
586 | print_packet (buf, length); | |
fe8c2806 WD |
587 | #endif |
588 | ||
589 | /* send the packet length ( +6 for status, length and ctl byte ) | |
8bde7f77 | 590 | and the status word ( set to zeros ) */ |
fe8c2806 | 591 | #ifdef USE_32_BIT |
b56ddc63 | 592 | SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); |
fe8c2806 | 593 | #else |
b56ddc63 WD |
594 | SMC_outw (0, SMC91111_DATA_REG); |
595 | /* send the packet length ( +6 for status words, length, and ctl */ | |
596 | SMC_outw ((length + 6), SMC91111_DATA_REG); | |
fe8c2806 WD |
597 | #endif |
598 | ||
599 | /* send the actual data | |
b56ddc63 WD |
600 | . I _think_ it's faster to send the longs first, and then |
601 | . mop up by sending the last word. It depends heavily | |
42dfe7a1 | 602 | . on alignment, at least on the 486. Maybe it would be |
b56ddc63 WD |
603 | . a good idea to check which is optimal? But that could take |
604 | . almost as much time as is saved? | |
605 | */ | |
fe8c2806 | 606 | #ifdef USE_32_BIT |
b56ddc63 WD |
607 | SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); |
608 | if (length & 0x2) | |
609 | SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), | |
610 | SMC91111_DATA_REG); | |
fe8c2806 | 611 | #else |
b56ddc63 | 612 | SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); |
fe8c2806 WD |
613 | #endif /* USE_32_BIT */ |
614 | ||
42dfe7a1 | 615 | /* Send the last byte, if there is one. */ |
b56ddc63 WD |
616 | if ((length & 1) == 0) { |
617 | SMC_outw (0, SMC91111_DATA_REG); | |
fe8c2806 | 618 | } else { |
b56ddc63 | 619 | SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); |
fe8c2806 WD |
620 | } |
621 | ||
622 | /* and let the chipset deal with it */ | |
b56ddc63 | 623 | SMC_outw (MC_ENQUEUE, MMU_CMD_REG); |
fe8c2806 WD |
624 | |
625 | /* poll for TX INT */ | |
518e2e1a WD |
626 | /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ |
627 | /* poll for TX_EMPTY INT - autorelease enabled */ | |
628 | if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { | |
fe8c2806 | 629 | /* sending failed */ |
b56ddc63 | 630 | PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); |
fe8c2806 WD |
631 | |
632 | /* release packet */ | |
518e2e1a WD |
633 | /* no need to release, MMU does that now */ |
634 | /* SMC_outw (MC_FREEPKT, MMU_CMD_REG); */ | |
fe8c2806 | 635 | |
8bde7f77 | 636 | /* wait for MMU getting ready (low) */ |
b56ddc63 WD |
637 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
638 | udelay (10); | |
8bde7f77 | 639 | } |
fe8c2806 | 640 | |
b56ddc63 | 641 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
642 | |
643 | ||
644 | return 0; | |
645 | } else { | |
646 | /* ack. int */ | |
518e2e1a WD |
647 | SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); |
648 | /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ | |
b56ddc63 WD |
649 | PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, |
650 | length); | |
fe8c2806 WD |
651 | |
652 | /* release packet */ | |
518e2e1a WD |
653 | /* no need to release, MMU does that now */ |
654 | /* SMC_outw (MC_FREEPKT, MMU_CMD_REG); */ | |
fe8c2806 | 655 | |
8bde7f77 | 656 | /* wait for MMU getting ready (low) */ |
b56ddc63 WD |
657 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
658 | udelay (10); | |
8bde7f77 | 659 | } |
fe8c2806 | 660 | |
b56ddc63 | 661 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
662 | |
663 | ||
664 | } | |
665 | ||
518e2e1a WD |
666 | /* restore previously saved registers */ |
667 | SMC_outb( saved_pnr, PN_REG ); | |
668 | SMC_outw( saved_ptr, PTR_REG ); | |
669 | ||
fe8c2806 WD |
670 | return length; |
671 | } | |
672 | ||
673 | /*------------------------------------------------------------------------- | |
674 | | | |
675 | | smc_destructor( struct net_device * dev ) | |
676 | | Input parameters: | |
677 | | dev, pointer to the device structure | |
678 | | | |
679 | | Output: | |
680 | | None. | |
681 | | | |
682 | --------------------------------------------------------------------------- | |
683 | */ | |
684 | void smc_destructor() | |
685 | { | |
f39748ae | 686 | PRINTK2(CARDNAME ": smc_destructor\n"); |
fe8c2806 WD |
687 | } |
688 | ||
689 | ||
690 | /* | |
691 | * Open and Initialize the board | |
692 | * | |
693 | * Set up everything, reset the card, etc .. | |
694 | * | |
695 | */ | |
b56ddc63 | 696 | static int smc_open (bd_t * bd) |
fe8c2806 | 697 | { |
b56ddc63 | 698 | int i, err; |
fe8c2806 | 699 | |
f39748ae | 700 | PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); |
fe8c2806 WD |
701 | |
702 | /* reset the hardware */ | |
b56ddc63 WD |
703 | smc_reset (); |
704 | smc_enable (); | |
fe8c2806 WD |
705 | |
706 | /* Configure the PHY */ | |
707 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 708 | smc_phy_configure (); |
fe8c2806 WD |
709 | #endif |
710 | ||
fe8c2806 WD |
711 | /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ |
712 | /* SMC_SELECT_BANK(0); */ | |
713 | /* SMC_outw(0, RPC_REG); */ | |
b56ddc63 | 714 | SMC_SELECT_BANK (1); |
487778b7 | 715 | |
b56ddc63 WD |
716 | err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ |
717 | if (err < 0) { | |
42dfe7a1 | 718 | memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ |
b56ddc63 WD |
719 | return (-1); /* upper code ignores this, but NOT bi_enetaddr */ |
720 | } | |
fe8c2806 | 721 | #ifdef USE_32_BIT |
b56ddc63 | 722 | for (i = 0; i < 6; i += 2) { |
fe8c2806 WD |
723 | word address; |
724 | ||
b56ddc63 WD |
725 | address = smc_mac_addr[i + 1] << 8; |
726 | address |= smc_mac_addr[i]; | |
727 | SMC_outw (address, ADDR0_REG + i); | |
fe8c2806 WD |
728 | } |
729 | #else | |
b56ddc63 WD |
730 | for (i = 0; i < 6; i++) |
731 | SMC_outb (smc_mac_addr[i], ADDR0_REG + i); | |
fe8c2806 WD |
732 | #endif |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
fe8c2806 WD |
737 | /*------------------------------------------------------------- |
738 | . | |
739 | . smc_rcv - receive a packet from the card | |
740 | . | |
741 | . There is ( at least ) a packet waiting to be read from | |
742 | . chip-memory. | |
743 | . | |
744 | . o Read the status | |
745 | . o If an error, record it | |
746 | . o otherwise, read in the packet | |
747 | -------------------------------------------------------------- | |
748 | */ | |
749 | static int smc_rcv() | |
750 | { | |
42dfe7a1 | 751 | int packet_number; |
fe8c2806 WD |
752 | word status; |
753 | word packet_length; | |
42dfe7a1 | 754 | int is_error = 0; |
fe8c2806 WD |
755 | #ifdef USE_32_BIT |
756 | dword stat_len; | |
757 | #endif | |
518e2e1a WD |
758 | byte saved_pnr; |
759 | word saved_ptr; | |
fe8c2806 | 760 | |
fe8c2806 | 761 | SMC_SELECT_BANK(2); |
518e2e1a WD |
762 | /* save PTR and PTR registers */ |
763 | saved_pnr = SMC_inb( PN_REG ); | |
764 | saved_ptr = SMC_inw( PTR_REG ); | |
765 | ||
fe8c2806 WD |
766 | packet_number = SMC_inw( RXFIFO_REG ); |
767 | ||
768 | if ( packet_number & RXFIFO_REMPTY ) { | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
f39748ae | 773 | PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); |
fe8c2806 WD |
774 | /* start reading from the start of the packet */ |
775 | SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); | |
776 | ||
777 | /* First two words are status and packet_length */ | |
778 | #ifdef USE_32_BIT | |
779 | stat_len = SMC_inl(SMC91111_DATA_REG); | |
780 | status = stat_len & 0xffff; | |
781 | packet_length = stat_len >> 16; | |
782 | #else | |
42dfe7a1 WD |
783 | status = SMC_inw( SMC91111_DATA_REG ); |
784 | packet_length = SMC_inw( SMC91111_DATA_REG ); | |
fe8c2806 WD |
785 | #endif |
786 | ||
787 | packet_length &= 0x07ff; /* mask off top bits */ | |
788 | ||
789 | PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); | |
790 | ||
791 | if ( !(status & RS_ERRORS ) ){ | |
792 | /* Adjust for having already read the first two words */ | |
793 | packet_length -= 4; /*4; */ | |
794 | ||
795 | ||
fe8c2806 WD |
796 | /* set odd length for bug in LAN91C111, */ |
797 | /* which never sets RS_ODDFRAME */ | |
798 | /* TODO ? */ | |
799 | ||
800 | ||
801 | #ifdef USE_32_BIT | |
802 | PRINTK3(" Reading %d dwords (and %d bytes) \n", | |
803 | packet_length >> 2, packet_length & 3 ); | |
804 | /* QUESTION: Like in the TX routine, do I want | |
805 | to send the DWORDs or the bytes first, or some | |
806 | mixture. A mixture might improve already slow PIO | |
42dfe7a1 | 807 | performance */ |
fe8c2806 WD |
808 | SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); |
809 | /* read the left over bytes */ | |
810 | if (packet_length & 3) { | |
811 | int i; | |
812 | ||
699b13a6 | 813 | byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); |
fe8c2806 WD |
814 | dword leftover = SMC_inl(SMC91111_DATA_REG); |
815 | for (i=0; i<(packet_length & 3); i++) | |
816 | *tail++ = (byte) (leftover >> (8*i)) & 0xff; | |
817 | } | |
818 | #else | |
819 | PRINTK3(" Reading %d words and %d byte(s) \n", | |
820 | (packet_length >> 1 ), packet_length & 1 ); | |
821 | SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); | |
822 | ||
823 | #endif /* USE_32_BIT */ | |
824 | ||
825 | #if SMC_DEBUG > 2 | |
826 | printf("Receiving Packet\n"); | |
827 | print_packet( NetRxPackets[0], packet_length ); | |
828 | #endif | |
829 | } else { | |
830 | /* error ... */ | |
831 | /* TODO ? */ | |
832 | is_error = 1; | |
833 | } | |
834 | ||
835 | while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) | |
836 | udelay(1); /* Wait until not busy */ | |
837 | ||
838 | /* error or good, tell the card to get rid of this packet */ | |
839 | SMC_outw( MC_RELEASE, MMU_CMD_REG ); | |
840 | ||
841 | while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) | |
842 | udelay(1); /* Wait until not busy */ | |
843 | ||
518e2e1a WD |
844 | /* restore saved registers */ |
845 | SMC_outb( saved_pnr, PN_REG ); | |
846 | SMC_outw( saved_ptr, PTR_REG ); | |
847 | ||
fe8c2806 WD |
848 | if (!is_error) { |
849 | /* Pass the packet up to the protocol layers. */ | |
850 | NetReceive(NetRxPackets[0], packet_length); | |
851 | return packet_length; | |
852 | } else { | |
853 | return 0; | |
854 | } | |
855 | ||
856 | } | |
857 | ||
858 | ||
fe8c2806 WD |
859 | /*---------------------------------------------------- |
860 | . smc_close | |
861 | . | |
862 | . this makes the board clean up everything that it can | |
42dfe7a1 | 863 | . and not talk to the outside world. Caused by |
fe8c2806 WD |
864 | . an 'ifconfig ethX down' |
865 | . | |
866 | -----------------------------------------------------*/ | |
867 | static int smc_close() | |
868 | { | |
f39748ae | 869 | PRINTK2("%s: smc_close\n", SMC_DEV_NAME); |
fe8c2806 WD |
870 | |
871 | /* clear everything */ | |
872 | smc_shutdown(); | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | ||
878 | #if 0 | |
879 | /*------------------------------------------------------------ | |
880 | . Modify a bit in the LAN91C111 register set | |
881 | .-------------------------------------------------------------*/ | |
882 | static word smc_modify_regbit(int bank, int ioaddr, int reg, | |
883 | unsigned int bit, int val) | |
884 | { | |
885 | word regval; | |
886 | ||
887 | SMC_SELECT_BANK( bank ); | |
888 | ||
889 | regval = SMC_inw( reg ); | |
890 | if (val) | |
891 | regval |= bit; | |
892 | else | |
893 | regval &= ~bit; | |
894 | ||
895 | SMC_outw( regval, 0 ); | |
896 | return(regval); | |
897 | } | |
898 | ||
899 | ||
900 | /*------------------------------------------------------------ | |
901 | . Retrieve a bit in the LAN91C111 register set | |
902 | .-------------------------------------------------------------*/ | |
903 | static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) | |
904 | { | |
905 | SMC_SELECT_BANK( bank ); | |
906 | if ( SMC_inw( reg ) & bit) | |
907 | return(1); | |
908 | else | |
909 | return(0); | |
910 | } | |
911 | ||
912 | ||
913 | /*------------------------------------------------------------ | |
914 | . Modify a LAN91C111 register (word access only) | |
915 | .-------------------------------------------------------------*/ | |
916 | static void smc_modify_reg(int bank, int ioaddr, int reg, word val) | |
917 | { | |
918 | SMC_SELECT_BANK( bank ); | |
919 | SMC_outw( val, reg ); | |
920 | } | |
921 | ||
922 | ||
923 | /*------------------------------------------------------------ | |
924 | . Retrieve a LAN91C111 register (word access only) | |
925 | .-------------------------------------------------------------*/ | |
926 | static int smc_get_reg(int bank, int ioaddr, int reg) | |
927 | { | |
928 | SMC_SELECT_BANK( bank ); | |
929 | return(SMC_inw( reg )); | |
930 | } | |
931 | ||
932 | #endif /* 0 */ | |
933 | ||
934 | /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ | |
935 | ||
936 | #if (SMC_DEBUG > 2 ) | |
937 | ||
938 | /*------------------------------------------------------------ | |
939 | . Debugging function for viewing MII Management serial bitstream | |
940 | .-------------------------------------------------------------*/ | |
b56ddc63 | 941 | static void smc_dump_mii_stream (byte * bits, int size) |
fe8c2806 WD |
942 | { |
943 | int i; | |
944 | ||
b56ddc63 WD |
945 | printf ("BIT#:"); |
946 | for (i = 0; i < size; ++i) { | |
947 | printf ("%d", i % 10); | |
948 | } | |
fe8c2806 | 949 | |
b56ddc63 WD |
950 | printf ("\nMDOE:"); |
951 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 952 | if (bits[i] & MII_MDOE) |
b56ddc63 | 953 | printf ("1"); |
fe8c2806 | 954 | else |
b56ddc63 WD |
955 | printf ("0"); |
956 | } | |
fe8c2806 | 957 | |
b56ddc63 WD |
958 | printf ("\nMDO :"); |
959 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 960 | if (bits[i] & MII_MDO) |
b56ddc63 | 961 | printf ("1"); |
fe8c2806 | 962 | else |
b56ddc63 WD |
963 | printf ("0"); |
964 | } | |
fe8c2806 | 965 | |
b56ddc63 WD |
966 | printf ("\nMDI :"); |
967 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 968 | if (bits[i] & MII_MDI) |
b56ddc63 | 969 | printf ("1"); |
fe8c2806 | 970 | else |
b56ddc63 WD |
971 | printf ("0"); |
972 | } | |
fe8c2806 | 973 | |
b56ddc63 | 974 | printf ("\n"); |
fe8c2806 WD |
975 | } |
976 | #endif | |
977 | ||
978 | /*------------------------------------------------------------ | |
979 | . Reads a register from the MII Management serial interface | |
980 | .-------------------------------------------------------------*/ | |
981 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 982 | static word smc_read_phy_register (byte phyreg) |
fe8c2806 WD |
983 | { |
984 | int oldBank; | |
985 | int i; | |
986 | byte mask; | |
987 | word mii_reg; | |
988 | byte bits[64]; | |
989 | int clk_idx = 0; | |
990 | int input_idx; | |
991 | word phydata; | |
992 | byte phyaddr = SMC_PHY_ADDR; | |
993 | ||
994 | /* 32 consecutive ones on MDO to establish sync */ | |
995 | for (i = 0; i < 32; ++i) | |
996 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
997 | ||
998 | /* Start code <01> */ | |
999 | bits[clk_idx++] = MII_MDOE; | |
1000 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1001 | ||
1002 | /* Read command <10> */ | |
1003 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1004 | bits[clk_idx++] = MII_MDOE; | |
1005 | ||
1006 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1007 | mask = (byte) 0x10; |
1008 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1009 | if (phyaddr & mask) |
1010 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1011 | else | |
1012 | bits[clk_idx++] = MII_MDOE; | |
1013 | ||
1014 | /* Shift to next lowest bit */ | |
1015 | mask >>= 1; | |
b56ddc63 | 1016 | } |
fe8c2806 WD |
1017 | |
1018 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1019 | mask = (byte) 0x10; |
1020 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1021 | if (phyreg & mask) |
1022 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1023 | else | |
1024 | bits[clk_idx++] = MII_MDOE; | |
1025 | ||
1026 | /* Shift to next lowest bit */ | |
1027 | mask >>= 1; | |
b56ddc63 | 1028 | } |
fe8c2806 WD |
1029 | |
1030 | /* Tristate and turnaround (2 bit times) */ | |
1031 | bits[clk_idx++] = 0; | |
1032 | /*bits[clk_idx++] = 0; */ | |
1033 | ||
1034 | /* Input starts at this bit time */ | |
1035 | input_idx = clk_idx; | |
1036 | ||
1037 | /* Will input 16 bits */ | |
1038 | for (i = 0; i < 16; ++i) | |
1039 | bits[clk_idx++] = 0; | |
1040 | ||
1041 | /* Final clock bit */ | |
1042 | bits[clk_idx++] = 0; | |
1043 | ||
1044 | /* Save the current bank */ | |
b56ddc63 | 1045 | oldBank = SMC_inw (BANK_SELECT); |
fe8c2806 WD |
1046 | |
1047 | /* Select bank 3 */ | |
b56ddc63 | 1048 | SMC_SELECT_BANK (3); |
fe8c2806 WD |
1049 | |
1050 | /* Get the current MII register value */ | |
b56ddc63 | 1051 | mii_reg = SMC_inw (MII_REG); |
fe8c2806 WD |
1052 | |
1053 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1054 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1055 | |
1056 | /* Clock all 64 cycles */ | |
b56ddc63 | 1057 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1058 | /* Clock Low - output data */ |
b56ddc63 WD |
1059 | SMC_outw (mii_reg | bits[i], MII_REG); |
1060 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1061 | |
1062 | ||
1063 | /* Clock Hi - input data */ | |
b56ddc63 WD |
1064 | SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); |
1065 | udelay (SMC_PHY_CLOCK_DELAY); | |
1066 | bits[i] |= SMC_inw (MII_REG) & MII_MDI; | |
1067 | } | |
fe8c2806 WD |
1068 | |
1069 | /* Return to idle state */ | |
1070 | /* Set clock to low, data to low, and output tristated */ | |
b56ddc63 WD |
1071 | SMC_outw (mii_reg, MII_REG); |
1072 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1073 | |
1074 | /* Restore original bank select */ | |
b56ddc63 | 1075 | SMC_SELECT_BANK (oldBank); |
fe8c2806 WD |
1076 | |
1077 | /* Recover input data */ | |
1078 | phydata = 0; | |
b56ddc63 | 1079 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1080 | phydata <<= 1; |
1081 | ||
1082 | if (bits[input_idx++] & MII_MDI) | |
1083 | phydata |= 0x0001; | |
b56ddc63 | 1084 | } |
fe8c2806 WD |
1085 | |
1086 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1087 | printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1088 | phyaddr, phyreg, phydata); |
b56ddc63 | 1089 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1090 | #endif |
1091 | ||
b56ddc63 | 1092 | return (phydata); |
fe8c2806 WD |
1093 | } |
1094 | ||
1095 | ||
1096 | /*------------------------------------------------------------ | |
1097 | . Writes a register to the MII Management serial interface | |
1098 | .-------------------------------------------------------------*/ | |
b56ddc63 | 1099 | static void smc_write_phy_register (byte phyreg, word phydata) |
fe8c2806 WD |
1100 | { |
1101 | int oldBank; | |
1102 | int i; | |
1103 | word mask; | |
1104 | word mii_reg; | |
1105 | byte bits[65]; | |
1106 | int clk_idx = 0; | |
1107 | byte phyaddr = SMC_PHY_ADDR; | |
1108 | ||
1109 | /* 32 consecutive ones on MDO to establish sync */ | |
1110 | for (i = 0; i < 32; ++i) | |
1111 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1112 | ||
1113 | /* Start code <01> */ | |
1114 | bits[clk_idx++] = MII_MDOE; | |
1115 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1116 | ||
1117 | /* Write command <01> */ | |
1118 | bits[clk_idx++] = MII_MDOE; | |
1119 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1120 | ||
1121 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1122 | mask = (byte) 0x10; |
1123 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1124 | if (phyaddr & mask) |
1125 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1126 | else | |
1127 | bits[clk_idx++] = MII_MDOE; | |
1128 | ||
1129 | /* Shift to next lowest bit */ | |
1130 | mask >>= 1; | |
b56ddc63 | 1131 | } |
fe8c2806 WD |
1132 | |
1133 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1134 | mask = (byte) 0x10; |
1135 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1136 | if (phyreg & mask) |
1137 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1138 | else | |
1139 | bits[clk_idx++] = MII_MDOE; | |
1140 | ||
1141 | /* Shift to next lowest bit */ | |
1142 | mask >>= 1; | |
b56ddc63 | 1143 | } |
fe8c2806 WD |
1144 | |
1145 | /* Tristate and turnaround (2 bit times) */ | |
1146 | bits[clk_idx++] = 0; | |
1147 | bits[clk_idx++] = 0; | |
1148 | ||
1149 | /* Write out 16 bits of data, msb first */ | |
1150 | mask = 0x8000; | |
b56ddc63 | 1151 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1152 | if (phydata & mask) |
1153 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1154 | else | |
1155 | bits[clk_idx++] = MII_MDOE; | |
1156 | ||
1157 | /* Shift to next lowest bit */ | |
1158 | mask >>= 1; | |
b56ddc63 | 1159 | } |
fe8c2806 WD |
1160 | |
1161 | /* Final clock bit (tristate) */ | |
1162 | bits[clk_idx++] = 0; | |
1163 | ||
1164 | /* Save the current bank */ | |
b56ddc63 | 1165 | oldBank = SMC_inw (BANK_SELECT); |
fe8c2806 WD |
1166 | |
1167 | /* Select bank 3 */ | |
b56ddc63 | 1168 | SMC_SELECT_BANK (3); |
fe8c2806 WD |
1169 | |
1170 | /* Get the current MII register value */ | |
b56ddc63 | 1171 | mii_reg = SMC_inw (MII_REG); |
fe8c2806 WD |
1172 | |
1173 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1174 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1175 | |
1176 | /* Clock all cycles */ | |
b56ddc63 | 1177 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1178 | /* Clock Low - output data */ |
b56ddc63 WD |
1179 | SMC_outw (mii_reg | bits[i], MII_REG); |
1180 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1181 | |
1182 | ||
1183 | /* Clock Hi - input data */ | |
b56ddc63 WD |
1184 | SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); |
1185 | udelay (SMC_PHY_CLOCK_DELAY); | |
1186 | bits[i] |= SMC_inw (MII_REG) & MII_MDI; | |
1187 | } | |
fe8c2806 WD |
1188 | |
1189 | /* Return to idle state */ | |
1190 | /* Set clock to low, data to low, and output tristated */ | |
b56ddc63 WD |
1191 | SMC_outw (mii_reg, MII_REG); |
1192 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1193 | |
1194 | /* Restore original bank select */ | |
b56ddc63 | 1195 | SMC_SELECT_BANK (oldBank); |
fe8c2806 WD |
1196 | |
1197 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1198 | printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1199 | phyaddr, phyreg, phydata); |
b56ddc63 | 1200 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1201 | #endif |
1202 | } | |
1203 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1204 | ||
1205 | ||
fe8c2806 WD |
1206 | /*------------------------------------------------------------ |
1207 | . Waits the specified number of milliseconds - kernel friendly | |
1208 | .-------------------------------------------------------------*/ | |
1209 | #ifndef CONFIG_SMC91111_EXT_PHY | |
1210 | static void smc_wait_ms(unsigned int ms) | |
1211 | { | |
1212 | udelay(ms*1000); | |
1213 | } | |
1214 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1215 | ||
1216 | ||
fe8c2806 WD |
1217 | /*------------------------------------------------------------ |
1218 | . Configures the specified PHY using Autonegotiation. Calls | |
1219 | . smc_phy_fixed() if the user has requested a certain config. | |
1220 | .-------------------------------------------------------------*/ | |
1221 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 1222 | static void smc_phy_configure () |
fe8c2806 WD |
1223 | { |
1224 | int timeout; | |
1225 | byte phyaddr; | |
b56ddc63 WD |
1226 | word my_phy_caps; /* My PHY capabilities */ |
1227 | word my_ad_caps; /* My Advertised capabilities */ | |
1228 | word status = 0; /*;my status = 0 */ | |
fe8c2806 WD |
1229 | int failed = 0; |
1230 | ||
f39748ae | 1231 | PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); |
fe8c2806 WD |
1232 | |
1233 | ||
fe8c2806 WD |
1234 | /* Get the detected phy address */ |
1235 | phyaddr = SMC_PHY_ADDR; | |
1236 | ||
1237 | /* Reset the PHY, setting all other bits to zero */ | |
b56ddc63 | 1238 | smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); |
fe8c2806 WD |
1239 | |
1240 | /* Wait for the reset to complete, or time out */ | |
b56ddc63 WD |
1241 | timeout = 6; /* Wait up to 3 seconds */ |
1242 | while (timeout--) { | |
1243 | if (!(smc_read_phy_register (PHY_CNTL_REG) | |
1244 | & PHY_CNTL_RST)) { | |
fe8c2806 WD |
1245 | /* reset complete */ |
1246 | break; | |
fe8c2806 WD |
1247 | } |
1248 | ||
b56ddc63 WD |
1249 | smc_wait_ms (500); /* wait 500 millisecs */ |
1250 | } | |
1251 | ||
1252 | if (timeout < 1) { | |
1253 | printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); | |
fe8c2806 | 1254 | goto smc_phy_configure_exit; |
b56ddc63 | 1255 | } |
fe8c2806 WD |
1256 | |
1257 | /* Read PHY Register 18, Status Output */ | |
1258 | /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ | |
1259 | ||
1260 | /* Enable PHY Interrupts (for register 18) */ | |
1261 | /* Interrupts listed here are disabled */ | |
8bf3b005 | 1262 | smc_write_phy_register (PHY_MASK_REG, 0xffff); |
fe8c2806 WD |
1263 | |
1264 | /* Configure the Receive/Phy Control register */ | |
b56ddc63 WD |
1265 | SMC_SELECT_BANK (0); |
1266 | SMC_outw (RPC_DEFAULT, RPC_REG); | |
fe8c2806 WD |
1267 | |
1268 | /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ | |
b56ddc63 WD |
1269 | my_phy_caps = smc_read_phy_register (PHY_STAT_REG); |
1270 | my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ | |
fe8c2806 WD |
1271 | |
1272 | if (my_phy_caps & PHY_STAT_CAP_T4) | |
1273 | my_ad_caps |= PHY_AD_T4; | |
1274 | ||
1275 | if (my_phy_caps & PHY_STAT_CAP_TXF) | |
1276 | my_ad_caps |= PHY_AD_TX_FDX; | |
1277 | ||
1278 | if (my_phy_caps & PHY_STAT_CAP_TXH) | |
1279 | my_ad_caps |= PHY_AD_TX_HDX; | |
1280 | ||
1281 | if (my_phy_caps & PHY_STAT_CAP_TF) | |
1282 | my_ad_caps |= PHY_AD_10_FDX; | |
1283 | ||
1284 | if (my_phy_caps & PHY_STAT_CAP_TH) | |
1285 | my_ad_caps |= PHY_AD_10_HDX; | |
1286 | ||
1287 | /* Update our Auto-Neg Advertisement Register */ | |
b56ddc63 | 1288 | smc_write_phy_register (PHY_AD_REG, my_ad_caps); |
fe8c2806 | 1289 | |
518e2e1a WD |
1290 | /* Read the register back. Without this, it appears that when */ |
1291 | /* auto-negotiation is restarted, sometimes it isn't ready and */ | |
1292 | /* the link does not come up. */ | |
1293 | smc_read_phy_register(PHY_AD_REG); | |
1294 | ||
f39748ae WD |
1295 | PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); |
1296 | PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); | |
fe8c2806 WD |
1297 | |
1298 | /* Restart auto-negotiation process in order to advertise my caps */ | |
b56ddc63 WD |
1299 | smc_write_phy_register (PHY_CNTL_REG, |
1300 | PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); | |
fe8c2806 WD |
1301 | |
1302 | /* Wait for the auto-negotiation to complete. This may take from */ | |
1303 | /* 2 to 3 seconds. */ | |
1304 | /* Wait for the reset to complete, or time out */ | |
f39748ae | 1305 | timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; |
b56ddc63 | 1306 | while (timeout--) { |
f39748ae | 1307 | |
b56ddc63 WD |
1308 | status = smc_read_phy_register (PHY_STAT_REG); |
1309 | if (status & PHY_STAT_ANEG_ACK) { | |
fe8c2806 WD |
1310 | /* auto-negotiate complete */ |
1311 | break; | |
b56ddc63 | 1312 | } |
fe8c2806 | 1313 | |
b56ddc63 | 1314 | smc_wait_ms (500); /* wait 500 millisecs */ |
fe8c2806 WD |
1315 | |
1316 | /* Restart auto-negotiation if remote fault */ | |
b56ddc63 | 1317 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1318 | printf ("%s: PHY remote fault detected\n", |
b56ddc63 | 1319 | SMC_DEV_NAME); |
fe8c2806 WD |
1320 | |
1321 | /* Restart auto-negotiation */ | |
f39748ae | 1322 | printf ("%s: PHY restarting auto-negotiation\n", |
fe8c2806 | 1323 | SMC_DEV_NAME); |
b56ddc63 WD |
1324 | smc_write_phy_register (PHY_CNTL_REG, |
1325 | PHY_CNTL_ANEG_EN | | |
1326 | PHY_CNTL_ANEG_RST | | |
1327 | PHY_CNTL_SPEED | | |
1328 | PHY_CNTL_DPLX); | |
fe8c2806 | 1329 | } |
b56ddc63 | 1330 | } |
fe8c2806 | 1331 | |
b56ddc63 | 1332 | if (timeout < 1) { |
f39748ae | 1333 | printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); |
fe8c2806 | 1334 | failed = 1; |
b56ddc63 | 1335 | } |
fe8c2806 WD |
1336 | |
1337 | /* Fail if we detected an auto-negotiate remote fault */ | |
b56ddc63 | 1338 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1339 | printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); |
fe8c2806 | 1340 | failed = 1; |
b56ddc63 | 1341 | } |
fe8c2806 WD |
1342 | |
1343 | /* Re-Configure the Receive/Phy Control register */ | |
b56ddc63 | 1344 | SMC_outw (RPC_DEFAULT, RPC_REG); |
fe8c2806 | 1345 | |
b56ddc63 | 1346 | smc_phy_configure_exit: |
fe8c2806 WD |
1347 | |
1348 | } | |
1349 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1350 | ||
1351 | ||
1352 | #if SMC_DEBUG > 2 | |
1353 | static void print_packet( byte * buf, int length ) | |
1354 | { | |
8bde7f77 WD |
1355 | int i; |
1356 | int remainder; | |
1357 | int lines; | |
fe8c2806 | 1358 | |
8bde7f77 | 1359 | printf("Packet of length %d \n", length ); |
fe8c2806 WD |
1360 | |
1361 | #if SMC_DEBUG > 3 | |
8bde7f77 WD |
1362 | lines = length / 16; |
1363 | remainder = length % 16; | |
1364 | ||
1365 | for ( i = 0; i < lines ; i ++ ) { | |
1366 | int cur; | |
1367 | ||
1368 | for ( cur = 0; cur < 8; cur ++ ) { | |
1369 | byte a, b; | |
1370 | ||
1371 | a = *(buf ++ ); | |
1372 | b = *(buf ++ ); | |
1373 | printf("%02x%02x ", a, b ); | |
1374 | } | |
1375 | printf("\n"); | |
1376 | } | |
1377 | for ( i = 0; i < remainder/2 ; i++ ) { | |
1378 | byte a, b; | |
1379 | ||
1380 | a = *(buf ++ ); | |
1381 | b = *(buf ++ ); | |
1382 | printf("%02x%02x ", a, b ); | |
1383 | } | |
1384 | printf("\n"); | |
fe8c2806 | 1385 | #endif |
fe8c2806 WD |
1386 | } |
1387 | #endif | |
1388 | ||
1389 | int eth_init(bd_t *bd) { | |
0b97ab14 | 1390 | return (smc_open(bd)); |
fe8c2806 WD |
1391 | } |
1392 | ||
1393 | void eth_halt() { | |
1394 | smc_close(); | |
1395 | } | |
1396 | ||
1397 | int eth_rx() { | |
1398 | return smc_rcv(); | |
1399 | } | |
1400 | ||
1401 | int eth_send(volatile void *packet, int length) { | |
1402 | return smc_send_packet(packet, length); | |
1403 | } | |
1404 | ||
b56ddc63 | 1405 | int smc_get_ethaddr (bd_t * bd) |
0b97ab14 | 1406 | { |
b56ddc63 WD |
1407 | int env_size, rom_valid, env_present = 0, reg; |
1408 | char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; | |
1409 | uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6]; | |
1410 | ||
1411 | env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); | |
1412 | if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ | |
1413 | printf ("\n*** ERROR: ethaddr is not set properly!!\n"); | |
1414 | return (-1); | |
1415 | } | |
1416 | ||
1417 | if (env_size > 0) { | |
1418 | env_present = 1; | |
1419 | s = s_env_mac; | |
8bde7f77 | 1420 | } |
8bde7f77 | 1421 | |
42dfe7a1 | 1422 | for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ |
b56ddc63 WD |
1423 | v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; |
1424 | if (s) | |
1425 | s = (*e) ? e + 1 : e; | |
8bde7f77 | 1426 | } |
b56ddc63 WD |
1427 | |
1428 | rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ | |
1429 | ||
1430 | if (!env_present) { /* if NO env */ | |
1431 | if (rom_valid) { /* but ROM is valid */ | |
1432 | v_mac = v_rom_mac; | |
1433 | sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", | |
1434 | v_mac[0], v_mac[1], v_mac[2], v_mac[3], | |
1435 | v_mac[4], v_mac[5]); | |
1436 | setenv ("ethaddr", s_env_mac); | |
1437 | } else { /* no env, bad ROM */ | |
1438 | printf ("\n*** ERROR: ethaddr is NOT set !!\n"); | |
1439 | return (-1); | |
1440 | } | |
1441 | } else { /* good env, don't care ROM */ | |
1442 | v_mac = v_env_mac; /* always use a good env over a ROM */ | |
1443 | } | |
1444 | ||
42dfe7a1 | 1445 | if (env_present && rom_valid) { /* if both env and ROM are good */ |
b56ddc63 | 1446 | if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { |
b56ddc63 WD |
1447 | printf ("\nWarning: MAC addresses don't match:\n"); |
1448 | printf ("\tHW MAC address: " | |
1449 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
1450 | v_rom_mac[0], v_rom_mac[1], | |
1451 | v_rom_mac[2], v_rom_mac[3], | |
1452 | v_rom_mac[4], v_rom_mac[5] ); | |
1453 | printf ("\t\"ethaddr\" value: " | |
1454 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
1455 | v_env_mac[0], v_env_mac[1], | |
1456 | v_env_mac[2], v_env_mac[3], | |
1457 | v_env_mac[4], v_env_mac[5]) ; | |
1458 | debug ("### Set MAC addr from environment\n"); | |
b56ddc63 WD |
1459 | } |
1460 | } | |
1461 | memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ | |
1462 | smc_set_mac_addr (v_mac); /* use old function to update smc default */ | |
3d3befa7 | 1463 | PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], |
42dfe7a1 | 1464 | v_mac[2], v_mac[3], v_mac[4], v_mac[5]); |
b56ddc63 | 1465 | return (0); |
0b97ab14 WD |
1466 | } |
1467 | ||
b56ddc63 | 1468 | int get_rom_mac (char *v_rom_mac) |
0b97ab14 | 1469 | { |
b56ddc63 WD |
1470 | #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ |
1471 | char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; | |
0b97ab14 | 1472 | |
b56ddc63 WD |
1473 | memcpy (v_rom_mac, hw_mac_addr, 6); |
1474 | return (1); | |
0b97ab14 | 1475 | #else |
3d3befa7 | 1476 | int i; |
f39748ae WD |
1477 | int valid_mac = 0; |
1478 | ||
3d3befa7 WD |
1479 | SMC_SELECT_BANK (1); |
1480 | for (i=0; i<6; i++) | |
1481 | { | |
1482 | v_rom_mac[i] = SMC_inb (ADDR0_REG + i); | |
f39748ae | 1483 | valid_mac |= v_rom_mac[i]; |
b56ddc63 | 1484 | } |
f39748ae WD |
1485 | |
1486 | return (valid_mac ? 1 : 0); | |
0b97ab14 WD |
1487 | #endif |
1488 | } | |
fe8c2806 | 1489 | #endif /* CONFIG_DRIVER_SMC91111 */ |