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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.h - macros for the LAN91C111 Ethernet Driver | |
3 | . | |
4 | . (C) Copyright 2002 | |
5 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | . Rolf Offermanns <rof@sysgo.de> | |
7 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
8 | . Developed by Simple Network Magic Corporation (SNMC) | |
9 | . Copyright (C) 1996 by Erik Stahlman (ES) | |
10 | . | |
11 | . This program is free software; you can redistribute it and/or modify | |
12 | . it under the terms of the GNU General Public License as published by | |
13 | . the Free Software Foundation; either version 2 of the License, or | |
14 | . (at your option) any later version. | |
15 | . | |
16 | . This program is distributed in the hope that it will be useful, | |
17 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | . GNU General Public License for more details. | |
20 | . | |
21 | . You should have received a copy of the GNU General Public License | |
22 | . along with this program; if not, write to the Free Software | |
23 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | . | |
25 | . This file contains register information and access macros for | |
26 | . the LAN91C111 single chip ethernet controller. It is a modified | |
27 | . version of the smc9194.h file. | |
28 | . | |
29 | . Information contained in this file was obtained from the LAN91C111 | |
30 | . manual from SMC. To get a copy, if you really want one, you can find | |
31 | . information under www.smsc.com. | |
32 | . | |
33 | . Authors | |
34 | . Erik Stahlman ( erik@vt.edu ) | |
35 | . Daris A Nevil ( dnevil@snmc.com ) | |
36 | . | |
37 | . History | |
38 | . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device | |
39 | . | |
40 | ---------------------------------------------------------------------------*/ | |
41 | #ifndef _SMC91111_H_ | |
42 | #define _SMC91111_H_ | |
43 | ||
44 | #include <asm/types.h> | |
45 | #include <config.h> | |
46 | ||
47 | /* | |
48 | * This function may be called by the board specific initialisation code | |
49 | * in order to override the default mac address. | |
50 | */ | |
51 | ||
52 | void smc_set_mac_addr(const char *addr); | |
53 | ||
54 | ||
55 | /* I want some simple types */ | |
56 | ||
57 | typedef unsigned char byte; | |
58 | typedef unsigned short word; | |
59 | typedef unsigned long int dword; | |
60 | ||
61 | /* | |
62 | . DEBUGGING LEVELS | |
63 | . | |
64 | . 0 for normal operation | |
65 | . 1 for slightly more details | |
66 | . >2 for various levels of increasingly useless information | |
67 | . 2 for interrupt tracking, status flags | |
68 | . 3 for packet info | |
69 | . 4 for complete packet dumps | |
70 | */ | |
71 | /*#define SMC_DEBUG 0 */ | |
72 | ||
73 | /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ | |
74 | ||
75 | #define SMC_IO_EXTENT 16 | |
76 | ||
77 | #ifdef CONFIG_PXA250 | |
78 | ||
79 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) | |
80 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) | |
81 | #define SMC_inb(p) ({ \ | |
82 | unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ | |
487778b7 | 83 | unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ |
fe8c2806 WD |
84 | if (__p & 1) __v >>= 8; \ |
85 | else __v &= 0xff; \ | |
86 | __v; }) | |
87 | ||
88 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) | |
89 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) | |
90 | #define SMC_outb(d,r) ({ word __d = (byte)(d); \ | |
91 | word __w = SMC_inw((r)&~1); \ | |
92 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ | |
93 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
94 | SMC_outw(__w,(r)&~1); \ | |
95 | }) | |
96 | ||
97 | #define SMC_outsl(r,b,l) ({ int __i; \ | |
98 | dword *__b2; \ | |
99 | __b2 = (dword *) b; \ | |
100 | for (__i = 0; __i < l; __i++) { \ | |
101 | SMC_outl( *(__b2 + __i), r); \ | |
102 | } \ | |
103 | }) | |
104 | ||
105 | #define SMC_outsw(r,b,l) ({ int __i; \ | |
106 | word *__b2; \ | |
107 | __b2 = (word *) b; \ | |
108 | for (__i = 0; __i < l; __i++) { \ | |
109 | SMC_outw( *(__b2 + __i), r); \ | |
110 | } \ | |
111 | }) | |
112 | ||
113 | #define SMC_insl(r,b,l) ({ int __i ; \ | |
114 | dword *__b2; \ | |
115 | __b2 = (dword *) b; \ | |
116 | for (__i = 0; __i < l; __i++) { \ | |
117 | *(__b2 + __i) = SMC_inl(r); \ | |
118 | SMC_inl(0); \ | |
119 | }; \ | |
120 | }) | |
121 | ||
122 | #define SMC_insw(r,b,l) ({ int __i ; \ | |
123 | word *__b2; \ | |
124 | __b2 = (word *) b; \ | |
125 | for (__i = 0; __i < l; __i++) { \ | |
126 | *(__b2 + __i) = SMC_inw(r); \ | |
127 | SMC_inw(0); \ | |
128 | }; \ | |
129 | }) | |
130 | ||
131 | #define SMC_insb(r,b,l) ({ int __i ; \ | |
132 | byte *__b2; \ | |
133 | __b2 = (byte *) b; \ | |
134 | for (__i = 0; __i < l; __i++) { \ | |
135 | *(__b2 + __i) = SMC_inb(r); \ | |
136 | SMC_inb(0); \ | |
137 | }; \ | |
138 | }) | |
139 | ||
140 | #else /* if not CONFIG_PXA250 */ | |
141 | ||
142 | /* | |
143 | * We have only 16 Bit PCMCIA access on Socket 0 | |
144 | */ | |
145 | ||
aaf224ab WD |
146 | #ifdef CONFIG_ADNPESC1 |
147 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) | |
148 | #else | |
fe8c2806 | 149 | #define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) |
aaf224ab | 150 | #endif |
fe8c2806 WD |
151 | #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) |
152 | ||
aaf224ab WD |
153 | #ifdef CONFIG_ADNPESC1 |
154 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) | |
155 | #else | |
fe8c2806 | 156 | #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) |
aaf224ab | 157 | #endif |
fe8c2806 WD |
158 | #define SMC_outb(d,r) ({ word __d = (byte)(d); \ |
159 | word __w = SMC_inw((r)&~1); \ | |
160 | __w &= ((r)&1) ? 0x00FF : 0xFF00; \ | |
161 | __w |= ((r)&1) ? __d<<8 : __d; \ | |
162 | SMC_outw(__w,(r)&~1); \ | |
163 | }) | |
164 | #if 0 | |
165 | #define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) | |
166 | #else | |
167 | #define SMC_outsw(r,b,l) ({ int __i; \ | |
168 | word *__b2; \ | |
169 | __b2 = (word *) b; \ | |
170 | for (__i = 0; __i < l; __i++) { \ | |
171 | SMC_outw( *(__b2 + __i), r); \ | |
172 | } \ | |
173 | }) | |
174 | #endif | |
175 | ||
176 | #if 0 | |
177 | #define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) | |
178 | #else | |
179 | #define SMC_insw(r,b,l) ({ int __i ; \ | |
180 | word *__b2; \ | |
181 | __b2 = (word *) b; \ | |
182 | for (__i = 0; __i < l; __i++) { \ | |
183 | *(__b2 + __i) = SMC_inw(r); \ | |
184 | SMC_inw(0); \ | |
185 | }; \ | |
186 | }) | |
187 | #endif | |
188 | ||
a3ad8e26 WD |
189 | #if defined(CONFIG_SMC_USE_32_BIT) |
190 | ||
191 | #define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) | |
192 | ||
193 | #define SMC_insl(r,b,l) ({ int __i ; \ | |
194 | dword *__b2; \ | |
195 | __b2 = (dword *) b; \ | |
196 | for (__i = 0; __i < l; __i++) { \ | |
197 | *(__b2 + __i) = SMC_inl(r); \ | |
198 | SMC_inl(0); \ | |
199 | }; \ | |
200 | }) | |
201 | ||
202 | #define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) | |
203 | ||
204 | #define SMC_outsl(r,b,l) ({ int __i; \ | |
205 | dword *__b2; \ | |
206 | __b2 = (dword *) b; \ | |
207 | for (__i = 0; __i < l; __i++) { \ | |
208 | SMC_outl( *(__b2 + __i), r); \ | |
209 | } \ | |
210 | }) | |
211 | ||
212 | #endif /* CONFIG_SMC_USE_32_BIT */ | |
213 | ||
fe8c2806 WD |
214 | #endif |
215 | ||
216 | /*--------------------------------------------------------------- | |
217 | . | |
218 | . A description of the SMSC registers is probably in order here, | |
219 | . although for details, the SMC datasheet is invaluable. | |
220 | . | |
221 | . Basically, the chip has 4 banks of registers ( 0 to 3 ), which | |
222 | . are accessed by writing a number into the BANK_SELECT register | |
223 | . ( I also use a SMC_SELECT_BANK macro for this ). | |
224 | . | |
225 | . The banks are configured so that for most purposes, bank 2 is all | |
226 | . that is needed for simple run time tasks. | |
227 | -----------------------------------------------------------------------*/ | |
228 | ||
229 | /* | |
230 | . Bank Select Register: | |
231 | . | |
232 | . yyyy yyyy 0000 00xx | |
233 | . xx = bank number | |
234 | . yyyy yyyy = 0x33, for identification purposes. | |
235 | */ | |
236 | #define BANK_SELECT 14 | |
237 | ||
238 | /* Transmit Control Register */ | |
239 | /* BANK 0 */ | |
240 | #define TCR_REG 0x0000 /* transmit control register */ | |
241 | #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ | |
242 | #define TCR_LOOP 0x0002 /* Controls output pin LBK */ | |
243 | #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ | |
244 | #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ | |
245 | #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ | |
246 | #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ | |
247 | #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ | |
248 | #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ | |
249 | #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ | |
250 | #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ | |
251 | ||
252 | #define TCR_CLEAR 0 /* do NOTHING */ | |
253 | /* the default settings for the TCR register : */ | |
254 | /* QUESTION: do I want to enable padding of short packets ? */ | |
255 | #define TCR_DEFAULT TCR_ENABLE | |
256 | ||
257 | ||
258 | /* EPH Status Register */ | |
259 | /* BANK 0 */ | |
260 | #define EPH_STATUS_REG 0x0002 | |
261 | #define ES_TX_SUC 0x0001 /* Last TX was successful */ | |
262 | #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ | |
263 | #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ | |
264 | #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ | |
265 | #define ES_16COL 0x0010 /* 16 Collisions Reached */ | |
266 | #define ES_SQET 0x0020 /* Signal Quality Error Test */ | |
267 | #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ | |
268 | #define ES_TXDEFR 0x0080 /* Transmit Deferred */ | |
269 | #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ | |
270 | #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ | |
271 | #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ | |
272 | #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ | |
273 | #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ | |
274 | #define ES_TXUNRN 0x8000 /* Tx Underrun */ | |
275 | ||
276 | ||
277 | /* Receive Control Register */ | |
278 | /* BANK 0 */ | |
279 | #define RCR_REG 0x0004 | |
280 | #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ | |
281 | #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ | |
282 | #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ | |
283 | #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ | |
284 | #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ | |
285 | #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ | |
286 | #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ | |
287 | #define RCR_SOFTRST 0x8000 /* resets the chip */ | |
288 | ||
289 | /* the normal settings for the RCR register : */ | |
290 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
291 | #define RCR_CLEAR 0x0 /* set it to a base state */ | |
292 | ||
293 | /* Counter Register */ | |
294 | /* BANK 0 */ | |
295 | #define COUNTER_REG 0x0006 | |
296 | ||
297 | /* Memory Information Register */ | |
298 | /* BANK 0 */ | |
299 | #define MIR_REG 0x0008 | |
300 | ||
301 | /* Receive/Phy Control Register */ | |
302 | /* BANK 0 */ | |
303 | #define RPC_REG 0x000A | |
304 | #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ | |
305 | #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ | |
306 | #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ | |
307 | #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ | |
308 | #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ | |
309 | #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ | |
310 | #define RPC_LED_RES (0x01) /* LED = Reserved */ | |
311 | #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ | |
312 | #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ | |
313 | #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ | |
314 | #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ | |
315 | #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ | |
316 | #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ | |
c935d3bd | 317 | #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) |
8bf3b005 | 318 | /* buggy schematic: LEDa -> yellow, LEDb --> green */ |
aaf224ab WD |
319 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
320 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
321 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
322 | #elif defined(CONFIG_ADNPESC1) | |
323 | /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ | |
8bf3b005 WD |
324 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ |
325 | | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | |
326 | | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) | |
327 | #else | |
328 | /* SMSC reference design: LEDa --> green, LEDb --> yellow */ | |
329 | #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ | |
330 | | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ | |
331 | | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) | |
332 | #endif | |
fe8c2806 WD |
333 | |
334 | /* Bank 0 0x000C is reserved */ | |
335 | ||
336 | /* Bank Select Register */ | |
337 | /* All Banks */ | |
338 | #define BSR_REG 0x000E | |
339 | ||
340 | ||
341 | /* Configuration Reg */ | |
342 | /* BANK 1 */ | |
343 | #define CONFIG_REG 0x0000 | |
344 | #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ | |
345 | #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ | |
346 | #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ | |
347 | #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ | |
348 | ||
349 | /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ | |
350 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
351 | ||
352 | ||
353 | /* Base Address Register */ | |
354 | /* BANK 1 */ | |
355 | #define BASE_REG 0x0002 | |
356 | ||
357 | ||
358 | /* Individual Address Registers */ | |
359 | /* BANK 1 */ | |
360 | #define ADDR0_REG 0x0004 | |
361 | #define ADDR1_REG 0x0006 | |
362 | #define ADDR2_REG 0x0008 | |
363 | ||
364 | ||
365 | /* General Purpose Register */ | |
366 | /* BANK 1 */ | |
367 | #define GP_REG 0x000A | |
368 | ||
369 | ||
370 | /* Control Register */ | |
371 | /* BANK 1 */ | |
372 | #define CTL_REG 0x000C | |
373 | #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ | |
374 | #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ | |
375 | #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ | |
376 | #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ | |
377 | #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ | |
378 | #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ | |
379 | #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ | |
380 | #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ | |
518e2e1a | 381 | #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ |
fe8c2806 WD |
382 | |
383 | /* MMU Command Register */ | |
384 | /* BANK 2 */ | |
385 | #define MMU_CMD_REG 0x0000 | |
386 | #define MC_BUSY 1 /* When 1 the last release has not completed */ | |
387 | #define MC_NOP (0<<5) /* No Op */ | |
388 | #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ | |
389 | #define MC_RESET (2<<5) /* Reset MMU to initial state */ | |
390 | #define MC_REMOVE (3<<5) /* Remove the current rx packet */ | |
391 | #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ | |
392 | #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ | |
393 | #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ | |
394 | #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ | |
395 | ||
396 | ||
397 | /* Packet Number Register */ | |
398 | /* BANK 2 */ | |
399 | #define PN_REG 0x0002 | |
400 | ||
401 | ||
402 | /* Allocation Result Register */ | |
403 | /* BANK 2 */ | |
404 | #define AR_REG 0x0003 | |
405 | #define AR_FAILED 0x80 /* Alocation Failed */ | |
406 | ||
407 | ||
408 | /* RX FIFO Ports Register */ | |
409 | /* BANK 2 */ | |
410 | #define RXFIFO_REG 0x0004 /* Must be read as a word */ | |
411 | #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ | |
412 | ||
413 | ||
414 | /* TX FIFO Ports Register */ | |
415 | /* BANK 2 */ | |
416 | #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ | |
417 | #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ | |
418 | ||
419 | ||
420 | /* Pointer Register */ | |
421 | /* BANK 2 */ | |
422 | #define PTR_REG 0x0006 | |
423 | #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ | |
424 | #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ | |
425 | #define PTR_READ 0x2000 /* When 1 the operation is a read */ | |
518e2e1a | 426 | #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ |
fe8c2806 WD |
427 | |
428 | ||
429 | /* Data Register */ | |
430 | /* BANK 2 */ | |
431 | #define SMC91111_DATA_REG 0x0008 | |
432 | ||
433 | ||
434 | /* Interrupt Status/Acknowledge Register */ | |
435 | /* BANK 2 */ | |
436 | #define SMC91111_INT_REG 0x000C | |
437 | ||
438 | ||
439 | /* Interrupt Mask Register */ | |
440 | /* BANK 2 */ | |
441 | #define IM_REG 0x000D | |
442 | #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ | |
443 | #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ | |
444 | #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ | |
445 | #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ | |
446 | #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ | |
447 | #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ | |
448 | #define IM_TX_INT 0x02 /* Transmit Interrrupt */ | |
449 | #define IM_RCV_INT 0x01 /* Receive Interrupt */ | |
450 | ||
451 | ||
452 | /* Multicast Table Registers */ | |
453 | /* BANK 3 */ | |
454 | #define MCAST_REG1 0x0000 | |
455 | #define MCAST_REG2 0x0002 | |
456 | #define MCAST_REG3 0x0004 | |
457 | #define MCAST_REG4 0x0006 | |
458 | ||
459 | ||
460 | /* Management Interface Register (MII) */ | |
461 | /* BANK 3 */ | |
462 | #define MII_REG 0x0008 | |
463 | #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ | |
464 | #define MII_MDOE 0x0008 /* MII Output Enable */ | |
465 | #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ | |
466 | #define MII_MDI 0x0002 /* MII Input, pin MDI */ | |
467 | #define MII_MDO 0x0001 /* MII Output, pin MDO */ | |
468 | ||
469 | ||
470 | /* Revision Register */ | |
471 | /* BANK 3 */ | |
472 | #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ | |
473 | ||
474 | ||
475 | /* Early RCV Register */ | |
476 | /* BANK 3 */ | |
477 | /* this is NOT on SMC9192 */ | |
478 | #define ERCV_REG 0x000C | |
479 | #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ | |
480 | #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ | |
481 | ||
482 | /* External Register */ | |
483 | /* BANK 7 */ | |
484 | #define EXT_REG 0x0000 | |
485 | ||
486 | ||
487 | #define CHIP_9192 3 | |
488 | #define CHIP_9194 4 | |
489 | #define CHIP_9195 5 | |
490 | #define CHIP_9196 6 | |
491 | #define CHIP_91100 7 | |
492 | #define CHIP_91100FD 8 | |
493 | #define CHIP_91111FD 9 | |
494 | ||
495 | #if 0 | |
496 | static const char * chip_ids[ 15 ] = { | |
497 | NULL, NULL, NULL, | |
498 | /* 3 */ "SMC91C90/91C92", | |
499 | /* 4 */ "SMC91C94", | |
500 | /* 5 */ "SMC91C95", | |
501 | /* 6 */ "SMC91C96", | |
502 | /* 7 */ "SMC91C100", | |
503 | /* 8 */ "SMC91C100FD", | |
504 | /* 9 */ "SMC91C111", | |
505 | NULL, NULL, | |
506 | NULL, NULL, NULL}; | |
507 | #endif | |
508 | ||
509 | /* | |
510 | . Transmit status bits | |
511 | */ | |
512 | #define TS_SUCCESS 0x0001 | |
513 | #define TS_LOSTCAR 0x0400 | |
514 | #define TS_LATCOL 0x0200 | |
515 | #define TS_16COL 0x0010 | |
516 | ||
517 | /* | |
518 | . Receive status bits | |
519 | */ | |
520 | #define RS_ALGNERR 0x8000 | |
521 | #define RS_BRODCAST 0x4000 | |
522 | #define RS_BADCRC 0x2000 | |
523 | #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ | |
524 | #define RS_TOOLONG 0x0800 | |
525 | #define RS_TOOSHORT 0x0400 | |
526 | #define RS_MULTICAST 0x0001 | |
527 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
528 | ||
529 | ||
530 | /* PHY Types */ | |
531 | enum { | |
532 | PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ | |
533 | PHY_LAN83C180 | |
534 | }; | |
535 | ||
536 | ||
537 | /* PHY Register Addresses (LAN91C111 Internal PHY) */ | |
538 | ||
539 | /* PHY Control Register */ | |
540 | #define PHY_CNTL_REG 0x00 | |
541 | #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ | |
542 | #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ | |
543 | #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ | |
544 | #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ | |
545 | #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ | |
546 | #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ | |
547 | #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ | |
548 | #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ | |
549 | #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ | |
550 | ||
551 | /* PHY Status Register */ | |
552 | #define PHY_STAT_REG 0x01 | |
553 | #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ | |
554 | #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ | |
555 | #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ | |
556 | #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ | |
557 | #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ | |
558 | #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ | |
559 | #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ | |
560 | #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ | |
561 | #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ | |
562 | #define PHY_STAT_LINK 0x0004 /* 1=valid link */ | |
563 | #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ | |
564 | #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ | |
565 | ||
566 | /* PHY Identifier Registers */ | |
567 | #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ | |
568 | #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ | |
569 | ||
570 | /* PHY Auto-Negotiation Advertisement Register */ | |
571 | #define PHY_AD_REG 0x04 | |
572 | #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ | |
573 | #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ | |
574 | #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ | |
575 | #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ | |
576 | #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ | |
577 | #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ | |
578 | #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ | |
579 | #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ | |
580 | #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ | |
581 | ||
582 | /* PHY Auto-negotiation Remote End Capability Register */ | |
583 | #define PHY_RMT_REG 0x05 | |
584 | /* Uses same bit definitions as PHY_AD_REG */ | |
585 | ||
586 | /* PHY Configuration Register 1 */ | |
587 | #define PHY_CFG1_REG 0x10 | |
588 | #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ | |
589 | #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ | |
590 | #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ | |
591 | #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ | |
592 | #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ | |
593 | #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ | |
594 | #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ | |
595 | #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ | |
596 | #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ | |
597 | #define PHY_CFG1_TLVL_MASK 0x003C | |
598 | #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ | |
599 | ||
600 | ||
601 | /* PHY Configuration Register 2 */ | |
602 | #define PHY_CFG2_REG 0x11 | |
603 | #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ | |
604 | #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ | |
605 | #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ | |
606 | #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ | |
607 | ||
608 | /* PHY Status Output (and Interrupt status) Register */ | |
609 | #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ | |
610 | #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ | |
611 | #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ | |
612 | #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ | |
613 | #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ | |
614 | #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ | |
615 | #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ | |
616 | #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ | |
617 | #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ | |
618 | #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ | |
619 | #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ | |
620 | ||
621 | /* PHY Interrupt/Status Mask Register */ | |
622 | #define PHY_MASK_REG 0x13 /* Interrupt Mask */ | |
623 | /* Uses the same bit definitions as PHY_INT_REG */ | |
624 | ||
625 | ||
fe8c2806 WD |
626 | /*------------------------------------------------------------------------- |
627 | . I define some macros to make it easier to do somewhat common | |
628 | . or slightly complicated, repeated tasks. | |
629 | --------------------------------------------------------------------------*/ | |
630 | ||
631 | /* select a register bank, 0 to 3 */ | |
632 | ||
633 | #define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } | |
634 | ||
635 | /* this enables an interrupt in the interrupt mask register */ | |
636 | #define SMC_ENABLE_INT(x) {\ | |
637 | unsigned char mask;\ | |
638 | SMC_SELECT_BANK(2);\ | |
639 | mask = SMC_inb( IM_REG );\ | |
640 | mask |= (x);\ | |
641 | SMC_outb( mask, IM_REG ); \ | |
642 | } | |
643 | ||
644 | /* this disables an interrupt from the interrupt mask register */ | |
645 | ||
646 | #define SMC_DISABLE_INT(x) {\ | |
647 | unsigned char mask;\ | |
648 | SMC_SELECT_BANK(2);\ | |
649 | mask = SMC_inb( IM_REG );\ | |
650 | mask &= ~(x);\ | |
651 | SMC_outb( mask, IM_REG ); \ | |
652 | } | |
653 | ||
654 | /*---------------------------------------------------------------------- | |
655 | . Define the interrupts that I want to receive from the card | |
656 | . | |
657 | . I want: | |
658 | . IM_EPH_INT, for nasty errors | |
659 | . IM_RCV_INT, for happy received packets | |
660 | . IM_RX_OVRN_INT, because I have to kick the receiver | |
661 | . IM_MDINT, for PHY Register 18 Status Changes | |
662 | --------------------------------------------------------------------------*/ | |
663 | #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ | |
664 | IM_MDINT) | |
665 | ||
666 | #endif /* _SMC_91111_H_ */ |