[people/arne_f/kernel.git] / drivers / soc / imx / gpc.c

/*
 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>

#define GPC_CNTR		0x000

#define GPC_PGC_CTRL_OFFS	0x0
#define GPC_PGC_PUPSCR_OFFS	0x4
#define GPC_PGC_PDNSCR_OFFS	0x8
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0

#define GPC_PGC_PCI_PDN		0x200
#define GPC_PGC_PCI_SR		0x20c

#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_GPU_SR		0x26c

#define GPC_PGC_DISP_PDN	0x240
#define GPC_PGC_DISP_SR		0x24c

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)

#define GPC_CLK_MAX		6

#define PGC_DOMAIN_FLAG_NO_PD		BIT(0)

struct imx_pm_domain {
	struct generic_pm_domain base;
	struct regmap *regmap;
	struct regulator *supply;
	struct clk *clk[GPC_CLK_MAX];
	int num_clks;
	unsigned int reg_offs;
	signed char cntr_pdn_bit;
	unsigned int ipg_rate_mhz;
	unsigned int flags;
};

static inline struct imx_pm_domain *
to_imx_pm_domain(struct generic_pm_domain *genpd)
{
	return container_of(genpd, struct imx_pm_domain, base);
}

static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
{
	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
	int iso, iso2sw;
	u32 val;

	if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
		return -EBUSY;

	/* Read ISO and ISO2SW power down delays */
	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val);
	iso = val & 0x3f;
	iso2sw = (val >> 8) & 0x3f;

	/* Gate off domain when powered down */
	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
			   0x1, 0x1);

	/* Request GPC to power down domain */
	val = BIT(pd->cntr_pdn_bit);
	regmap_update_bits(pd->regmap, GPC_CNTR, val, val);

	/* Wait ISO + ISO2SW IPG clock cycles */
	udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));

	if (pd->supply)
		regulator_disable(pd->supply);

	return 0;
}

static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
{
	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
	int i, ret, sw, sw2iso;
	u32 val;

	if (pd->supply) {
		ret = regulator_enable(pd->supply);
		if (ret) {
			pr_err("%s: failed to enable regulator: %d\n",
			       __func__, ret);
			return ret;
		}
	}

	/* Enable reset clocks for all devices in the domain */
	for (i = 0; i < pd->num_clks; i++)
		clk_prepare_enable(pd->clk[i]);

	/* Gate off domain when powered down */
	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
			   0x1, 0x1);

	/* Read ISO and ISO2SW power up delays */
	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
	sw = val & 0x3f;
	sw2iso = (val >> 8) & 0x3f;

	/* Request GPC to power up domain */
	val = BIT(pd->cntr_pdn_bit + 1);
	regmap_update_bits(pd->regmap, GPC_CNTR, val, val);

	/* Wait ISO + ISO2SW IPG clock cycles */
	udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));

	/* Disable reset clocks for all devices in the domain */
	for (i = 0; i < pd->num_clks; i++)
		clk_disable_unprepare(pd->clk[i]);

	return 0;
}

static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
{
	int i, ret;

	for (i = 0; ; i++) {
		struct clk *clk = of_clk_get(dev->of_node, i);
		if (IS_ERR(clk))
			break;
		if (i >= GPC_CLK_MAX) {
			dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
			ret = -EINVAL;
			goto clk_err;
		}
		domain->clk[i] = clk;
	}
	domain->num_clks = i;

	return 0;

clk_err:
	while (i--)
		clk_put(domain->clk[i]);

	return ret;
}

static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
{
	int i;

	for (i = domain->num_clks - 1; i >= 0; i--)
		clk_put(domain->clk[i]);
}

static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
{
	/* try to get the domain supply regulator */
	domain->supply = devm_regulator_get_optional(dev, "power");
	if (IS_ERR(domain->supply)) {
		if (PTR_ERR(domain->supply) == -ENODEV)
			domain->supply = NULL;
		else
			return PTR_ERR(domain->supply);
	}

	/* try to get all clocks needed for reset propagation */
	return imx_pgc_get_clocks(dev, domain);
}

static int imx_pgc_power_domain_probe(struct platform_device *pdev)
{
	struct imx_pm_domain *domain = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	int ret;

	/* if this PD is associated with a DT node try to parse it */
	if (dev->of_node) {
		ret = imx_pgc_parse_dt(dev, domain);
		if (ret)
			return ret;
	}

	/* initially power on the domain */
	if (domain->base.power_on)
		domain->base.power_on(&domain->base);

	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
		pm_genpd_init(&domain->base, NULL, false);
		ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
		if (ret)
			goto genpd_err;
	}

	device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);

	return 0;

genpd_err:
	pm_genpd_remove(&domain->base);
	imx_pgc_put_clocks(domain);

	return ret;
}

static int imx_pgc_power_domain_remove(struct platform_device *pdev)
{
	struct imx_pm_domain *domain = pdev->dev.platform_data;

	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
		of_genpd_del_provider(pdev->dev.of_node);
		pm_genpd_remove(&domain->base);
		imx_pgc_put_clocks(domain);
	}

	return 0;
}

static const struct platform_device_id imx_pgc_power_domain_id[] = {
	{ "imx-pgc-power-domain"},
	{ },
};

static struct platform_driver imx_pgc_power_domain_driver = {
	.driver = {
		.name = "imx-pgc-pd",
	},
	.probe = imx_pgc_power_domain_probe,
	.remove = imx_pgc_power_domain_remove,
	.id_table = imx_pgc_power_domain_id,
};
builtin_platform_driver(imx_pgc_power_domain_driver)

#define GPC_PGC_DOMAIN_ARM	0
#define GPC_PGC_DOMAIN_PU	1
#define GPC_PGC_DOMAIN_DISPLAY	2

static struct genpd_power_state imx6_pm_domain_pu_state = {
	.power_off_latency_ns = 25000,
	.power_on_latency_ns = 2000000,
};

static struct imx_pm_domain imx_gpc_domains[] = {
	{
		.base = {
			.name = "ARM",
		},
	}, {
		.base = {
			.name = "PU",
			.power_off = imx6_pm_domain_power_off,
			.power_on = imx6_pm_domain_power_on,
			.states = &imx6_pm_domain_pu_state,
			.state_count = 1,
		},
		.reg_offs = 0x260,
		.cntr_pdn_bit = 0,
	}, {
		.base = {
			.name = "DISPLAY",
			.power_off = imx6_pm_domain_power_off,
			.power_on = imx6_pm_domain_power_on,
		},
		.reg_offs = 0x240,
		.cntr_pdn_bit = 4,
	}
};

struct imx_gpc_dt_data {
	int num_domains;
	bool err009619_present;
};

static const struct imx_gpc_dt_data imx6q_dt_data = {
	.num_domains = 2,
	.err009619_present = false,
};

static const struct imx_gpc_dt_data imx6qp_dt_data = {
	.num_domains = 2,
	.err009619_present = true,
};

static const struct imx_gpc_dt_data imx6sl_dt_data = {
	.num_domains = 3,
	.err009619_present = false,
};

static const struct of_device_id imx_gpc_dt_ids[] = {
	{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
	{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
	{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
	{ }
};

static const struct regmap_range yes_ranges[] = {
	regmap_reg_range(GPC_CNTR, GPC_CNTR),
	regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
	regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
	regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
};

static const struct regmap_access_table access_table = {
	.yes_ranges	= yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(yes_ranges),
};

static const struct regmap_config imx_gpc_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.rd_table = &access_table,
	.wr_table = &access_table,
	.max_register = 0x2ac,
};

static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
	&imx_gpc_domains[0].base,
	&imx_gpc_domains[1].base,
};

static struct genpd_onecell_data imx_gpc_onecell_data = {
	.domains = imx_gpc_onecell_domains,
	.num_domains = 2,
};

static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
			       unsigned int num_domains)
{
	struct imx_pm_domain *domain;
	int i, ret;

	for (i = 0; i < num_domains; i++) {
		domain = &imx_gpc_domains[i];
		domain->regmap = regmap;
		domain->ipg_rate_mhz = 66;

		if (i == 1) {
			domain->supply = devm_regulator_get(dev, "pu");
			if (IS_ERR(domain->supply))
				return PTR_ERR(domain->supply);;

			ret = imx_pgc_get_clocks(dev, domain);
			if (ret)
				goto clk_err;

			domain->base.power_on(&domain->base);
		}
	}

	for (i = 0; i < num_domains; i++)
		pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);

	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
		ret = of_genpd_add_provider_onecell(dev->of_node,
						    &imx_gpc_onecell_data);
		if (ret)
			goto genpd_err;
	}

	return 0;

genpd_err:
	for (i = 0; i < num_domains; i++)
		pm_genpd_remove(&imx_gpc_domains[i].base);
	imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
clk_err:
	return ret;
}

static int imx_gpc_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(imx_gpc_dt_ids, &pdev->dev);
	const struct imx_gpc_dt_data *of_id_data = of_id->data;
	struct device_node *pgc_node;
	struct regmap *regmap;
	struct resource *res;
	void __iomem *base;
	int ret;

	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");

	/* bail out if DT too old and doesn't provide the necessary info */
	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
	    !pgc_node)
		return 0;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
					   &imx_gpc_regmap_config);
	if (IS_ERR(regmap)) {
		ret = PTR_ERR(regmap);
		dev_err(&pdev->dev, "failed to init regmap: %d\n",
			ret);
		return ret;
	}

	/* Disable PU power down in normal operation if ERR009619 is present */
	if (of_id_data->err009619_present)
		imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags |=
				PGC_DOMAIN_FLAG_NO_PD;

	if (!pgc_node) {
		ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
					  of_id_data->num_domains);
		if (ret)
			return ret;
	} else {
		struct imx_pm_domain *domain;
		struct platform_device *pd_pdev;
		struct device_node *np;
		struct clk *ipg_clk;
		unsigned int ipg_rate_mhz;
		int domain_index;

		ipg_clk = devm_clk_get(&pdev->dev, "ipg");
		if (IS_ERR(ipg_clk))
			return PTR_ERR(ipg_clk);
		ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;

		for_each_child_of_node(pgc_node, np) {
			ret = of_property_read_u32(np, "reg", &domain_index);
			if (ret) {
				of_node_put(np);
				return ret;
			}
			if (domain_index >= of_id_data->num_domains)
				continue;

			domain = &imx_gpc_domains[domain_index];
			domain->regmap = regmap;
			domain->ipg_rate_mhz = ipg_rate_mhz;

			pd_pdev = platform_device_alloc("imx-pgc-power-domain",
							domain_index);
			if (!pd_pdev) {
				of_node_put(np);
				return -ENOMEM;
			}
			pd_pdev->dev.platform_data = domain;
			pd_pdev->dev.parent = &pdev->dev;
			pd_pdev->dev.of_node = np;

			ret = platform_device_add(pd_pdev);
			if (ret) {
				platform_device_put(pd_pdev);
				of_node_put(np);
				return ret;
			}
		}
	}

	return 0;
}

static int imx_gpc_remove(struct platform_device *pdev)
{
	struct device_node *pgc_node;
	int ret;

	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");

	/* bail out if DT too old and doesn't provide the necessary info */
	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
	    !pgc_node)
		return 0;

	/*
	 * If the old DT binding is used the toplevel driver needs to
	 * de-register the power domains
	 */
	if (!pgc_node) {
		of_genpd_del_provider(pdev->dev.of_node);

		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
		if (ret)
			return ret;
		imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);

		ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
		if (ret)
			return ret;
	}

	return 0;
}

static struct platform_driver imx_gpc_driver = {
	.driver = {
		.name = "imx-gpc",
		.of_match_table = imx_gpc_dt_ids,
	},
	.probe = imx_gpc_probe,
	.remove = imx_gpc_remove,
};
builtin_platform_driver(imx_gpc_driver)
Commit	Line	Data
721cabf6 LS	1	/*
	2	* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
	3	* Copyright 2011-2013 Freescale Semiconductor, Inc.
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/delay.h>
	15	#include <linux/io.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pm_domain.h>
	19	#include <linux/regmap.h>
	20	#include <linux/regulator/consumer.h>
	21
	22	#define GPC_CNTR 0x000
	23
fbb0b440	24	#define GPC_PGC_CTRL_OFFS 0x0
721cabf6 LS	25	#define GPC_PGC_PUPSCR_OFFS 0x4
	26	#define GPC_PGC_PDNSCR_OFFS 0x8
	27	#define GPC_PGC_SW2ISO_SHIFT 0x8
	28	#define GPC_PGC_SW_SHIFT 0x0
	29
715f5f92 AH	30	#define GPC_PGC_PCI_PDN 0x200
	31	#define GPC_PGC_PCI_SR 0x20c
	32
721cabf6 LS	33	#define GPC_PGC_GPU_PDN 0x260
	34	#define GPC_PGC_GPU_PUPSCR 0x264
	35	#define GPC_PGC_GPU_PDNSCR 0x268
715f5f92 AH	36	#define GPC_PGC_GPU_SR 0x26c
	37
	38	#define GPC_PGC_DISP_PDN 0x240
	39	#define GPC_PGC_DISP_SR 0x24c
721cabf6 LS	40
	41	#define GPU_VPU_PUP_REQ BIT(1)
	42	#define GPU_VPU_PDN_REQ BIT(0)
	43
	44	#define GPC_CLK_MAX 6
	45
44c43c98 LS	46	#define PGC_DOMAIN_FLAG_NO_PD BIT(0)
44c43c98 LS	47
721cabf6 LS	48	struct imx_pm_domain {
	49	struct generic_pm_domain base;
	50	struct regmap *regmap;
	51	struct regulator *supply;
	52	struct clk *clk[GPC_CLK_MAX];
	53	int num_clks;
	54	unsigned int reg_offs;
	55	signed char cntr_pdn_bit;
	56	unsigned int ipg_rate_mhz;
44c43c98	57	unsigned int flags;
721cabf6 LS	58	};
	59
	60	static inline struct imx_pm_domain *
	61	to_imx_pm_domain(struct generic_pm_domain *genpd)
	62	{
	63	return container_of(genpd, struct imx_pm_domain, base);
	64	}
	65
	66	static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
	67	{
	68	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
	69	int iso, iso2sw;
	70	u32 val;
	71
44c43c98 LS	72	if (pd->flags & PGC_DOMAIN_FLAG_NO_PD)
	73	return -EBUSY;
	74
721cabf6	75	/* Read ISO and ISO2SW power down delays */
830a50a3	76	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val);
721cabf6 LS	77	iso = val & 0x3f;
	78	iso2sw = (val >> 8) & 0x3f;
	79
	80	/* Gate off domain when powered down */
fbb0b440	81	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
721cabf6 LS	82	0x1, 0x1);
	83
	84	/* Request GPC to power down domain */
	85	val = BIT(pd->cntr_pdn_bit);
	86	regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
	87
	88	/* Wait ISO + ISO2SW IPG clock cycles */
	89	udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
	90
	91	if (pd->supply)
	92	regulator_disable(pd->supply);
	93
	94	return 0;
	95	}
	96
	97	static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
	98	{
	99	struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
	100	int i, ret, sw, sw2iso;
	101	u32 val;
	102
	103	if (pd->supply) {
	104	ret = regulator_enable(pd->supply);
	105	if (ret) {
	106	pr_err("%s: failed to enable regulator: %d\n",
	107	__func__, ret);
	108	return ret;
	109	}
	110	}
	111
	112	/* Enable reset clocks for all devices in the domain */
	113	for (i = 0; i < pd->num_clks; i++)
	114	clk_prepare_enable(pd->clk[i]);
	115
	116	/* Gate off domain when powered down */
fbb0b440	117	regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
721cabf6 LS	118	0x1, 0x1);
721cabf6 LS	119
6e6e339c	120	/* Read ISO and ISO2SW power up delays */
721cabf6 LS	121	regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
	122	sw = val & 0x3f;
	123	sw2iso = (val >> 8) & 0x3f;
	124
	125	/* Request GPC to power up domain */
	126	val = BIT(pd->cntr_pdn_bit + 1);
	127	regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
	128
	129	/* Wait ISO + ISO2SW IPG clock cycles */
	130	udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
	131
	132	/* Disable reset clocks for all devices in the domain */
	133	for (i = 0; i < pd->num_clks; i++)
	134	clk_disable_unprepare(pd->clk[i]);
	135
	136	return 0;
	137	}
	138
	139	static int imx_pgc_get_clocks(struct device dev, struct imx_pm_domain domain)
	140	{
	141	int i, ret;
	142
	143	for (i = 0; ; i++) {
	144	struct clk *clk = of_clk_get(dev->of_node, i);
	145	if (IS_ERR(clk))
	146	break;
	147	if (i >= GPC_CLK_MAX) {
	148	dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
	149	ret = -EINVAL;
	150	goto clk_err;
	151	}
	152	domain->clk[i] = clk;
	153	}
	154	domain->num_clks = i;
	155
	156	return 0;
	157
	158	clk_err:
55b0baa2	159	while (i--)
721cabf6 LS	160	clk_put(domain->clk[i]);
	161
	162	return ret;
	163	}
	164
	165	static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
	166	{
	167	int i;
	168
	169	for (i = domain->num_clks - 1; i >= 0; i--)
	170	clk_put(domain->clk[i]);
	171	}
	172
	173	static int imx_pgc_parse_dt(struct device dev, struct imx_pm_domain domain)
	174	{
	175	/* try to get the domain supply regulator */
	176	domain->supply = devm_regulator_get_optional(dev, "power");
	177	if (IS_ERR(domain->supply)) {
	178	if (PTR_ERR(domain->supply) == -ENODEV)
	179	domain->supply = NULL;
	180	else
	181	return PTR_ERR(domain->supply);
	182	}
	183
	184	/* try to get all clocks needed for reset propagation */
	185	return imx_pgc_get_clocks(dev, domain);
	186	}
	187
	188	static int imx_pgc_power_domain_probe(struct platform_device *pdev)
	189	{
	190	struct imx_pm_domain *domain = pdev->dev.platform_data;
	191	struct device *dev = &pdev->dev;
	192	int ret;
	193
	194	/* if this PD is associated with a DT node try to parse it */
	195	if (dev->of_node) {
	196	ret = imx_pgc_parse_dt(dev, domain);
	197	if (ret)
	198	return ret;
	199	}
	200
	201	/* initially power on the domain */
	202	if (domain->base.power_on)
	203	domain->base.power_on(&domain->base);
	204
	205	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
	206	pm_genpd_init(&domain->base, NULL, false);
	207	ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
	208	if (ret)
	209	goto genpd_err;
	210	}
	211
	212	device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE);
	213
	214	return 0;
	215
	216	genpd_err:
	217	pm_genpd_remove(&domain->base);
	218	imx_pgc_put_clocks(domain);
	219
	220	return ret;
	221	}
	222
	223	static int imx_pgc_power_domain_remove(struct platform_device *pdev)
224	{
225	struct imx_pm_domain *domain = pdev->dev.platform_data;
226
227	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
228	of_genpd_del_provider(pdev->dev.of_node);
229	pm_genpd_remove(&domain->base);
230	imx_pgc_put_clocks(domain);
231	}
232
233	return 0;
234	}
235
236	static const struct platform_device_id imx_pgc_power_domain_id[] = {
237	{ "imx-pgc-power-domain"},
238	{ },
239	};
240
241	static struct platform_driver imx_pgc_power_domain_driver = {
242	.driver = {
243	.name = "imx-pgc-pd",
244	},
245	.probe = imx_pgc_power_domain_probe,
246	.remove = imx_pgc_power_domain_remove,
247	.id_table = imx_pgc_power_domain_id,
248	};
249	builtin_platform_driver(imx_pgc_power_domain_driver)
250
7c42af78 LS	251	#define GPC_PGC_DOMAIN_ARM 0
	252	#define GPC_PGC_DOMAIN_PU 1
	253	#define GPC_PGC_DOMAIN_DISPLAY 2
	254
721cabf6 LS	255	static struct genpd_power_state imx6_pm_domain_pu_state = {
	256	.power_off_latency_ns = 25000,
	257	.power_on_latency_ns = 2000000,
	258	};
	259
	260	static struct imx_pm_domain imx_gpc_domains[] = {
	261	{
	262	.base = {
	263	.name = "ARM",
	264	},
	265	}, {
	266	.base = {
	267	.name = "PU",
	268	.power_off = imx6_pm_domain_power_off,
	269	.power_on = imx6_pm_domain_power_on,
	270	.states = &imx6_pm_domain_pu_state,
	271	.state_count = 1,
	272	},
	273	.reg_offs = 0x260,
	274	.cntr_pdn_bit = 0,
	275	}, {
	276	.base = {
	277	.name = "DISPLAY",
	278	.power_off = imx6_pm_domain_power_off,
	279	.power_on = imx6_pm_domain_power_on,
	280	},
	281	.reg_offs = 0x240,
	282	.cntr_pdn_bit = 4,
	283	}
	284	};
	285
	286	struct imx_gpc_dt_data {
	287	int num_domains;
44c43c98	288	bool err009619_present;
721cabf6 LS	289	};
	290
	291	static const struct imx_gpc_dt_data imx6q_dt_data = {
	292	.num_domains = 2,
44c43c98 LS	293	.err009619_present = false,
	294	};
	295
	296	static const struct imx_gpc_dt_data imx6qp_dt_data = {
	297	.num_domains = 2,
	298	.err009619_present = true,
721cabf6 LS	299	};
	300
	301	static const struct imx_gpc_dt_data imx6sl_dt_data = {
	302	.num_domains = 3,
44c43c98	303	.err009619_present = false,
721cabf6 LS	304	};
	305
	306	static const struct of_device_id imx_gpc_dt_ids[] = {
	307	{ .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
44c43c98	308	{ .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
721cabf6 LS	309	{ .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
	310	{ }
	311	};
	312
715f5f92 AH	313	static const struct regmap_range yes_ranges[] = {
	314	regmap_reg_range(GPC_CNTR, GPC_CNTR),
	315	regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
	316	regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
	317	regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
	318	};
	319
	320	static const struct regmap_access_table access_table = {
	321	.yes_ranges = yes_ranges,
	322	.n_yes_ranges = ARRAY_SIZE(yes_ranges),
	323	};
	324
721cabf6	325	static const struct regmap_config imx_gpc_regmap_config = {
721cabf6 LS	326	.reg_bits = 32,
	327	.val_bits = 32,
	328	.reg_stride = 4,
715f5f92 AH	329	.rd_table = &access_table,
715f5f92 AH	330	.wr_table = &access_table,
721cabf6 LS	331	.max_register = 0x2ac,
	332	};
	333
	334	static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
	335	&imx_gpc_domains[0].base,
	336	&imx_gpc_domains[1].base,
	337	};
	338
	339	static struct genpd_onecell_data imx_gpc_onecell_data = {
	340	.domains = imx_gpc_onecell_domains,
	341	.num_domains = 2,
	342	};
	343
5a42d119 DA	344	static int imx_gpc_old_dt_init(struct device dev, struct regmap regmap,
5a42d119 DA	345	unsigned int num_domains)
721cabf6 LS	346	{
	347	struct imx_pm_domain *domain;
	348	int i, ret;
	349
5a42d119	350	for (i = 0; i < num_domains; i++) {
721cabf6 LS	351	domain = &imx_gpc_domains[i];
	352	domain->regmap = regmap;
	353	domain->ipg_rate_mhz = 66;
	354
	355	if (i == 1) {
	356	domain->supply = devm_regulator_get(dev, "pu");
	357	if (IS_ERR(domain->supply))
	358	return PTR_ERR(domain->supply);;
	359
	360	ret = imx_pgc_get_clocks(dev, domain);
	361	if (ret)
	362	goto clk_err;
	363
	364	domain->base.power_on(&domain->base);
	365	}
	366	}
	367
5a42d119	368	for (i = 0; i < num_domains; i++)
721cabf6 LS	369	pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
	370
	371	if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
	372	ret = of_genpd_add_provider_onecell(dev->of_node,
	373	&imx_gpc_onecell_data);
	374	if (ret)
	375	goto genpd_err;
	376	}
	377
	378	return 0;
	379
	380	genpd_err:
5a42d119	381	for (i = 0; i < num_domains; i++)
721cabf6	382	pm_genpd_remove(&imx_gpc_domains[i].base);
7c42af78	383	imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
721cabf6 LS	384	clk_err:
	385	return ret;
	386	}
	387
	388	static int imx_gpc_probe(struct platform_device *pdev)
	389	{
	390	const struct of_device_id *of_id =
	391	of_match_device(imx_gpc_dt_ids, &pdev->dev);
	392	const struct imx_gpc_dt_data *of_id_data = of_id->data;
	393	struct device_node *pgc_node;
	394	struct regmap *regmap;
	395	struct resource *res;
	396	void __iomem *base;
	397	int ret;
	398
	399	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
	400
	401	/* bail out if DT too old and doesn't provide the necessary info */
	402	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
	403	!pgc_node)
	404	return 0;
	405
	406	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	407	base = devm_ioremap_resource(&pdev->dev, res);
	408	if (IS_ERR(base))
	409	return PTR_ERR(base);
	410
	411	regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	412	&imx_gpc_regmap_config);
	413	if (IS_ERR(regmap)) {
	414	ret = PTR_ERR(regmap);
	415	dev_err(&pdev->dev, "failed to init regmap: %d\n",
	416	ret);
	417	return ret;
	418	}
	419
44c43c98 LS	420	/* Disable PU power down in normal operation if ERR009619 is present */
	421	if (of_id_data->err009619_present)
	422	imx_gpc_domains[GPC_PGC_DOMAIN_PU].flags \|=
	423	PGC_DOMAIN_FLAG_NO_PD;
	424
721cabf6	425	if (!pgc_node) {
5a42d119 DA	426	ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
5a42d119 DA	427	of_id_data->num_domains);
721cabf6 LS	428	if (ret)
	429	return ret;
	430	} else {
	431	struct imx_pm_domain *domain;
	432	struct platform_device *pd_pdev;
	433	struct device_node *np;
	434	struct clk *ipg_clk;
	435	unsigned int ipg_rate_mhz;
	436	int domain_index;
	437
	438	ipg_clk = devm_clk_get(&pdev->dev, "ipg");
	439	if (IS_ERR(ipg_clk))
	440	return PTR_ERR(ipg_clk);
	441	ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
	442
	443	for_each_child_of_node(pgc_node, np) {
	444	ret = of_property_read_u32(np, "reg", &domain_index);
	445	if (ret) {
	446	of_node_put(np);
	447	return ret;
	448	}
15c3de4e	449	if (domain_index >= of_id_data->num_domains)
721cabf6 LS	450	continue;
	451
	452	domain = &imx_gpc_domains[domain_index];
	453	domain->regmap = regmap;
	454	domain->ipg_rate_mhz = ipg_rate_mhz;
	455
	456	pd_pdev = platform_device_alloc("imx-pgc-power-domain",
	457	domain_index);
	458	if (!pd_pdev) {
	459	of_node_put(np);
	460	return -ENOMEM;
	461	}
	462	pd_pdev->dev.platform_data = domain;
	463	pd_pdev->dev.parent = &pdev->dev;
	464	pd_pdev->dev.of_node = np;
	465
	466	ret = platform_device_add(pd_pdev);
	467	if (ret) {
	468	platform_device_put(pd_pdev);
	469	of_node_put(np);
	470	return ret;
	471	}
	472	}
	473	}
	474
	475	return 0;
	476	}
	477
	478	static int imx_gpc_remove(struct platform_device *pdev)
	479	{
e1bb3673	480	struct device_node *pgc_node;
721cabf6 LS	481	int ret;
721cabf6 LS	482
e1bb3673 SA	483	pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
	484
	485	/* bail out if DT too old and doesn't provide the necessary info */
	486	if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
	487	!pgc_node)
	488	return 0;
	489
721cabf6 LS	490	/*
	491	* If the old DT binding is used the toplevel driver needs to
	492	* de-register the power domains
	493	*/
e1bb3673	494	if (!pgc_node) {
721cabf6 LS	495	of_genpd_del_provider(pdev->dev.of_node);
721cabf6 LS	496
7c42af78	497	ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
721cabf6 LS	498	if (ret)
721cabf6 LS	499	return ret;
7c42af78	500	imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
721cabf6	501
7c42af78	502	ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
721cabf6 LS	503	if (ret)
	504	return ret;
	505	}
	506
	507	return 0;
	508	}
	509
	510	static struct platform_driver imx_gpc_driver = {
	511	.driver = {
	512	.name = "imx-gpc",
	513	.of_match_table = imx_gpc_dt_ids,
	514	},
	515	.probe = imx_gpc_probe,
	516	.remove = imx_gpc_remove,
	517	};
	518	builtin_platform_driver(imx_gpc_driver)