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a2d8e0a7 RS |
1 | /* |
2 | * (C) Copyright 2012 Samsung Electronics | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
a2d8e0a7 RS |
5 | */ |
6 | ||
7 | #ifndef __WM8994_REGISTERS_H__ | |
8 | #define __WM8994_REGISTERS_H__ | |
9 | ||
10 | /* | |
11 | * Register values. | |
12 | */ | |
13 | #define WM8994_SOFTWARE_RESET 0x00 | |
14 | #define WM8994_POWER_MANAGEMENT_1 0x01 | |
15 | #define WM8994_POWER_MANAGEMENT_2 0x02 | |
d981d80d | 16 | #define WM8994_POWER_MANAGEMENT_4 0x04 |
a2d8e0a7 RS |
17 | #define WM8994_POWER_MANAGEMENT_5 0x05 |
18 | #define WM8994_LEFT_OUTPUT_VOLUME 0x1C | |
19 | #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D | |
20 | #define WM8994_OUTPUT_MIXER_1 0x2D | |
21 | #define WM8994_OUTPUT_MIXER_2 0x2E | |
22 | #define WM8994_CHARGE_PUMP_1 0x4C | |
23 | #define WM8994_DC_SERVO_1 0x54 | |
24 | #define WM8994_ANALOGUE_HP_1 0x60 | |
25 | #define WM8994_CHIP_REVISION 0x100 | |
26 | #define WM8994_AIF1_CLOCKING_1 0x200 | |
27 | #define WM8994_AIF1_CLOCKING_2 0x201 | |
28 | #define WM8994_AIF2_CLOCKING_1 0x204 | |
29 | #define WM8994_CLOCKING_1 0x208 | |
30 | #define WM8994_CLOCKING_2 0x209 | |
31 | #define WM8994_AIF1_RATE 0x210 | |
32 | #define WM8994_AIF2_RATE 0x211 | |
33 | #define WM8994_RATE_STATUS 0x212 | |
34 | #define WM8994_AIF1_CONTROL_1 0x300 | |
35 | #define WM8994_AIF1_CONTROL_2 0x301 | |
36 | #define WM8994_AIF1_MASTER_SLAVE 0x302 | |
37 | #define WM8994_AIF1_BCLK 0x303 | |
38 | #define WM8994_AIF2_CONTROL_1 0x310 | |
39 | #define WM8994_AIF2_CONTROL_2 0x311 | |
40 | #define WM8994_AIF2_MASTER_SLAVE 0x312 | |
41 | #define WM8994_AIF2_BCLK 0x313 | |
d981d80d | 42 | #define WM8994_AIF1_DAC_FILTERS_1 0x420 |
a2d8e0a7 RS |
43 | #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 |
44 | #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 | |
45 | #define WM8994_AIF2_DAC_FILTERS_1 0x520 | |
46 | #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 | |
47 | #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 | |
48 | #define WM8994_DAC1_LEFT_VOLUME 0x610 | |
49 | #define WM8994_DAC1_RIGHT_VOLUME 0x611 | |
d981d80d | 50 | #define WM8994_GPIO_1 0x700 |
a2d8e0a7 RS |
51 | #define WM8994_GPIO_3 0x702 |
52 | #define WM8994_GPIO_4 0x703 | |
53 | #define WM8994_GPIO_5 0x704 | |
54 | ||
55 | /* | |
56 | * Field Definitions. | |
57 | */ | |
58 | ||
59 | /* | |
60 | * R0 (0x00) - Software Reset | |
61 | */ | |
62 | /* SW_RESET */ | |
63 | #define WM8994_SW_RESET 1 | |
64 | /* | |
65 | * R1 (0x01) - Power Management (1) | |
66 | */ | |
67 | /* HPOUT1L_ENA */ | |
68 | #define WM8994_HPOUT1L_ENA 0x0200 | |
69 | /* HPOUT1L_ENA */ | |
70 | #define WM8994_HPOUT1L_ENA_MASK 0x0200 | |
71 | /* HPOUT1R_ENA */ | |
72 | #define WM8994_HPOUT1R_ENA 0x0100 | |
73 | /* HPOUT1R_ENA */ | |
74 | #define WM8994_HPOUT1R_ENA_MASK 0x0100 | |
75 | /* VMID_SEL - [2:1] */ | |
76 | #define WM8994_VMID_SEL_MASK 0x0006 | |
77 | /* BIAS_ENA */ | |
78 | #define WM8994_BIAS_ENA 0x0001 | |
79 | /* BIAS_ENA */ | |
80 | #define WM8994_BIAS_ENA_MASK 0x0001 | |
81 | ||
82 | /* | |
83 | * R2 (0x02) - Power Management (2) | |
84 | */ | |
85 | /* OPCLK_ENA */ | |
86 | #define WM8994_OPCLK_ENA 0x0800 | |
87 | ||
d981d80d DKM |
88 | #define WM8994_TSHUT_ENA 0x4000 |
89 | #define WM8994_MIXINL_ENA 0x0200 | |
90 | #define WM8994_MIXINR_ENA 0x0100 | |
91 | #define WM8994_IN2L_ENA 0x0080 | |
92 | #define WM8994_IN2R_ENA 0x0020 | |
93 | ||
94 | /* | |
95 | * R5 (0x04) - Power Management (4) | |
96 | */ | |
97 | #define WM8994_ADCL_ENA 0x0001 | |
98 | #define WM8994_ADCR_ENA 0x0002 | |
99 | #define WM8994_AIF1ADC1R_ENA 0x0100 | |
100 | #define WM8994_AIF1ADC1L_ENA 0x0200 | |
101 | ||
a2d8e0a7 RS |
102 | /* |
103 | * R5 (0x05) - Power Management (5) | |
104 | */ | |
105 | /* AIF2DACL_ENA */ | |
106 | #define WM8994_AIF2DACL_ENA 0x2000 | |
107 | #define WM8994_AIF2DACL_ENA_MASK 0x2000 | |
108 | /* AIF2DACR_ENA */ | |
109 | #define WM8994_AIF2DACR_ENA 0x1000 | |
110 | #define WM8994_AIF2DACR_ENA_MASK 0x1000 | |
d981d80d DKM |
111 | /* AIF1DACL_ENA */ |
112 | #define WM8994_AIF1DACL_ENA 0x0200 | |
113 | #define WM8994_AIF1DACL_ENA_MASK 0x0200 | |
114 | /* AIF1DACR_ENA */ | |
115 | #define WM8994_AIF1DACR_ENA 0x0100 | |
116 | #define WM8994_AIF1DACR_ENA_MASK 0x0100 | |
a2d8e0a7 RS |
117 | /* DAC1L_ENA */ |
118 | #define WM8994_DAC1L_ENA 0x0002 | |
119 | #define WM8994_DAC1L_ENA_MASK 0x0002 | |
120 | /* DAC1R_ENA */ | |
121 | #define WM8994_DAC1R_ENA 0x0001 | |
122 | #define WM8994_DAC1R_ENA_MASK 0x0001 | |
123 | ||
124 | /* | |
125 | * R45 (0x2D) - Output Mixer (1) | |
126 | */ | |
127 | /* DAC1L_TO_HPOUT1L */ | |
128 | #define WM8994_DAC1L_TO_HPOUT1L 0x0100 | |
129 | #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 | |
130 | ||
131 | /* | |
132 | * R46 (0x2E) - Output Mixer (2) | |
133 | */ | |
134 | /* DAC1R_TO_HPOUT1R */ | |
135 | #define WM8994_DAC1R_TO_HPOUT1R 0x0100 | |
136 | #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 | |
137 | ||
138 | /* | |
139 | * R76 (0x4C) - Charge Pump (1) | |
140 | */ | |
141 | /* CP_ENA */ | |
142 | #define WM8994_CP_ENA 0x8000 | |
143 | #define WM8994_CP_ENA_MASK 0x8000 | |
144 | /* | |
145 | * R84 (0x54) - DC Servo (1) | |
146 | */ | |
147 | /* DCS_ENA_CHAN_1 */ | |
148 | #define WM8994_DCS_ENA_CHAN_1 0x0002 | |
149 | #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 | |
150 | /* DCS_ENA_CHAN_0 */ | |
151 | #define WM8994_DCS_ENA_CHAN_0 0x0001 | |
152 | #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 | |
153 | ||
154 | /* | |
155 | * R96 (0x60) - Analogue HP (1) | |
156 | */ | |
157 | /* HPOUT1L_RMV_SHORT */ | |
158 | #define WM8994_HPOUT1L_RMV_SHORT 0x0080 | |
159 | #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 | |
160 | /* HPOUT1L_OUTP */ | |
161 | #define WM8994_HPOUT1L_OUTP 0x0040 | |
162 | #define WM8994_HPOUT1L_OUTP_MASK 0x0040 | |
163 | /* HPOUT1L_DLY */ | |
164 | #define WM8994_HPOUT1L_DLY 0x0020 | |
165 | #define WM8994_HPOUT1L_DLY_MASK 0x0020 | |
166 | /* HPOUT1R_RMV_SHORT */ | |
167 | #define WM8994_HPOUT1R_RMV_SHORT 0x0008 | |
168 | #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 | |
169 | /* HPOUT1R_OUTP */ | |
170 | #define WM8994_HPOUT1R_OUTP 0x0004 | |
171 | #define WM8994_HPOUT1R_OUTP_MASK 0x0004 | |
172 | /* HPOUT1R_DLY */ | |
173 | #define WM8994_HPOUT1R_DLY 0x0002 | |
174 | #define WM8994_HPOUT1R_DLY_MASK 0x0002 | |
175 | ||
176 | /* | |
177 | * R512 (0x200) - AIF1 Clocking (1) | |
178 | */ | |
179 | /* AIF1CLK_SRC - [4:3] */ | |
180 | #define WM8994_AIF1CLK_SRC_MASK 0x0018 | |
181 | /* AIF1CLK_DIV */ | |
182 | #define WM8994_AIF1CLK_DIV 0x0002 | |
183 | /* AIF1CLK_ENA */ | |
184 | #define WM8994_AIF1CLK_ENA 0x0001 | |
185 | #define WM8994_AIF1CLK_ENA_MASK 0x0001 | |
186 | ||
187 | /* | |
188 | * R517 (0x205) - AIF2 Clocking (2) | |
189 | */ | |
190 | /* AIF2DAC_DIV - [5:3] */ | |
191 | #define WM8994_AIF2DAC_DIV_MASK 0x0038 | |
192 | ||
193 | /* | |
194 | * R520 (0x208) - Clocking (1) | |
195 | */ | |
d981d80d DKM |
196 | /* AIF1DSPCLK_ENA */ |
197 | #define WM8994_AIF1DSPCLK_ENA 0x0008 | |
198 | #define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 | |
a2d8e0a7 RS |
199 | /* AIF2DSPCLK_ENA */ |
200 | #define WM8994_AIF2DSPCLK_ENA 0x0004 | |
201 | #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 | |
202 | /* SYSDSPCLK_ENA */ | |
203 | #define WM8994_SYSDSPCLK_ENA 0x0002 | |
204 | #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 | |
205 | /* SYSCLK_SRC */ | |
206 | #define WM8994_SYSCLK_SRC 0x0001 | |
207 | ||
208 | /* | |
209 | * R521 (0x209) - Clocking (2) | |
210 | */ | |
211 | /* OPCLK_DIV - [2:0] */ | |
212 | #define WM8994_OPCLK_DIV_MASK 0x0007 | |
213 | ||
214 | /* | |
215 | * R528 (0x210) - AIF1 Rate | |
216 | */ | |
217 | /* AIF1_SR - [7:4] */ | |
218 | #define WM8994_AIF1_SR_MASK 0x00F0 | |
219 | #define WM8994_AIF1_SR_SHIFT 4 | |
220 | /* AIF1CLK_RATE - [3:0] */ | |
221 | #define WM8994_AIF1CLK_RATE_MASK 0x000F | |
222 | ||
223 | /* | |
224 | * R768 (0x300) - AIF1 Control (1) | |
225 | */ | |
226 | /* AIF1_BCLK_INV */ | |
227 | #define WM8994_AIF1_BCLK_INV 0x0100 | |
228 | /* AIF1_LRCLK_INV */ | |
229 | #define WM8994_AIF1_LRCLK_INV 0x0080 | |
230 | #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 | |
231 | /* AIF1_WL - [6:5] */ | |
232 | #define WM8994_AIF1_WL_MASK 0x0060 | |
233 | /* AIF1_FMT - [4:3] */ | |
234 | #define WM8994_AIF1_FMT_MASK 0x0018 | |
235 | ||
236 | /* | |
237 | * R769 (0x301) - AIF1 Control (2) | |
238 | */ | |
239 | /* AIF1_MONO */ | |
240 | #define WM8994_AIF1_MONO 0x0100 | |
241 | ||
242 | /* | |
243 | * R770 (0x302) - AIF1 Master/Slave | |
244 | */ | |
245 | /* AIF1_MSTR */ | |
246 | #define WM8994_AIF1_MSTR 0x4000 | |
247 | #define WM8994_AIF1_MSTR_MASK 0x4000 | |
248 | ||
249 | /* | |
250 | * R771 (0x303) - AIF1 BCLK | |
251 | */ | |
252 | /* AIF1_BCLK_DIV - [8:4] */ | |
253 | #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 | |
254 | #define WM8994_AIF1_BCLK_DIV_SHIFT 4 | |
255 | ||
256 | /* | |
257 | * R1282 (0x502) - AIF2 DAC Left Volume | |
258 | */ | |
259 | /* AIF2DAC_VU */ | |
260 | #define WM8994_AIF2DAC_VU 0x0100 | |
261 | #define WM8994_AIF2DAC_VU_MASK 0x0100 | |
262 | /* AIF2DACL_VOL - [7:0] */ | |
263 | #define WM8994_AIF2DACL_VOL_MASK 0x00FF | |
264 | ||
265 | /* | |
266 | * R1283 (0x503) - AIF2 DAC Right Volume | |
267 | */ | |
268 | /* AIF2DACR_VOL - [7:0] */ | |
269 | #define WM8994_AIF2DACR_VOL_MASK 0x00FF | |
270 | ||
271 | /* | |
272 | * R1312 (0x520) - AIF2 DAC Filters (1) | |
273 | */ | |
274 | /* AIF2DAC_MUTE */ | |
275 | #define WM8994_AIF2DAC_MUTE_MASK 0x0200 | |
276 | ||
277 | /* | |
278 | * R1537 (0x601) - DAC1 Left Mixer Routing | |
279 | */ | |
280 | /* AIF2DACL_TO_DAC1L */ | |
281 | #define WM8994_AIF2DACL_TO_DAC1L 0x0004 | |
282 | #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 | |
d981d80d DKM |
283 | /* AIF1DAC1L_TO_DAC1L */ |
284 | #define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 | |
a2d8e0a7 RS |
285 | |
286 | /* | |
287 | * R1538 (0x602) - DAC1 Right Mixer Routing | |
288 | */ | |
289 | /* AIF2DACR_TO_DAC1R */ | |
290 | #define WM8994_AIF2DACR_TO_DAC1R 0x0004 | |
291 | #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 | |
d981d80d DKM |
292 | /* AIF1DAC1R_TO_DAC1R */ |
293 | #define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 | |
a2d8e0a7 RS |
294 | |
295 | /* | |
296 | * R1552 (0x610) - DAC1 Left Volume | |
297 | */ | |
298 | /* DAC1L_MUTE */ | |
299 | #define WM8994_DAC1L_MUTE_MASK 0x0200 | |
300 | /* DAC1_VU */ | |
301 | #define WM8994_DAC1_VU 0x0100 | |
302 | #define WM8994_DAC1_VU_MASK 0x0100 | |
303 | /* DAC1L_VOL - [7:0] */ | |
304 | #define WM8994_DAC1L_VOL_MASK 0x00FF | |
305 | ||
306 | /* | |
307 | * R1553 (0x611) - DAC1 Right Volume | |
308 | */ | |
309 | /* DAC1R_MUTE */ | |
310 | #define WM8994_DAC1R_MUTE_MASK 0x0200 | |
311 | /* DAC1R_VOL - [7:0] */ | |
312 | #define WM8994_DAC1R_VOL_MASK 0x00FF | |
313 | ||
314 | /* | |
315 | * GPIO | |
316 | */ | |
317 | /* OUTPUT PIN */ | |
d981d80d | 318 | #define WM8994_GPIO_DIR_OUTPUT 0x8000 |
a2d8e0a7 | 319 | /* GPIO PIN MASK */ |
d981d80d | 320 | #define WM8994_GPIO_DIR_MASK 0xFFE0 |
a2d8e0a7 | 321 | /* I2S CLK */ |
d981d80d DKM |
322 | #define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001 |
323 | #define WM8994_GPIO_INPUT_DEBOUNCE 0x0100 | |
a2d8e0a7 | 324 | /* GPn FN */ |
d981d80d | 325 | #define WM8994_GPIO_FUNCTION_MASK 0x001F |
a2d8e0a7 | 326 | #endif |