]>
Commit | Line | Data |
---|---|---|
fefb6c10 SP |
1 | /* |
2 | * Driver for ATMEL DataFlash support | |
3 | * Author : Hamid Ikdoumi (Atmel) | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
fefb6c10 SP |
6 | */ |
7 | ||
0c427914 RM |
8 | /* |
9 | * This driver desperately needs rework: | |
10 | * | |
11 | * - use structure SoC access | |
12 | * - get rid of including asm/arch/at91_spi.h | |
13 | * - remove asm/arch/at91_spi.h | |
14 | * - get rid of all CONFIG_ATMEL_LEGACY defines and uses | |
15 | * | |
16 | * 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de> | |
17 | */ | |
18 | ||
fefb6c10 | 19 | #include <common.h> |
0c427914 RM |
20 | #ifndef CONFIG_ATMEL_LEGACY |
21 | # define CONFIG_ATMEL_LEGACY | |
0cf0b931 | 22 | #endif |
a0cfd188 RM |
23 | #include <spi.h> |
24 | #include <malloc.h> | |
25 | ||
26 | #include <asm/io.h> | |
27 | ||
dc39ae95 | 28 | #include <asm/arch/clk.h> |
a0cfd188 RM |
29 | #include <asm/arch/hardware.h> |
30 | ||
31 | #include "atmel_spi.h" | |
32 | ||
983c1db0 | 33 | #include <asm/arch/gpio.h> |
983c1db0 SP |
34 | #include <asm/arch/at91_pio.h> |
35 | #include <asm/arch/at91_spi.h> | |
fefb6c10 | 36 | |
fefb6c10 SP |
37 | #include <dataflash.h> |
38 | ||
983c1db0 | 39 | #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */ |
41dfd8a6 RB |
40 | #define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */ |
41 | #define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */ | |
983c1db0 | 42 | #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */ |
fefb6c10 SP |
43 | |
44 | void AT91F_SpiInit(void) | |
45 | { | |
46 | /* Reset the SPI */ | |
a0cfd188 | 47 | writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
fefb6c10 SP |
48 | |
49 | /* Configure SPI in Master Mode with No CS selected !!! */ | |
983c1db0 | 50 | writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, |
a0cfd188 | 51 | ATMEL_BASE_SPI0 + AT91_SPI_MR); |
fefb6c10 SP |
52 | |
53 | /* Configure CS0 */ | |
983c1db0 SP |
54 | writel(AT91_SPI_NCPHA | |
55 | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | | |
56 | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | | |
dc39ae95 | 57 | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
a0cfd188 | 58 | ATMEL_BASE_SPI0 + AT91_SPI_CSR(0)); |
983c1db0 | 59 | |
6d0f6bcf | 60 | #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 |
983c1db0 SP |
61 | /* Configure CS1 */ |
62 | writel(AT91_SPI_NCPHA | | |
63 | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | | |
64 | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | | |
dc39ae95 | 65 | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
a0cfd188 | 66 | ATMEL_BASE_SPI0 + AT91_SPI_CSR(1)); |
983c1db0 | 67 | #endif |
41dfd8a6 RB |
68 | #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 |
69 | /* Configure CS2 */ | |
70 | writel(AT91_SPI_NCPHA | | |
71 | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | | |
72 | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | | |
73 | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), | |
a0cfd188 | 74 | ATMEL_BASE_SPI0 + AT91_SPI_CSR(2)); |
41dfd8a6 | 75 | #endif |
6d0f6bcf | 76 | #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 |
983c1db0 SP |
77 | /* Configure CS3 */ |
78 | writel(AT91_SPI_NCPHA | | |
79 | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | | |
80 | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | | |
dc39ae95 | 81 | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), |
a0cfd188 | 82 | ATMEL_BASE_SPI0 + AT91_SPI_CSR(3)); |
983c1db0 SP |
83 | #endif |
84 | ||
85 | /* SPI_Enable */ | |
a0cfd188 | 86 | writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
983c1db0 | 87 | |
a0cfd188 RM |
88 | while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS)) |
89 | ; | |
983c1db0 SP |
90 | |
91 | /* | |
92 | * Add tempo to get SPI in a safe state. | |
93 | * Should not be needed for new silicon (Rev B) | |
94 | */ | |
95 | udelay(500000); | |
a0cfd188 RM |
96 | readl(ATMEL_BASE_SPI0 + AT91_SPI_SR); |
97 | readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR); | |
983c1db0 | 98 | |
fefb6c10 SP |
99 | } |
100 | ||
101 | void AT91F_SpiEnable(int cs) | |
102 | { | |
983c1db0 | 103 | unsigned long mode; |
1762f13b | 104 | |
7dfc4dbd AL |
105 | mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR); |
106 | mode &= ~AT91_SPI_PCS; | |
107 | ||
fefb6c10 | 108 | switch (cs) { |
7dfc4dbd AL |
109 | case 0: |
110 | mode |= AT91_SPI_PCS0_DATAFLASH_CARD << 16; | |
983c1db0 | 111 | break; |
7dfc4dbd AL |
112 | case 1: |
113 | mode |= AT91_SPI_PCS1_DATAFLASH_CARD << 16; | |
fefb6c10 | 114 | break; |
7dfc4dbd AL |
115 | case 2: |
116 | mode |= AT91_SPI_PCS2_DATAFLASH_CARD << 16; | |
41dfd8a6 | 117 | break; |
fefb6c10 | 118 | case 3: |
7dfc4dbd | 119 | mode |= AT91_SPI_PCS3_DATAFLASH_CARD << 16; |
fefb6c10 SP |
120 | break; |
121 | } | |
122 | ||
7dfc4dbd AL |
123 | writel(mode, ATMEL_BASE_SPI0 + AT91_SPI_MR); |
124 | ||
fefb6c10 | 125 | /* SPI_Enable */ |
a0cfd188 | 126 | writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR); |
fefb6c10 SP |
127 | } |
128 | ||
983c1db0 SP |
129 | unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc); |
130 | ||
fefb6c10 SP |
131 | unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) |
132 | { | |
133 | unsigned int timeout; | |
a0cfd188 | 134 | unsigned int timebase; |
fefb6c10 SP |
135 | |
136 | pDesc->state = BUSY; | |
137 | ||
a0cfd188 RM |
138 | writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, |
139 | ATMEL_BASE_SPI0 + AT91_SPI_PTCR); | |
983c1db0 | 140 | |
fefb6c10 | 141 | /* Initialize the Transmit and Receive Pointer */ |
a0cfd188 RM |
142 | writel((unsigned int)pDesc->rx_cmd_pt, |
143 | ATMEL_BASE_SPI0 + AT91_SPI_RPR); | |
144 | writel((unsigned int)pDesc->tx_cmd_pt, | |
145 | ATMEL_BASE_SPI0 + AT91_SPI_TPR); | |
fefb6c10 SP |
146 | |
147 | /* Intialize the Transmit and Receive Counters */ | |
a0cfd188 RM |
148 | writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR); |
149 | writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR); | |
fefb6c10 SP |
150 | |
151 | if (pDesc->tx_data_size != 0) { | |
152 | /* Initialize the Next Transmit and Next Receive Pointer */ | |
a0cfd188 RM |
153 | writel((unsigned int)pDesc->rx_data_pt, |
154 | ATMEL_BASE_SPI0 + AT91_SPI_RNPR); | |
155 | writel((unsigned int)pDesc->tx_data_pt, | |
156 | ATMEL_BASE_SPI0 + AT91_SPI_TNPR); | |
fefb6c10 SP |
157 | |
158 | /* Intialize the Next Transmit and Next Receive Counters */ | |
a0cfd188 RM |
159 | writel(pDesc->rx_data_size, |
160 | ATMEL_BASE_SPI0 + AT91_SPI_RNCR); | |
161 | writel(pDesc->tx_data_size, | |
162 | ATMEL_BASE_SPI0 + AT91_SPI_TNCR); | |
fefb6c10 SP |
163 | } |
164 | ||
165 | /* arm simple, non interrupt dependent timer */ | |
a0cfd188 | 166 | timebase = get_timer(0); |
fefb6c10 SP |
167 | timeout = 0; |
168 | ||
a0cfd188 RM |
169 | writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, |
170 | ATMEL_BASE_SPI0 + AT91_SPI_PTCR); | |
171 | while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) && | |
172 | ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT)) | |
173 | ; | |
174 | writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, | |
175 | ATMEL_BASE_SPI0 + AT91_SPI_PTCR); | |
fefb6c10 SP |
176 | pDesc->state = IDLE; |
177 | ||
6d0f6bcf | 178 | if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) { |
fefb6c10 SP |
179 | printf("Error Timeout\n\r"); |
180 | return DATAFLASH_ERROR; | |
181 | } | |
182 | ||
183 | return DATAFLASH_OK; | |
184 | } |