[people/ms/u-boot.git] / drivers / spi / cadence_qspi.h

/*
 * Copyright (C) 2012
 * Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CADENCE_QSPI_H__
#define __CADENCE_QSPI_H__

#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)

#define CQSPI_NO_DECODER_MAX_CS		4
#define CQSPI_DECODER_MAX_CS		16
#define CQSPI_READ_CAPTURE_MAX_DELAY	16

struct cadence_spi_platdata {
	unsigned int	max_hz;
	void		*regbase;
	void		*ahbbase;
	bool		is_decoded_cs;
	u32		fifo_depth;
	u32		fifo_width;
	u32		trigger_address;

	/* Flash parameters */
	u32		page_size;
	u32		block_size;
	u32		tshsl_ns;
	u32		tsd2d_ns;
	u32		tchsh_ns;
	u32		tslch_ns;
};

struct cadence_spi_priv {
	void		*regbase;
	void		*ahbbase;
	size_t		cmd_len;
	u8		cmd_buf[32];
	size_t		data_len;

	int		qspi_is_init;
	unsigned int	qspi_calibrated_hz;
	unsigned int	qspi_calibrated_cs;
	unsigned int	previous_hz;
};

/* Functions call declaration */
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);

int cadence_qspi_apb_command_read(void *reg_base_addr,
	unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_command_write(void *reg_base_addr,
	unsigned int cmdlen, const u8 *cmdbuf,
	unsigned int txlen,  const u8 *txbuf);

int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
	unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
	unsigned int rxlen, u8 *rxbuf);
int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
	unsigned int cmdlen, const u8 *cmdbuf);
int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
	unsigned int txlen, const u8 *txbuf);

void cadence_qspi_apb_chipselect(void *reg_base,
	unsigned int chip_select, unsigned int decoder_enable);
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
void cadence_qspi_apb_config_baudrate_div(void *reg_base,
	unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base,
	unsigned int ref_clk, unsigned int sclk_hz,
	unsigned int tshsl_ns, unsigned int tsd2d_ns,
	unsigned int tchsh_ns, unsigned int tslch_ns);
void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
void cadence_qspi_apb_readdata_capture(void *reg_base,
	unsigned int bypass, unsigned int delay);

#endif /* __CADENCE_QSPI_H__ */
Commit	Line	Data
10e8bf88 SR	1	/*
	2	* Copyright (C) 2012
	3	* Altera Corporation <www.altera.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __CADENCE_QSPI_H__
	9	#define __CADENCE_QSPI_H__
	10
	11	#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
	12
	13	#define CQSPI_NO_DECODER_MAX_CS 4
	14	#define CQSPI_DECODER_MAX_CS 16
	15	#define CQSPI_READ_CAPTURE_MAX_DELAY 16
	16
	17	struct cadence_spi_platdata {
	18	unsigned int max_hz;
	19	void *regbase;
	20	void *ahbbase;
15a70a5d JR	21	bool is_decoded_cs;
	22	u32 fifo_depth;
	23	u32 fifo_width;
	24	u32 trigger_address;
10e8bf88	25
15a70a5d	26	/* Flash parameters */
10e8bf88 SR	27	u32 page_size;
	28	u32 block_size;
	29	u32 tshsl_ns;
	30	u32 tsd2d_ns;
	31	u32 tchsh_ns;
	32	u32 tslch_ns;
	33	};
	34
	35	struct cadence_spi_priv {
	36	void *regbase;
	37	void *ahbbase;
	38	size_t cmd_len;
	39	u8 cmd_buf[32];
	40	size_t data_len;
	41
	42	int qspi_is_init;
	43	unsigned int qspi_calibrated_hz;
	44	unsigned int qspi_calibrated_cs;
98fbd71d	45	unsigned int previous_hz;
10e8bf88 SR	46	};
	47
	48	/* Functions call declaration */
	49	void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
	50	void cadence_qspi_apb_controller_enable(void *reg_base_addr);
	51	void cadence_qspi_apb_controller_disable(void *reg_base_addr);
	52
	53	int cadence_qspi_apb_command_read(void *reg_base_addr,
	54	unsigned int cmdlen, const u8 cmdbuf, unsigned int rxlen, u8 rxbuf);
	55	int cadence_qspi_apb_command_write(void *reg_base_addr,
	56	unsigned int cmdlen, const u8 *cmdbuf,
	57	unsigned int txlen, const u8 *txbuf);
	58
	59	int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
2372e14f	60	unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf);
10e8bf88 SR	61	int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
	62	unsigned int rxlen, u8 *rxbuf);
	63	int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
	64	unsigned int cmdlen, const u8 *cmdbuf);
	65	int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
	66	unsigned int txlen, const u8 *txbuf);
	67
	68	void cadence_qspi_apb_chipselect(void *reg_base,
	69	unsigned int chip_select, unsigned int decoder_enable);
7d403f28	70	void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
10e8bf88 SR	71	void cadence_qspi_apb_config_baudrate_div(void *reg_base,
	72	unsigned int ref_clk_hz, unsigned int sclk_hz);
	73	void cadence_qspi_apb_delay(void *reg_base,
	74	unsigned int ref_clk, unsigned int sclk_hz,
	75	unsigned int tshsl_ns, unsigned int tsd2d_ns,
	76	unsigned int tchsh_ns, unsigned int tslch_ns);
	77	void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
	78	void cadence_qspi_apb_readdata_capture(void *reg_base,
	79	unsigned int bypass, unsigned int delay);
	80
	81	#endif /* __CADENCE_QSPI_H__ */