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8ed58856 SN |
1 | /* |
2 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Driver for SPI controller on DaVinci. Based on atmel_spi.c | |
5 | * by Atmel Corporation | |
6 | * | |
7 | * Copyright (C) 2007 Atmel Corporation | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
8ed58856 SN |
10 | */ |
11 | #include <common.h> | |
12 | #include <spi.h> | |
13 | #include <malloc.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/arch/hardware.h> | |
16 | #include "davinci_spi.h" | |
17 | ||
18 | void spi_init() | |
19 | { | |
20 | /* do nothing */ | |
21 | } | |
22 | ||
23 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | |
24 | unsigned int max_hz, unsigned int mode) | |
25 | { | |
26 | struct davinci_spi_slave *ds; | |
27 | ||
28 | if (!spi_cs_is_valid(bus, cs)) | |
29 | return NULL; | |
30 | ||
d3504fee | 31 | ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); |
8ed58856 SN |
32 | if (!ds) |
33 | return NULL; | |
34 | ||
8ed58856 SN |
35 | ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; |
36 | ds->freq = max_hz; | |
37 | ||
38 | return &ds->slave; | |
39 | } | |
40 | ||
41 | void spi_free_slave(struct spi_slave *slave) | |
42 | { | |
43 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
44 | ||
45 | free(ds); | |
46 | } | |
47 | ||
48 | int spi_claim_bus(struct spi_slave *slave) | |
49 | { | |
50 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
77436d66 | 51 | unsigned int scalar; |
8ed58856 SN |
52 | |
53 | /* Enable the SPI hardware */ | |
54 | writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); | |
55 | udelay(1000); | |
56 | writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); | |
57 | ||
58 | /* Set master mode, powered up and not activated */ | |
59 | writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); | |
60 | ||
61 | /* CS, CLK, SIMO and SOMI are functional pins */ | |
62 | writel((SPIPC0_EN0FUN_MASK | SPIPC0_CLKFUN_MASK | | |
63 | SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); | |
64 | ||
65 | /* setup format */ | |
66 | scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; | |
67 | ||
68 | /* | |
69 | * Use following format: | |
70 | * character length = 8, | |
71 | * clock signal delayed by half clk cycle, | |
72 | * clock low in idle state - Mode 0, | |
73 | * MSB shifted out first | |
74 | */ | |
75 | writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | | |
76 | (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); | |
77 | ||
8ed58856 SN |
78 | /* |
79 | * Including a minor delay. No science here. Should be good even with | |
80 | * no delay | |
81 | */ | |
82 | writel((50 << SPI_C2TDELAY_SHIFT) | | |
83 | (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); | |
84 | ||
85 | /* default chip select register */ | |
86 | writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); | |
87 | ||
88 | /* no interrupts */ | |
89 | writel(0, &ds->regs->int0); | |
90 | writel(0, &ds->regs->lvl); | |
91 | ||
92 | /* enable SPI */ | |
77436d66 | 93 | writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); |
8ed58856 SN |
94 | |
95 | return 0; | |
96 | } | |
97 | ||
98 | void spi_release_bus(struct spi_slave *slave) | |
99 | { | |
100 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
101 | ||
102 | /* Disable the SPI hardware */ | |
103 | writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); | |
104 | } | |
105 | ||
77436d66 NT |
106 | /* |
107 | * This functions needs to act like a macro to avoid pipeline reloads in the | |
108 | * loops below. Use always_inline. This gains us about 160KiB/s and the bloat | |
109 | * appears to be zero bytes (da830). | |
110 | */ | |
111 | __attribute__((always_inline)) | |
112 | static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data) | |
113 | { | |
114 | u32 buf_reg_val; | |
115 | ||
116 | /* send out data */ | |
117 | writel(data, &ds->regs->dat1); | |
118 | ||
119 | /* wait for the data to clock in/out */ | |
120 | while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK) | |
121 | ; | |
122 | ||
123 | return buf_reg_val; | |
124 | } | |
125 | ||
126 | static int davinci_spi_read(struct spi_slave *slave, unsigned int len, | |
127 | u8 *rxp, unsigned long flags) | |
128 | { | |
129 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
130 | unsigned int data1_reg_val; | |
131 | ||
132 | /* enable CS hold, CS[n] and clear the data bits */ | |
133 | data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | | |
134 | (slave->cs << SPIDAT1_CSNR_SHIFT)); | |
135 | ||
136 | /* wait till TXFULL is deasserted */ | |
137 | while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) | |
138 | ; | |
139 | ||
140 | /* preload the TX buffer to avoid clock starvation */ | |
141 | writel(data1_reg_val, &ds->regs->dat1); | |
142 | ||
143 | /* keep reading 1 byte until only 1 byte left */ | |
144 | while ((len--) > 1) | |
145 | *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val); | |
146 | ||
147 | /* clear CS hold when we reach the end */ | |
148 | if (flags & SPI_XFER_END) | |
149 | data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); | |
150 | ||
151 | /* read the last byte */ | |
152 | *rxp = davinci_spi_xfer_data(ds, data1_reg_val); | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | static int davinci_spi_write(struct spi_slave *slave, unsigned int len, | |
dce6538f | 158 | const u8 *txp, unsigned long flags) |
77436d66 NT |
159 | { |
160 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
161 | unsigned int data1_reg_val; | |
162 | ||
163 | /* enable CS hold and clear the data bits */ | |
164 | data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | | |
165 | (slave->cs << SPIDAT1_CSNR_SHIFT)); | |
166 | ||
167 | /* wait till TXFULL is deasserted */ | |
168 | while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) | |
169 | ; | |
170 | ||
171 | /* preload the TX buffer to avoid clock starvation */ | |
172 | if (len > 2) { | |
173 | writel(data1_reg_val | *txp++, &ds->regs->dat1); | |
174 | len--; | |
175 | } | |
176 | ||
177 | /* keep writing 1 byte until only 1 byte left */ | |
178 | while ((len--) > 1) | |
179 | davinci_spi_xfer_data(ds, data1_reg_val | *txp++); | |
180 | ||
181 | /* clear CS hold when we reach the end */ | |
182 | if (flags & SPI_XFER_END) | |
183 | data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); | |
184 | ||
185 | /* write the last byte */ | |
186 | davinci_spi_xfer_data(ds, data1_reg_val | *txp); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | #ifndef CONFIG_SPI_HALF_DUPLEX | |
192 | static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, | |
193 | u8 *rxp, const u8 *txp, unsigned long flags) | |
194 | { | |
195 | struct davinci_spi_slave *ds = to_davinci_spi(slave); | |
196 | unsigned int data1_reg_val; | |
197 | ||
198 | /* enable CS hold and clear the data bits */ | |
199 | data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | | |
200 | (slave->cs << SPIDAT1_CSNR_SHIFT)); | |
201 | ||
202 | /* wait till TXFULL is deasserted */ | |
203 | while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) | |
204 | ; | |
205 | ||
206 | /* keep reading and writing 1 byte until only 1 byte left */ | |
207 | while ((len--) > 1) | |
208 | *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++); | |
209 | ||
210 | /* clear CS hold when we reach the end */ | |
211 | if (flags & SPI_XFER_END) | |
212 | data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT); | |
213 | ||
214 | /* read and write the last byte */ | |
215 | *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | #endif | |
220 | ||
8ed58856 | 221 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
dce6538f | 222 | const void *dout, void *din, unsigned long flags) |
8ed58856 | 223 | { |
77436d66 | 224 | unsigned int len; |
8ed58856 | 225 | |
8ed58856 SN |
226 | if (bitlen == 0) |
227 | /* Finish any previously submitted transfers */ | |
228 | goto out; | |
229 | ||
230 | /* | |
231 | * It's not clear how non-8-bit-aligned transfers are supposed to be | |
232 | * represented as a stream of bytes...this is a limitation of | |
233 | * the current SPI interface - here we terminate on receiving such a | |
234 | * transfer request. | |
235 | */ | |
236 | if (bitlen % 8) { | |
237 | /* Errors always terminate an ongoing transfer */ | |
238 | flags |= SPI_XFER_END; | |
239 | goto out; | |
240 | } | |
241 | ||
242 | len = bitlen / 8; | |
243 | ||
77436d66 NT |
244 | if (!dout) |
245 | return davinci_spi_read(slave, len, din, flags); | |
246 | else if (!din) | |
247 | return davinci_spi_write(slave, len, dout, flags); | |
248 | #ifndef CONFIG_SPI_HALF_DUPLEX | |
249 | else | |
250 | return davinci_spi_read_write(slave, len, din, dout, flags); | |
dce6538f NT |
251 | #else |
252 | printf("SPI full duplex transaction requested with " | |
253 | "CONFIG_SPI_HALF_DUPLEX defined.\n"); | |
254 | flags |= SPI_XFER_END; | |
77436d66 | 255 | #endif |
8ed58856 SN |
256 | |
257 | out: | |
258 | if (flags & SPI_XFER_END) { | |
77436d66 NT |
259 | u8 dummy = 0; |
260 | davinci_spi_write(slave, 1, &dummy, flags); | |
8ed58856 SN |
261 | } |
262 | return 0; | |
263 | } | |
264 | ||
265 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
266 | { | |
267 | return bus == 0 && cs == 0; | |
268 | } | |
269 | ||
270 | void spi_cs_activate(struct spi_slave *slave) | |
271 | { | |
272 | /* do nothing */ | |
273 | } | |
274 | ||
275 | void spi_cs_deactivate(struct spi_slave *slave) | |
276 | { | |
277 | /* do nothing */ | |
278 | } |