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1bf43b82 RS |
1 | /* |
2 | * (C) Copyright 2012 SAMSUNG Electronics | |
3 | * Padmavathi Venna <padma.v@samsung.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
1bf43b82 RS |
6 | */ |
7 | ||
8 | #include <common.h> | |
73186c94 SG |
9 | #include <dm.h> |
10 | #include <errno.h> | |
1bf43b82 RS |
11 | #include <malloc.h> |
12 | #include <spi.h> | |
4d3acb9d | 13 | #include <fdtdec.h> |
1bf43b82 RS |
14 | #include <asm/arch/clk.h> |
15 | #include <asm/arch/clock.h> | |
16 | #include <asm/arch/cpu.h> | |
17 | #include <asm/arch/gpio.h> | |
18 | #include <asm/arch/pinmux.h> | |
19 | #include <asm/arch-exynos/spi.h> | |
20 | #include <asm/io.h> | |
21 | ||
4d3acb9d RS |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
73186c94 | 24 | struct exynos_spi_platdata { |
1bf43b82 RS |
25 | enum periph_id periph_id; |
26 | s32 frequency; /* Default clock frequency, -1 for none */ | |
27 | struct exynos_spi *regs; | |
8d203afd | 28 | uint deactivate_delay_us; /* Delay to wait after deactivate */ |
1bf43b82 RS |
29 | }; |
30 | ||
73186c94 | 31 | struct exynos_spi_priv { |
1bf43b82 RS |
32 | struct exynos_spi *regs; |
33 | unsigned int freq; /* Default frequency */ | |
34 | unsigned int mode; | |
35 | enum periph_id periph_id; /* Peripheral ID for this device */ | |
36 | unsigned int fifo_size; | |
e4eaef89 | 37 | int skip_preamble; |
8d203afd | 38 | ulong last_transaction_us; /* Time of last transaction end */ |
1bf43b82 RS |
39 | }; |
40 | ||
1bf43b82 RS |
41 | /** |
42 | * Flush spi tx, rx fifos and reset the SPI controller | |
43 | * | |
73186c94 | 44 | * @param regs Pointer to SPI registers |
1bf43b82 | 45 | */ |
73186c94 | 46 | static void spi_flush_fifo(struct exynos_spi *regs) |
1bf43b82 | 47 | { |
1bf43b82 RS |
48 | clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); |
49 | clrbits_le32(®s->ch_cfg, SPI_CH_RST); | |
50 | setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); | |
51 | } | |
52 | ||
1bf43b82 RS |
53 | static void spi_get_fifo_levels(struct exynos_spi *regs, |
54 | int *rx_lvl, int *tx_lvl) | |
55 | { | |
56 | uint32_t spi_sts = readl(®s->spi_sts); | |
57 | ||
58 | *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; | |
59 | *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; | |
60 | } | |
61 | ||
62 | /** | |
63 | * If there's something to transfer, do a software reset and set a | |
64 | * transaction size. | |
65 | * | |
66 | * @param regs SPI peripheral registers | |
67 | * @param count Number of bytes to transfer | |
c4a79632 | 68 | * @param step Number of bytes to transfer in each packet (1 or 4) |
1bf43b82 | 69 | */ |
c4a79632 | 70 | static void spi_request_bytes(struct exynos_spi *regs, int count, int step) |
1bf43b82 | 71 | { |
73186c94 SG |
72 | debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step); |
73 | ||
c4a79632 RS |
74 | /* For word address we need to swap bytes */ |
75 | if (step == 4) { | |
76 | setbits_le32(®s->mode_cfg, | |
77 | SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); | |
78 | count /= 4; | |
79 | setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | | |
80 | SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | | |
81 | SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); | |
82 | } else { | |
83 | /* Select byte access and clear the swap configuration */ | |
84 | clrbits_le32(®s->mode_cfg, | |
85 | SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); | |
86 | writel(0, ®s->swap_cfg); | |
87 | } | |
88 | ||
1bf43b82 RS |
89 | assert(count && count < (1 << 16)); |
90 | setbits_le32(®s->ch_cfg, SPI_CH_RST); | |
91 | clrbits_le32(®s->ch_cfg, SPI_CH_RST); | |
c4a79632 | 92 | |
1bf43b82 RS |
93 | writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt); |
94 | } | |
95 | ||
73186c94 | 96 | static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, |
e4eaef89 | 97 | void **dinp, void const **doutp, unsigned long flags) |
1bf43b82 | 98 | { |
73186c94 | 99 | struct exynos_spi *regs = priv->regs; |
1bf43b82 RS |
100 | uchar *rxp = *dinp; |
101 | const uchar *txp = *doutp; | |
102 | int rx_lvl, tx_lvl; | |
103 | uint out_bytes, in_bytes; | |
e4eaef89 RS |
104 | int toread; |
105 | unsigned start = get_timer(0); | |
106 | int stopping; | |
c4a79632 | 107 | int step; |
1bf43b82 RS |
108 | |
109 | out_bytes = in_bytes = todo; | |
110 | ||
73186c94 SG |
111 | stopping = priv->skip_preamble && (flags & SPI_XFER_END) && |
112 | !(priv->mode & SPI_SLAVE); | |
e4eaef89 | 113 | |
c4a79632 RS |
114 | /* |
115 | * Try to transfer words if we can. This helps read performance at | |
116 | * SPI clock speeds above about 20MHz. | |
117 | */ | |
118 | step = 1; | |
119 | if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) && | |
73186c94 | 120 | !priv->skip_preamble) |
c4a79632 RS |
121 | step = 4; |
122 | ||
1bf43b82 RS |
123 | /* |
124 | * If there's something to send, do a software reset and set a | |
125 | * transaction size. | |
126 | */ | |
c4a79632 | 127 | spi_request_bytes(regs, todo, step); |
1bf43b82 RS |
128 | |
129 | /* | |
130 | * Bytes are transmitted/received in pairs. Wait to receive all the | |
131 | * data because then transmission will be done as well. | |
132 | */ | |
e4eaef89 RS |
133 | toread = in_bytes; |
134 | ||
1bf43b82 RS |
135 | while (in_bytes) { |
136 | int temp; | |
137 | ||
138 | /* Keep the fifos full/empty. */ | |
139 | spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl); | |
c4a79632 RS |
140 | |
141 | /* | |
142 | * Don't completely fill the txfifo, since we don't want our | |
143 | * rxfifo to overflow, and it may already contain data. | |
144 | */ | |
73186c94 | 145 | while (tx_lvl < priv->fifo_size/2 && out_bytes) { |
c4a79632 RS |
146 | if (!txp) |
147 | temp = -1; | |
148 | else if (step == 4) | |
149 | temp = *(uint32_t *)txp; | |
150 | else | |
151 | temp = *txp; | |
1bf43b82 | 152 | writel(temp, ®s->tx_data); |
c4a79632 RS |
153 | out_bytes -= step; |
154 | if (txp) | |
155 | txp += step; | |
156 | tx_lvl += step; | |
1bf43b82 | 157 | } |
c4a79632 RS |
158 | if (rx_lvl >= step) { |
159 | while (rx_lvl >= step) { | |
120af157 | 160 | temp = readl(®s->rx_data); |
73186c94 | 161 | if (priv->skip_preamble) { |
120af157 | 162 | if (temp == SPI_PREAMBLE_END_BYTE) { |
73186c94 | 163 | priv->skip_preamble = 0; |
120af157 RS |
164 | stopping = 0; |
165 | } | |
166 | } else { | |
c4a79632 | 167 | if (rxp || stopping) { |
e76d2a81 AS |
168 | if (step == 4) |
169 | *(uint32_t *)rxp = temp; | |
170 | else | |
171 | *rxp = temp; | |
c4a79632 RS |
172 | rxp += step; |
173 | } | |
174 | in_bytes -= step; | |
e4eaef89 | 175 | } |
c4a79632 RS |
176 | toread -= step; |
177 | rx_lvl -= step; | |
178 | } | |
e4eaef89 RS |
179 | } else if (!toread) { |
180 | /* | |
181 | * We have run out of input data, but haven't read | |
182 | * enough bytes after the preamble yet. Read some more, | |
183 | * and make sure that we transmit dummy bytes too, to | |
184 | * keep things going. | |
185 | */ | |
186 | assert(!out_bytes); | |
187 | out_bytes = in_bytes; | |
188 | toread = in_bytes; | |
189 | txp = NULL; | |
c4a79632 | 190 | spi_request_bytes(regs, toread, step); |
e4eaef89 | 191 | } |
73186c94 | 192 | if (priv->skip_preamble && get_timer(start) > 100) { |
e4eaef89 RS |
193 | printf("SPI timeout: in_bytes=%d, out_bytes=%d, ", |
194 | in_bytes, out_bytes); | |
195 | return -1; | |
1bf43b82 RS |
196 | } |
197 | } | |
e4eaef89 | 198 | |
1bf43b82 RS |
199 | *dinp = rxp; |
200 | *doutp = txp; | |
e4eaef89 RS |
201 | |
202 | return 0; | |
1bf43b82 RS |
203 | } |
204 | ||
1bf43b82 RS |
205 | /** |
206 | * Activate the CS by driving it LOW | |
207 | * | |
208 | * @param slave Pointer to spi_slave to which controller has to | |
209 | * communicate with | |
210 | */ | |
73186c94 | 211 | static void spi_cs_activate(struct udevice *dev) |
1bf43b82 | 212 | { |
73186c94 SG |
213 | struct udevice *bus = dev->parent; |
214 | struct exynos_spi_platdata *pdata = dev_get_platdata(bus); | |
215 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
1bf43b82 | 216 | |
8d203afd | 217 | /* If it's too soon to do another transaction, wait */ |
73186c94 SG |
218 | if (pdata->deactivate_delay_us && |
219 | priv->last_transaction_us) { | |
8d203afd | 220 | ulong delay_us; /* The delay completed so far */ |
73186c94 SG |
221 | delay_us = timer_get_us() - priv->last_transaction_us; |
222 | if (delay_us < pdata->deactivate_delay_us) | |
223 | udelay(pdata->deactivate_delay_us - delay_us); | |
8d203afd RS |
224 | } |
225 | ||
73186c94 SG |
226 | clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); |
227 | debug("Activate CS, bus '%s'\n", bus->name); | |
228 | priv->skip_preamble = priv->mode & SPI_PREAMBLE; | |
1bf43b82 RS |
229 | } |
230 | ||
231 | /** | |
232 | * Deactivate the CS by driving it HIGH | |
233 | * | |
234 | * @param slave Pointer to spi_slave to which controller has to | |
235 | * communicate with | |
236 | */ | |
73186c94 | 237 | static void spi_cs_deactivate(struct udevice *dev) |
1bf43b82 | 238 | { |
73186c94 SG |
239 | struct udevice *bus = dev->parent; |
240 | struct exynos_spi_platdata *pdata = dev_get_platdata(bus); | |
241 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
1bf43b82 | 242 | |
73186c94 | 243 | setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT); |
a4e29db2 SG |
244 | |
245 | /* Remember time of this transaction so we can honour the bus delay */ | |
73186c94 SG |
246 | if (pdata->deactivate_delay_us) |
247 | priv->last_transaction_us = timer_get_us(); | |
a4e29db2 | 248 | |
73186c94 | 249 | debug("Deactivate CS, bus '%s'\n", bus->name); |
1bf43b82 RS |
250 | } |
251 | ||
73186c94 | 252 | static int exynos_spi_ofdata_to_platdata(struct udevice *bus) |
1bf43b82 | 253 | { |
73186c94 SG |
254 | struct exynos_spi_platdata *plat = bus->platdata; |
255 | const void *blob = gd->fdt_blob; | |
256 | int node = bus->of_offset; | |
1bf43b82 | 257 | |
73186c94 SG |
258 | plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg"); |
259 | plat->periph_id = pinmux_decode_periph_id(blob, node); | |
4d3acb9d | 260 | |
73186c94 | 261 | if (plat->periph_id == PERIPH_ID_NONE) { |
4d3acb9d | 262 | debug("%s: Invalid peripheral ID %d\n", __func__, |
73186c94 | 263 | plat->periph_id); |
4d3acb9d RS |
264 | return -FDT_ERR_NOTFOUND; |
265 | } | |
266 | ||
267 | /* Use 500KHz as a suitable default */ | |
73186c94 | 268 | plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", |
4d3acb9d | 269 | 500000); |
73186c94 | 270 | plat->deactivate_delay_us = fdtdec_get_int(blob, node, |
8d203afd | 271 | "spi-deactivate-delay", 0); |
73186c94 SG |
272 | debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", |
273 | __func__, plat->regs, plat->periph_id, plat->frequency, | |
274 | plat->deactivate_delay_us); | |
4d3acb9d RS |
275 | |
276 | return 0; | |
277 | } | |
278 | ||
73186c94 | 279 | static int exynos_spi_probe(struct udevice *bus) |
4d3acb9d | 280 | { |
73186c94 SG |
281 | struct exynos_spi_platdata *plat = dev_get_platdata(bus); |
282 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
4d3acb9d | 283 | |
73186c94 SG |
284 | priv->regs = plat->regs; |
285 | if (plat->periph_id == PERIPH_ID_SPI1 || | |
286 | plat->periph_id == PERIPH_ID_SPI2) | |
287 | priv->fifo_size = 64; | |
288 | else | |
289 | priv->fifo_size = 256; | |
4d3acb9d | 290 | |
73186c94 SG |
291 | priv->skip_preamble = 0; |
292 | priv->last_transaction_us = timer_get_us(); | |
293 | priv->freq = plat->frequency; | |
294 | priv->periph_id = plat->periph_id; | |
4d3acb9d | 295 | |
73186c94 SG |
296 | return 0; |
297 | } | |
4d3acb9d | 298 | |
73186c94 SG |
299 | static int exynos_spi_claim_bus(struct udevice *bus) |
300 | { | |
301 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
302 | ||
303 | exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE); | |
304 | spi_flush_fifo(priv->regs); | |
305 | ||
306 | writel(SPI_FB_DELAY_180, &priv->regs->fb_clk); | |
4d3acb9d RS |
307 | |
308 | return 0; | |
309 | } | |
310 | ||
73186c94 | 311 | static int exynos_spi_release_bus(struct udevice *bus) |
f3424c55 | 312 | { |
73186c94 SG |
313 | struct exynos_spi_priv *priv = dev_get_priv(bus); |
314 | ||
315 | spi_flush_fifo(priv->regs); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen, | |
321 | const void *dout, void *din, unsigned long flags) | |
322 | { | |
323 | struct udevice *bus = dev->parent; | |
324 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
325 | int upto, todo; | |
326 | int bytelen; | |
327 | int ret = 0; | |
328 | ||
329 | /* spi core configured to do 8 bit transfers */ | |
330 | if (bitlen % 8) { | |
331 | debug("Non byte aligned SPI transfer.\n"); | |
332 | return -1; | |
333 | } | |
334 | ||
335 | /* Start the transaction, if necessary. */ | |
336 | if ((flags & SPI_XFER_BEGIN)) | |
337 | spi_cs_activate(dev); | |
338 | ||
339 | /* | |
340 | * Exynos SPI limits each transfer to 65535 transfers. To keep | |
341 | * things simple, allow a maximum of 65532 bytes. We could allow | |
342 | * more in word mode, but the performance difference is small. | |
343 | */ | |
344 | bytelen = bitlen / 8; | |
345 | for (upto = 0; !ret && upto < bytelen; upto += todo) { | |
346 | todo = min(bytelen - upto, (1 << 16) - 4); | |
347 | ret = spi_rx_tx(priv, todo, &din, &dout, flags); | |
348 | if (ret) | |
349 | break; | |
350 | } | |
f3424c55 | 351 | |
73186c94 SG |
352 | /* Stop the transaction, if necessary. */ |
353 | if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) { | |
354 | spi_cs_deactivate(dev); | |
355 | if (priv->skip_preamble) { | |
356 | assert(!priv->skip_preamble); | |
357 | debug("Failed to complete premable transaction\n"); | |
358 | ret = -1; | |
359 | } | |
f3424c55 HT |
360 | } |
361 | ||
73186c94 | 362 | return ret; |
f3424c55 HT |
363 | } |
364 | ||
73186c94 | 365 | static int exynos_spi_set_speed(struct udevice *bus, uint speed) |
1bf43b82 | 366 | { |
73186c94 SG |
367 | struct exynos_spi_platdata *plat = bus->platdata; |
368 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
369 | int ret; | |
4d3acb9d | 370 | |
73186c94 SG |
371 | if (speed > plat->frequency) |
372 | speed = plat->frequency; | |
373 | ret = set_spi_clk(priv->periph_id, speed); | |
374 | if (ret) | |
375 | return ret; | |
376 | priv->freq = speed; | |
377 | debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); | |
378 | ||
379 | return 0; | |
380 | } | |
4d3acb9d | 381 | |
73186c94 SG |
382 | static int exynos_spi_set_mode(struct udevice *bus, uint mode) |
383 | { | |
384 | struct exynos_spi_priv *priv = dev_get_priv(bus); | |
385 | uint32_t reg; | |
4d3acb9d | 386 | |
73186c94 SG |
387 | reg = readl(&priv->regs->ch_cfg); |
388 | reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L); | |
1bf43b82 | 389 | |
73186c94 SG |
390 | if (mode & SPI_CPHA) |
391 | reg |= SPI_CH_CPHA_B; | |
1bf43b82 | 392 | |
73186c94 SG |
393 | if (mode & SPI_CPOL) |
394 | reg |= SPI_CH_CPOL_L; | |
395 | ||
396 | writel(reg, &priv->regs->ch_cfg); | |
397 | priv->mode = mode; | |
398 | debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); | |
399 | ||
400 | return 0; | |
1bf43b82 | 401 | } |
73186c94 SG |
402 | |
403 | static const struct dm_spi_ops exynos_spi_ops = { | |
404 | .claim_bus = exynos_spi_claim_bus, | |
405 | .release_bus = exynos_spi_release_bus, | |
406 | .xfer = exynos_spi_xfer, | |
407 | .set_speed = exynos_spi_set_speed, | |
408 | .set_mode = exynos_spi_set_mode, | |
409 | /* | |
410 | * cs_info is not needed, since we require all chip selects to be | |
411 | * in the device tree explicitly | |
412 | */ | |
413 | }; | |
414 | ||
415 | static const struct udevice_id exynos_spi_ids[] = { | |
416 | { .compatible = "samsung,exynos-spi" }, | |
417 | { } | |
418 | }; | |
419 | ||
420 | U_BOOT_DRIVER(exynos_spi) = { | |
421 | .name = "exynos_spi", | |
422 | .id = UCLASS_SPI, | |
423 | .of_match = exynos_spi_ids, | |
424 | .ops = &exynos_spi_ops, | |
425 | .ofdata_to_platdata = exynos_spi_ofdata_to_platdata, | |
426 | .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata), | |
427 | .priv_auto_alloc_size = sizeof(struct exynos_spi_priv), | |
428 | .per_child_auto_alloc_size = sizeof(struct spi_slave), | |
429 | .probe = exynos_spi_probe, | |
430 | }; |