[thirdparty/u-boot.git] / drivers / spi / fsl_dspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 * Chao Fu (B44548@freescale.com)
 * Haikun Wang (B53464@freescale.com)
 */

#include <asm/global_data.h>
#include <linux/math64.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <spi.h>
#include <malloc.h>
#include <asm/io.h>
#include <fdtdec.h>
#ifndef CONFIG_M68K
#include <asm/arch/clock.h>
#endif
#include <fsl_dspi.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>
#include <linux/time.h>

DECLARE_GLOBAL_DATA_PTR;

/* fsl_dspi_plat flags */
#define DSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)

/* idle data value */
#define DSPI_IDLE_VAL			0x0

/* max chipselect signals number */
#define FSL_DSPI_MAX_CHIPSELECT		6

/* default SCK frequency, unit: HZ */
#define FSL_DSPI_DEFAULT_SCK_FREQ	10000000

/* tx/rx data wait timeout value, unit: us */
#define DSPI_TXRX_WAIT_TIMEOUT		1000000

/* CTAR register pre-configure value */
#define DSPI_CTAR_DEFAULT_VALUE		(DSPI_CTAR_TRSZ(7) | \
					DSPI_CTAR_PCSSCK_1CLK | \
					DSPI_CTAR_PASC(0) | \
					DSPI_CTAR_PDT(0) | \
					DSPI_CTAR_CSSCK(0) | \
					DSPI_CTAR_ASC(0) | \
					DSPI_CTAR_DT(0))

/* CTAR register pre-configure mask */
#define DSPI_CTAR_SET_MODE_MASK		(DSPI_CTAR_TRSZ(15) | \
					DSPI_CTAR_PCSSCK(3) | \
					DSPI_CTAR_PASC(3) | \
					DSPI_CTAR_PDT(3) | \
					DSPI_CTAR_CSSCK(15) | \
					DSPI_CTAR_ASC(15) | \
					DSPI_CTAR_DT(15))

/**
 * struct fsl_dspi_plat - platform data for Freescale DSPI
 *
 * @flags: Flags for DSPI DSPI_FLAG_...
 * @speed_hz: Default SCK frequency
 * @num_chipselect: Number of DSPI chipselect signals
 * @regs_addr: Base address of DSPI registers
 */
struct fsl_dspi_plat {
	uint flags;
	uint speed_hz;
	uint num_chipselect;
	fdt_addr_t regs_addr;
};

/**
 * struct fsl_dspi_priv - private data for Freescale DSPI
 *
 * @flags: Flags for DSPI DSPI_FLAG_...
 * @mode: SPI mode to use for slave device (see SPI mode flags)
 * @mcr_val: MCR register configure value
 * @bus_clk: DSPI input clk frequency
 * @speed_hz: Default SCK frequency
 * @charbit: How many bits in every transfer
 * @num_chipselect: Number of DSPI chipselect signals
 * @ctar_val: CTAR register configure value of per chipselect slave device
 * @regs: Point to DSPI register structure for I/O access
 */
struct fsl_dspi_priv {
	uint flags;
	uint mode;
	uint mcr_val;
	uint bus_clk;
	uint speed_hz;
	uint charbit;
	uint num_chipselect;
	uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
	struct dspi *regs;
};

__weak void cpu_dspi_port_conf(void)
{
}

__weak int cpu_dspi_claim_bus(uint bus, uint cs)
{
	return 0;
}

__weak void cpu_dspi_release_bus(uint bus, uint cs)
{
}

static uint dspi_read32(uint flags, uint *addr)
{
	return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
		in_be32(addr) : in_le32(addr);
}

static void dspi_write32(uint flags, uint *addr, uint val)
{
	flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
		out_be32(addr, val) : out_le32(addr, val);
}

static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
{
	uint mcr_val;

	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);

	if (halt)
		mcr_val |= DSPI_MCR_HALT;
	else
		mcr_val &= ~DSPI_MCR_HALT;

	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
}

static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
{
	/* halt DSPI module */
	dspi_halt(priv, 1);

	dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);

	/* resume module */
	dspi_halt(priv, 0);

	priv->mcr_val = cfg_val;
}

static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
		uint cs, uint state)
{
	uint mcr_val;

	dspi_halt(priv, 1);

	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
	if (state & SPI_CS_HIGH)
		/* CSx inactive state is low */
		mcr_val &= ~DSPI_MCR_PCSIS(cs);
	else
		/* CSx inactive state is high */
		mcr_val |= DSPI_MCR_PCSIS(cs);
	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);

	dspi_halt(priv, 0);
}

static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
		uint cs, uint mode)
{
	uint bus_setup;

	bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);

	bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
	bus_setup |= priv->ctar_val[cs];
	bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);

	if (mode & SPI_CPOL)
		bus_setup |= DSPI_CTAR_CPOL;
	if (mode & SPI_CPHA)
		bus_setup |= DSPI_CTAR_CPHA;
	if (mode & SPI_LSB_FIRST)
		bus_setup |= DSPI_CTAR_LSBFE;

	dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);

	priv->charbit =
		((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
		  DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;

	return 0;
}

static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
{
	uint mcr_val;

	dspi_halt(priv, 1);
	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
	/* flush RX and TX FIFO */
	mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
	dspi_halt(priv, 0);
}

static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
{
	int timeout = DSPI_TXRX_WAIT_TIMEOUT;

	/* wait for empty entries in TXFIFO or timeout */
	while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
			timeout--)
		udelay(1);

	if (timeout >= 0)
		dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
	else
		debug("dspi_tx: waiting timeout!\n");
}

static u16 dspi_rx(struct fsl_dspi_priv *priv)
{
	int timeout = DSPI_TXRX_WAIT_TIMEOUT;

	/* wait for valid entries in RXFIFO or timeout */
	while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
			timeout--)
		udelay(1);

	if (timeout >= 0)
		return (u16)DSPI_RFR_RXDATA(
				dspi_read32(priv->flags, &priv->regs->rfr));
	else {
		debug("dspi_rx: waiting timeout!\n");
		return (u16)(~0);
	}
}

static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
	u8 *spi_rd = NULL, *spi_wr = NULL;
	static u32 ctrl;
	uint len = bitlen >> 3;

	if (priv->charbit == 16) {
		bitlen >>= 1;
		spi_wr16 = (u16 *)dout;
		spi_rd16 = (u16 *)din;
	} else {
		spi_wr = (u8 *)dout;
		spi_rd = (u8 *)din;
	}

	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
		ctrl |= DSPI_TFR_CONT;

	ctrl = ctrl & DSPI_TFR_CONT;
	ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);

	if (len > 1) {
		int tmp_len = len - 1;
		while (tmp_len--) {
			if ((dout != NULL) && (din != NULL)) {
				if (priv->charbit == 16) {
					dspi_tx(priv, ctrl, *spi_wr16++);
					*spi_rd16++ = dspi_rx(priv);
				}
				else {
					dspi_tx(priv, ctrl, *spi_wr++);
					*spi_rd++ = dspi_rx(priv);
				}
			}

			else if (dout != NULL) {
				if (priv->charbit == 16)
					dspi_tx(priv, ctrl, *spi_wr16++);
				else
					dspi_tx(priv, ctrl, *spi_wr++);
				dspi_rx(priv);
			}

			else if (din != NULL) {
				dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
				if (priv->charbit == 16)
					*spi_rd16++ = dspi_rx(priv);
				else
					*spi_rd++ = dspi_rx(priv);
			}
		}

		len = 1;	/* remaining byte */
	}

	if ((flags & SPI_XFER_END) == SPI_XFER_END)
		ctrl &= ~DSPI_TFR_CONT;

	if (len) {
		if ((dout != NULL) && (din != NULL)) {
			if (priv->charbit == 16) {
				dspi_tx(priv, ctrl, *spi_wr16++);
				*spi_rd16++ = dspi_rx(priv);
			}
			else {
				dspi_tx(priv, ctrl, *spi_wr++);
				*spi_rd++ = dspi_rx(priv);
			}
		}

		else if (dout != NULL) {
			if (priv->charbit == 16)
				dspi_tx(priv, ctrl, *spi_wr16);
			else
				dspi_tx(priv, ctrl, *spi_wr);
			dspi_rx(priv);
		}

		else if (din != NULL) {
			dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
			if (priv->charbit == 16)
				*spi_rd16 = dspi_rx(priv);
			else
				*spi_rd = dspi_rx(priv);
		}
	} else {
		/* dummy read */
		dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
		dspi_rx(priv);
	}

	return 0;
}

/**
 * Calculate the divide value between input clk frequency and expected SCK frequency
 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
 * Dbr: use default value 0
 *
 * @pbr: return Baud Rate Prescaler value
 * @br: return Baud Rate Scaler value
 * @speed_hz: expected SCK frequency
 * @clkrate: input clk frequency
 */
static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
		int speed_hz, uint clkrate)
{
	/* Valid baud rate pre-scaler values */
	int pbr_tbl[4] = {2, 3, 5, 7};
	int brs[16] = {2, 4, 6, 8,
		16, 32, 64, 128,
		256, 512, 1024, 2048,
		4096, 8192, 16384, 32768};
	int temp, i = 0, j = 0;

	temp = clkrate / speed_hz;

	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
		for (j = 0; j < ARRAY_SIZE(brs); j++) {
			if (pbr_tbl[i] * brs[j] >= temp) {
				*pbr = i;
				*br = j;
				return 0;
			}
		}

	debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
	debug("clkrate is %d, we use the max prescaler value.\n", clkrate);

	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	*br =  ARRAY_SIZE(brs) - 1;
	return -EINVAL;
}

static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
			   unsigned long clkrate)
{
	int scale_needed, scale, minscale = INT_MAX;
	int pscale_tbl[4] = {1, 3, 5, 7};
	u32 remainder;
	int i, j;

	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
				   &remainder);
	if (remainder)
		scale_needed++;

	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
		for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
			scale = pscale_tbl[i] * (2 << j);
			if (scale >= scale_needed) {
				if (scale < minscale) {
					minscale = scale;
					*psc = i;
					*sc = j;
				}
				break;
			}
		}

	if (minscale == INT_MAX) {
		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
			delay_ns, clkrate);
		*psc = ARRAY_SIZE(pscale_tbl) - 1;
		*sc = DSPI_CTAR_SCALE_BITS;
	}
}

static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
{
	int ret;
	uint bus_setup;
	int best_i, best_j, bus_clk;

	bus_clk = priv->bus_clk;

	debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
	      speed, bus_clk);

	bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
	bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));

	ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
	if (ret) {
		speed = priv->speed_hz;
		debug("DSPI set_speed use default SCK rate %u.\n", speed);
		fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
	}

	bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
	dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);

	priv->speed_hz = speed;

	return 0;
}

static int fsl_dspi_child_pre_probe(struct udevice *dev)
{
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
	u32 cs_sck_delay = 0, sck_cs_delay = 0;
	unsigned char pcssck = 0, cssck = 0;
	unsigned char pasc = 0, asc = 0;

	if (slave_plat->cs >= priv->num_chipselect) {
		debug("DSPI invalid chipselect number %d(max %d)!\n",
		      slave_plat->cs, priv->num_chipselect - 1);
		return -EINVAL;
	}

	ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
			&cs_sck_delay);
	ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
			&sck_cs_delay);

	/* Set PCS to SCK delay scale values */
	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);

	/* Set After SCK delay scale values */
	ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);

	priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
					 DSPI_CTAR_PCSSCK(pcssck) |
					 DSPI_CTAR_PASC(pasc);

	debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
	      slave_plat->cs, slave_plat->max_hz, slave_plat->mode);

	return 0;
}

static int fsl_dspi_probe(struct udevice *bus)
{
	struct fsl_dspi_plat *plat = dev_get_plat(bus);
	struct fsl_dspi_priv *priv = dev_get_priv(bus);
	struct dm_spi_bus *dm_spi_bus;
	uint mcr_cfg_val;

	dm_spi_bus = dev_get_uclass_priv(bus);

	/* cpu special pin muxing configure */
	cpu_dspi_port_conf();

	/* get input clk frequency */
	priv->regs = (struct dspi *)plat->regs_addr;
	priv->flags = plat->flags;
#ifdef CONFIG_M68K
	priv->bus_clk = gd->bus_clk;
#else
	priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
#endif
	priv->num_chipselect = plat->num_chipselect;
	priv->speed_hz = plat->speed_hz;
	/* frame data length in bits, default 8bits */
	priv->charbit = 8;

	dm_spi_bus->max_hz = plat->speed_hz;

	/* default: all CS signals inactive state is high */
	mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
		DSPI_MCR_CRXF | DSPI_MCR_CTXF;
	fsl_dspi_init_mcr(priv, mcr_cfg_val);

	debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));

	return 0;
}

static int fsl_dspi_claim_bus(struct udevice *dev)
{
	uint sr_val;
	struct fsl_dspi_priv *priv;
	struct udevice *bus = dev->parent;
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	priv = dev_get_priv(bus);

	/* processor special preparation work */
	cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);

	/* configure transfer mode */
	fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);

	/* configure active state of CSX */
	fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
				     priv->mode);

	fsl_dspi_clr_fifo(priv);

	/* check module TX and RX status */
	sr_val = dspi_read32(priv->flags, &priv->regs->sr);
	if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
		debug("DSPI RX/TX not ready!\n");
		return -EIO;
	}

	return 0;
}

static int fsl_dspi_release_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct fsl_dspi_priv *priv = dev_get_priv(bus);
	struct dm_spi_slave_plat *slave_plat =
		dev_get_parent_plat(dev);

	/* halt module */
	dspi_halt(priv, 1);

	/* processor special release work */
	cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);

	return 0;
}

/**
 * This function doesn't do anything except help with debugging
 */
static int fsl_dspi_bind(struct udevice *bus)
{
	debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
	return 0;
}

static int fsl_dspi_of_to_plat(struct udevice *bus)
{
	fdt_addr_t addr;
	struct fsl_dspi_plat *plat = dev_get_plat(bus);
	const void *blob = gd->fdt_blob;
	int node = dev_of_offset(bus);

	if (fdtdec_get_bool(blob, node, "big-endian"))
		plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;

	plat->num_chipselect = fdtdec_get_int(blob, node,
					      "spi-num-chipselects",
					      FSL_DSPI_MAX_CHIPSELECT);

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE) {
		debug("DSPI: Can't get base address or size\n");
		return -ENOMEM;
	}
	plat->regs_addr = addr;

	plat->speed_hz = fdtdec_get_int(blob,
			node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);

	debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n",
	      &plat->regs_addr, plat->speed_hz,
	      plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
	      plat->num_chipselect);

	return 0;
}

static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
		const void *dout, void *din, unsigned long flags)
{
	struct fsl_dspi_priv *priv;
	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
	struct udevice *bus;

	bus = dev->parent;
	priv = dev_get_priv(bus);

	return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
}

static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
{
	struct fsl_dspi_priv *priv = dev_get_priv(bus);

	return fsl_dspi_cfg_speed(priv, speed);
}

static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
{
	struct fsl_dspi_priv *priv = dev_get_priv(bus);

	debug("DSPI set_mode: mode 0x%x.\n", mode);

	/*
	 * We store some chipselect special configure value in priv->ctar_val,
	 * and we can't get the correct chipselect number here,
	 * so just store mode value.
	 * Do really configuration when claim_bus.
	 */
	priv->mode = mode;

	return 0;
}

static const struct dm_spi_ops fsl_dspi_ops = {
	.claim_bus	= fsl_dspi_claim_bus,
	.release_bus	= fsl_dspi_release_bus,
	.xfer		= fsl_dspi_xfer,
	.set_speed	= fsl_dspi_set_speed,
	.set_mode	= fsl_dspi_set_mode,
};

static const struct udevice_id fsl_dspi_ids[] = {
	{ .compatible = "fsl,vf610-dspi" },
	{ .compatible = "fsl,ls1021a-v1.0-dspi" },
	{ }
};

U_BOOT_DRIVER(fsl_dspi) = {
	.name	= "fsl_dspi",
	.id	= UCLASS_SPI,
	.of_match = fsl_dspi_ids,
	.ops	= &fsl_dspi_ops,
	.of_to_plat = fsl_dspi_of_to_plat,
	.plat_auto	= sizeof(struct fsl_dspi_plat),
	.priv_auto	= sizeof(struct fsl_dspi_priv),
	.probe	= fsl_dspi_probe,
	.child_pre_probe = fsl_dspi_child_pre_probe,
	.bind = fsl_dspi_bind,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a8919371 HW	2	/*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
	6	* Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	* Chao Fu (B44548@freescale.com)
	9	* Haikun Wang (B53464@freescale.com)
a8919371	10	*/
4af0d7e8	11
401d1c4f	12	#include <asm/global_data.h>
e7005b3e	13	#include <linux/math64.h>
4af0d7e8	14	#include <common.h>
a8919371 HW	15	#include <dm.h>
a8919371 HW	16	#include <errno.h>
f7ae49fc	17	#include <log.h>
a8919371 HW	18	#include <spi.h>
	19	#include <malloc.h>
	20	#include <asm/io.h>
	21	#include <fdtdec.h>
	22	#ifndef CONFIG_M68K
	23	#include <asm/arch/clock.h>
	24	#endif
	25	#include <fsl_dspi.h>
cd93d625	26	#include <linux/bitops.h>
c05ed00a	27	#include <linux/delay.h>
1e94b46f	28	#include <linux/printk.h>
13248d66	29	#include <linux/time.h>
e7005b3e	30
a8919371 HW	31	DECLARE_GLOBAL_DATA_PTR;
a8919371 HW	32
8a8d24bd	33	/* fsl_dspi_plat flags */
29e6abd9	34	#define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
a8919371 HW	35
	36	/* idle data value */
	37	#define DSPI_IDLE_VAL 0x0
	38
	39	/* max chipselect signals number */
	40	#define FSL_DSPI_MAX_CHIPSELECT 6
	41
	42	/* default SCK frequency, unit: HZ */
	43	#define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
	44
	45	/* tx/rx data wait timeout value, unit: us */
	46	#define DSPI_TXRX_WAIT_TIMEOUT 1000000
	47
	48	/* CTAR register pre-configure value */
	49	#define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) \| \
	50	DSPI_CTAR_PCSSCK_1CLK \| \
	51	DSPI_CTAR_PASC(0) \| \
	52	DSPI_CTAR_PDT(0) \| \
	53	DSPI_CTAR_CSSCK(0) \| \
	54	DSPI_CTAR_ASC(0) \| \
	55	DSPI_CTAR_DT(0))
	56
	57	/* CTAR register pre-configure mask */
	58	#define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) \| \
	59	DSPI_CTAR_PCSSCK(3) \| \
	60	DSPI_CTAR_PASC(3) \| \
	61	DSPI_CTAR_PDT(3) \| \
	62	DSPI_CTAR_CSSCK(15) \| \
	63	DSPI_CTAR_ASC(15) \| \
	64	DSPI_CTAR_DT(15))
	65
	66	/**
8a8d24bd	67	* struct fsl_dspi_plat - platform data for Freescale DSPI
a8919371 HW	68	*
	69	* @flags: Flags for DSPI DSPI_FLAG_...
	70	* @speed_hz: Default SCK frequency
	71	* @num_chipselect: Number of DSPI chipselect signals
	72	* @regs_addr: Base address of DSPI registers
	73	*/
8a8d24bd	74	struct fsl_dspi_plat {
a8919371 HW	75	uint flags;
	76	uint speed_hz;
	77	uint num_chipselect;
	78	fdt_addr_t regs_addr;
	79	};
	80
	81	/**
	82	* struct fsl_dspi_priv - private data for Freescale DSPI
	83	*
	84	* @flags: Flags for DSPI DSPI_FLAG_...
	85	* @mode: SPI mode to use for slave device (see SPI mode flags)
	86	* @mcr_val: MCR register configure value
	87	* @bus_clk: DSPI input clk frequency
	88	* @speed_hz: Default SCK frequency
	89	* @charbit: How many bits in every transfer
	90	* @num_chipselect: Number of DSPI chipselect signals
	91	* @ctar_val: CTAR register configure value of per chipselect slave device
	92	* @regs: Point to DSPI register structure for I/O access
	93	*/
	94	struct fsl_dspi_priv {
	95	uint flags;
	96	uint mode;
	97	uint mcr_val;
	98	uint bus_clk;
	99	uint speed_hz;
	100	uint charbit;
	101	uint num_chipselect;
	102	uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
	103	struct dspi *regs;
	104	};
	105
a8919371 HW	106	__weak void cpu_dspi_port_conf(void)
	107	{
	108	}
	109
	110	__weak int cpu_dspi_claim_bus(uint bus, uint cs)
	111	{
	112	return 0;
	113	}
	114
	115	__weak void cpu_dspi_release_bus(uint bus, uint cs)
	116	{
	117	}
	118
	119	static uint dspi_read32(uint flags, uint *addr)
	120	{
	121	return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
	122	in_be32(addr) : in_le32(addr);
	123	}
	124
	125	static void dspi_write32(uint flags, uint *addr, uint val)
	126	{
	127	flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
	128	out_be32(addr, val) : out_le32(addr, val);
	129	}
	130
	131	static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
	132	{
	133	uint mcr_val;
	134
	135	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
	136
	137	if (halt)
	138	mcr_val \|= DSPI_MCR_HALT;
	139	else
	140	mcr_val &= ~DSPI_MCR_HALT;
	141
	142	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
	143	}
	144
	145	static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
	146	{
	147	/* halt DSPI module */
	148	dspi_halt(priv, 1);
	149
	150	dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
	151
	152	/* resume module */
	153	dspi_halt(priv, 0);
	154
	155	priv->mcr_val = cfg_val;
	156	}
	157
	158	static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
	159	uint cs, uint state)
	160	{
	161	uint mcr_val;
	162
	163	dspi_halt(priv, 1);
	164
	165	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
	166	if (state & SPI_CS_HIGH)
	167	/* CSx inactive state is low */
	168	mcr_val &= ~DSPI_MCR_PCSIS(cs);
	169	else
170	/* CSx inactive state is high */
171	mcr_val \|= DSPI_MCR_PCSIS(cs);
172	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
173
174	dspi_halt(priv, 0);
175	}
176
177	static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
178	uint cs, uint mode)
179	{
180	uint bus_setup;
181
182	bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
183
184	bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
185	bus_setup \|= priv->ctar_val[cs];
186	bus_setup &= ~(DSPI_CTAR_CPOL \| DSPI_CTAR_CPHA \| DSPI_CTAR_LSBFE);
187
188	if (mode & SPI_CPOL)
189	bus_setup \|= DSPI_CTAR_CPOL;
190	if (mode & SPI_CPHA)
191	bus_setup \|= DSPI_CTAR_CPHA;
192	if (mode & SPI_LSB_FIRST)
193	bus_setup \|= DSPI_CTAR_LSBFE;
194
195	dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
196
197	priv->charbit =
198	((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
199	DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
200
201	return 0;
202	}
203
204	static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
205	{
206	uint mcr_val;
207
208	dspi_halt(priv, 1);
209	mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
210	/* flush RX and TX FIFO */
211	mcr_val \|= (DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
212	dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
213	dspi_halt(priv, 0);
214	}
215
216	static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
217	{
218	int timeout = DSPI_TXRX_WAIT_TIMEOUT;
219
220	/* wait for empty entries in TXFIFO or timeout */
221	while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
222	timeout--)
223	udelay(1);
224
225	if (timeout >= 0)
226	dspi_write32(priv->flags, &priv->regs->tfr, (ctrl \| data));
227	else
228	debug("dspi_tx: waiting timeout!\n");
229	}
230
231	static u16 dspi_rx(struct fsl_dspi_priv *priv)
232	{
233	int timeout = DSPI_TXRX_WAIT_TIMEOUT;
234
235	/* wait for valid entries in RXFIFO or timeout */
236	while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
237	timeout--)
238	udelay(1);
239
240	if (timeout >= 0)
241	return (u16)DSPI_RFR_RXDATA(
242	dspi_read32(priv->flags, &priv->regs->rfr));
243	else {
244	debug("dspi_rx: waiting timeout!\n");
245	return (u16)(~0);
246	}
247	}
248
249	static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
250	const void dout, void din, unsigned long flags)
251	{
252	u16 spi_rd16 = NULL, spi_wr16 = NULL;
253	u8 spi_rd = NULL, spi_wr = NULL;
254	static u32 ctrl;
255	uint len = bitlen >> 3;
256
257	if (priv->charbit == 16) {
258	bitlen >>= 1;
259	spi_wr16 = (u16 *)dout;
260	spi_rd16 = (u16 *)din;
261	} else {
262	spi_wr = (u8 *)dout;
263	spi_rd = (u8 *)din;
264	}
265
266	if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
267	ctrl \|= DSPI_TFR_CONT;
268
269	ctrl = ctrl & DSPI_TFR_CONT;
270	ctrl = ctrl \| DSPI_TFR_CTAS(0) \| DSPI_TFR_PCS(cs);
271
272	if (len > 1) {
273	int tmp_len = len - 1;
274	while (tmp_len--) {
40264c0c JB	275	if ((dout != NULL) && (din != NULL)) {
	276	if (priv->charbit == 16) {
	277	dspi_tx(priv, ctrl, *spi_wr16++);
	278	*spi_rd16++ = dspi_rx(priv);
	279	}
	280	else {
	281	dspi_tx(priv, ctrl, *spi_wr++);
	282	*spi_rd++ = dspi_rx(priv);
	283	}
	284	}
	285
	286	else if (dout != NULL) {
a8919371 HW	287	if (priv->charbit == 16)
	288	dspi_tx(priv, ctrl, *spi_wr16++);
	289	else
	290	dspi_tx(priv, ctrl, *spi_wr++);
	291	dspi_rx(priv);
	292	}
	293
40264c0c	294	else if (din != NULL) {
a8919371 HW	295	dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
	296	if (priv->charbit == 16)
	297	*spi_rd16++ = dspi_rx(priv);
	298	else
	299	*spi_rd++ = dspi_rx(priv);
	300	}
	301	}
	302
	303	len = 1; /* remaining byte */
	304	}
	305
	306	if ((flags & SPI_XFER_END) == SPI_XFER_END)
	307	ctrl &= ~DSPI_TFR_CONT;
	308
	309	if (len) {
40264c0c JB	310	if ((dout != NULL) && (din != NULL)) {
	311	if (priv->charbit == 16) {
	312	dspi_tx(priv, ctrl, *spi_wr16++);
	313	*spi_rd16++ = dspi_rx(priv);
	314	}
	315	else {
	316	dspi_tx(priv, ctrl, *spi_wr++);
	317	*spi_rd++ = dspi_rx(priv);
	318	}
	319	}
	320
	321	else if (dout != NULL) {
a8919371 HW	322	if (priv->charbit == 16)
	323	dspi_tx(priv, ctrl, *spi_wr16);
	324	else
	325	dspi_tx(priv, ctrl, *spi_wr);
	326	dspi_rx(priv);
	327	}
	328
40264c0c	329	else if (din != NULL) {
a8919371 HW	330	dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
	331	if (priv->charbit == 16)
	332	*spi_rd16 = dspi_rx(priv);
	333	else
	334	*spi_rd = dspi_rx(priv);
	335	}
	336	} else {
	337	/* dummy read */
	338	dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
	339	dspi_rx(priv);
	340	}
	341
	342	return 0;
	343	}
	344
	345	/**
	346	* Calculate the divide value between input clk frequency and expected SCK frequency
	347	* Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
	348	* Dbr: use default value 0
	349	*
	350	* @pbr: return Baud Rate Prescaler value
	351	* @br: return Baud Rate Scaler value
	352	* @speed_hz: expected SCK frequency
	353	* @clkrate: input clk frequency
	354	*/
	355	static int fsl_dspi_hz_to_spi_baud(int pbr, int br,
	356	int speed_hz, uint clkrate)
	357	{
	358	/* Valid baud rate pre-scaler values */
	359	int pbr_tbl[4] = {2, 3, 5, 7};
	360	int brs[16] = {2, 4, 6, 8,
	361	16, 32, 64, 128,
	362	256, 512, 1024, 2048,
	363	4096, 8192, 16384, 32768};
	364	int temp, i = 0, j = 0;
	365
	366	temp = clkrate / speed_hz;
	367
	368	for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
	369	for (j = 0; j < ARRAY_SIZE(brs); j++) {
	370	if (pbr_tbl[i] * brs[j] >= temp) {
	371	*pbr = i;
	372	*br = j;
	373	return 0;
	374	}
	375	}
	376
	377	debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
	378	debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
	379
	380	*pbr = ARRAY_SIZE(pbr_tbl) - 1;
	381	*br = ARRAY_SIZE(brs) - 1;
	382	return -EINVAL;
	383	}
	384
e7005b3e VO	385	static void ns_delay_scale(unsigned char psc, unsigned char sc, int delay_ns,
	386	unsigned long clkrate)
	387	{
	388	int scale_needed, scale, minscale = INT_MAX;
	389	int pscale_tbl[4] = {1, 3, 5, 7};
	390	u32 remainder;
	391	int i, j;
	392
	393	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
	394	&remainder);
	395	if (remainder)
	396	scale_needed++;
	397
	398	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
	399	for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
	400	scale = pscale_tbl[i] * (2 << j);
	401	if (scale >= scale_needed) {
	402	if (scale < minscale) {
	403	minscale = scale;
	404	*psc = i;
	405	*sc = j;
	406	}
	407	break;
	408	}
	409	}
	410
	411	if (minscale == INT_MAX) {
	412	pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
	413	delay_ns, clkrate);
	414	*psc = ARRAY_SIZE(pscale_tbl) - 1;
	415	*sc = DSPI_CTAR_SCALE_BITS;
	416	}
	417	}
	418
a8919371 HW	419	static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
	420	{
	421	int ret;
	422	uint bus_setup;
	423	int best_i, best_j, bus_clk;
	424
	425	bus_clk = priv->bus_clk;
	426
	427	debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
	428	speed, bus_clk);
	429
	430	bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
	431	bus_setup &= ~(DSPI_CTAR_DBR \| DSPI_CTAR_PBR(0x3) \| DSPI_CTAR_BR(0xf));
	432
	433	ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
	434	if (ret) {
	435	speed = priv->speed_hz;
	436	debug("DSPI set_speed use default SCK rate %u.\n", speed);
	437	fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
	438	}
	439
	440	bus_setup \|= (DSPI_CTAR_PBR(best_i) \| DSPI_CTAR_BR(best_j));
	441	dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
	442
	443	priv->speed_hz = speed;
	444
	445	return 0;
	446	}
a8919371	447
a8919371 HW	448	static int fsl_dspi_child_pre_probe(struct udevice *dev)
a8919371 HW	449	{
8a8d24bd	450	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
a8919371	451	struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
e7005b3e VO	452	u32 cs_sck_delay = 0, sck_cs_delay = 0;
	453	unsigned char pcssck = 0, cssck = 0;
	454	unsigned char pasc = 0, asc = 0;
a8919371 HW	455
	456	if (slave_plat->cs >= priv->num_chipselect) {
	457	debug("DSPI invalid chipselect number %d(max %d)!\n",
	458	slave_plat->cs, priv->num_chipselect - 1);
	459	return -EINVAL;
	460	}
	461
f10643cf SG	462	ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
	463	&cs_sck_delay);
	464	ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
	465	&sck_cs_delay);
e7005b3e VO	466
	467	/* Set PCS to SCK delay scale values */
	468	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
	469
	470	/* Set After SCK delay scale values */
	471	ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
	472
	473	priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE \|
	474	DSPI_CTAR_PCSSCK(pcssck) \|
	475	DSPI_CTAR_PASC(pasc);
a8919371 HW	476
	477	debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
	478	slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
	479
	480	return 0;
	481	}
	482
	483	static int fsl_dspi_probe(struct udevice *bus)
	484	{
8a8d24bd	485	struct fsl_dspi_plat *plat = dev_get_plat(bus);
a8919371 HW	486	struct fsl_dspi_priv *priv = dev_get_priv(bus);
	487	struct dm_spi_bus *dm_spi_bus;
	488	uint mcr_cfg_val;
	489
0fd3d911	490	dm_spi_bus = dev_get_uclass_priv(bus);
a8919371	491
d466f620	492	/* cpu special pin muxing configure */
a8919371 HW	493	cpu_dspi_port_conf();
	494
	495	/* get input clk frequency */
	496	priv->regs = (struct dspi *)plat->regs_addr;
	497	priv->flags = plat->flags;
	498	#ifdef CONFIG_M68K
	499	priv->bus_clk = gd->bus_clk;
	500	#else
	501	priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
	502	#endif
	503	priv->num_chipselect = plat->num_chipselect;
	504	priv->speed_hz = plat->speed_hz;
	505	/* frame data length in bits, default 8bits */
	506	priv->charbit = 8;
	507
	508	dm_spi_bus->max_hz = plat->speed_hz;
	509
	510	/* default: all CS signals inactive state is high */
	511	mcr_cfg_val = DSPI_MCR_MSTR \| DSPI_MCR_PCSIS_MASK \|
	512	DSPI_MCR_CRXF \| DSPI_MCR_CTXF;
	513	fsl_dspi_init_mcr(priv, mcr_cfg_val);
	514
8b85dfc6	515	debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
a8919371 HW	516
	517	return 0;
	518	}
	519
	520	static int fsl_dspi_claim_bus(struct udevice *dev)
	521	{
	522	uint sr_val;
	523	struct fsl_dspi_priv *priv;
	524	struct udevice *bus = dev->parent;
8a8d24bd	525	struct dm_spi_slave_plat *slave_plat =
caa4daa2	526	dev_get_parent_plat(dev);
a8919371 HW	527
	528	priv = dev_get_priv(bus);
	529
fc0b5948	530	/* processor special preparation work */
8b85dfc6	531	cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
a8919371 HW	532
	533	/* configure transfer mode */
	534	fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
	535
	536	/* configure active state of CSX */
	537	fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
	538	priv->mode);
	539
	540	fsl_dspi_clr_fifo(priv);
	541
	542	/* check module TX and RX status */
	543	sr_val = dspi_read32(priv->flags, &priv->regs->sr);
	544	if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
	545	debug("DSPI RX/TX not ready!\n");
	546	return -EIO;
	547	}
	548
	549	return 0;
	550	}
	551
	552	static int fsl_dspi_release_bus(struct udevice *dev)
	553	{
	554	struct udevice *bus = dev->parent;
	555	struct fsl_dspi_priv *priv = dev_get_priv(bus);
8a8d24bd	556	struct dm_spi_slave_plat *slave_plat =
caa4daa2	557	dev_get_parent_plat(dev);
a8919371 HW	558
	559	/* halt module */
	560	dspi_halt(priv, 1);
	561
	562	/* processor special release work */
8b85dfc6	563	cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
a8919371 HW	564
	565	return 0;
	566	}
	567
	568	/**
	569	* This function doesn't do anything except help with debugging
	570	*/
	571	static int fsl_dspi_bind(struct udevice *bus)
	572	{
6d83c74d	573	debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
a8919371 HW	574	return 0;
	575	}
	576
d1998a9f	577	static int fsl_dspi_of_to_plat(struct udevice *bus)
a8919371 HW	578	{
a8919371 HW	579	fdt_addr_t addr;
0fd3d911	580	struct fsl_dspi_plat *plat = dev_get_plat(bus);
a8919371	581	const void *blob = gd->fdt_blob;
e160f7d4	582	int node = dev_of_offset(bus);
a8919371 HW	583
	584	if (fdtdec_get_bool(blob, node, "big-endian"))
	585	plat->flags \|= DSPI_FLAG_REGMAP_ENDIAN_BIG;
	586
8c580892 MW	587	plat->num_chipselect = fdtdec_get_int(blob, node,
	588	"spi-num-chipselects",
	589	FSL_DSPI_MAX_CHIPSELECT);
a8919371	590
2548493a	591	addr = dev_read_addr(bus);
a8919371 HW	592	if (addr == FDT_ADDR_T_NONE) {
	593	debug("DSPI: Can't get base address or size\n");
	594	return -ENOMEM;
	595	}
	596	plat->regs_addr = addr;
	597
	598	plat->speed_hz = fdtdec_get_int(blob,
	599	node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
	600
d466f620	601	debug("DSPI: regs=%pa, max-frequency=%d, endianness=%s, num-cs=%d\n",
fdb9f349	602	&plat->regs_addr, plat->speed_hz,
a8919371 HW	603	plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
	604	plat->num_chipselect);
	605
	606	return 0;
	607	}
	608
	609	static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
	610	const void dout, void din, unsigned long flags)
	611	{
	612	struct fsl_dspi_priv *priv;
8a8d24bd	613	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
a8919371 HW	614	struct udevice *bus;
	615
	616	bus = dev->parent;
	617	priv = dev_get_priv(bus);
	618
	619	return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
	620	}
	621
	622	static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
	623	{
	624	struct fsl_dspi_priv *priv = dev_get_priv(bus);
	625
	626	return fsl_dspi_cfg_speed(priv, speed);
	627	}
	628
	629	static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
	630	{
	631	struct fsl_dspi_priv *priv = dev_get_priv(bus);
	632
	633	debug("DSPI set_mode: mode 0x%x.\n", mode);
	634
	635	/*
	636	* We store some chipselect special configure value in priv->ctar_val,
	637	* and we can't get the correct chipselect number here,
	638	* so just store mode value.
	639	* Do really configuration when claim_bus.
	640	*/
	641	priv->mode = mode;
	642
	643	return 0;
	644	}
	645
	646	static const struct dm_spi_ops fsl_dspi_ops = {
	647	.claim_bus = fsl_dspi_claim_bus,
	648	.release_bus = fsl_dspi_release_bus,
	649	.xfer = fsl_dspi_xfer,
	650	.set_speed = fsl_dspi_set_speed,
	651	.set_mode = fsl_dspi_set_mode,
	652	};
	653
	654	static const struct udevice_id fsl_dspi_ids[] = {
	655	{ .compatible = "fsl,vf610-dspi" },
765afe7f	656	{ .compatible = "fsl,ls1021a-v1.0-dspi" },
a8919371 HW	657	{ }
	658	};
	659
	660	U_BOOT_DRIVER(fsl_dspi) = {
	661	.name = "fsl_dspi",
	662	.id = UCLASS_SPI,
	663	.of_match = fsl_dspi_ids,
	664	.ops = &fsl_dspi_ops,
d1998a9f	665	.of_to_plat = fsl_dspi_of_to_plat,
8a8d24bd	666	.plat_auto = sizeof(struct fsl_dspi_plat),
41575d8e	667	.priv_auto = sizeof(struct fsl_dspi_priv),
a8919371 HW	668	.probe = fsl_dspi_probe,
	669	.child_pre_probe = fsl_dspi_child_pre_probe,
	670	.bind = fsl_dspi_bind,
	671	};