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mmc: sdhci-cadence: set timing mode register depending on frequency
[people/ms/u-boot.git] / drivers / spi / fsl_qspi.c
CommitLineData
6b57ff6f 1/*
5bc48308 2 * Copyright 2013-2015 Freescale Semiconductor, Inc.
6b57ff6f
AW		 3 *
4 * Freescale Quad Serial Peripheral Interface (QSPI) driver
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <spi.h>
12#include <asm/io.h>
13#include <linux/sizes.h>
5bc48308
HW		 14#include <dm.h>
15#include <errno.h>
beedbc2e 16#include <watchdog.h>
1c631da4 17#include <wait_bit.h>
6b57ff6f
AW		 18#include "fsl_qspi.h"
19
5bc48308
HW		 20DECLARE_GLOBAL_DATA_PTR;
21
6b57ff6f 22#define RX_BUFFER_SIZE 0x80
b93ab2ee
PF		 23#ifdef CONFIG_MX6SX
24#define TX_BUFFER_SIZE 0x200
25#else
6b57ff6f 26#define TX_BUFFER_SIZE 0x40
b93ab2ee 27#endif
6b57ff6f 28
8770413f 29#define OFFSET_BITS_MASK GENMASK(23, 0)
6b57ff6f
AW		 30
31#define FLASH_STATUS_WEL 0x02
32
33/* SEQID */
34#define SEQID_WREN 1
35#define SEQID_FAST_READ 2
36#define SEQID_RDSR 3
37#define SEQID_SE 4
38#define SEQID_CHIP_ERASE 5
39#define SEQID_PP 6
40#define SEQID_RDID 7
ba4dc8ab 41#define SEQID_BE_4K 8
a2358783
PF		 42#ifdef CONFIG_SPI_FLASH_BAR
43#define SEQID_BRRD 9
44#define SEQID_BRWR 10
45#define SEQID_RDEAR 11
46#define SEQID_WREAR 12
47#endif
febffe8d
YY		 48#define SEQID_WRAR 13
49#define SEQID_RDAR 14
6b57ff6f 50
53e3db7f
PF		 51/* QSPI CMD */
52#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
53#define QSPI_CMD_RDSR 0x05 /* Read status register */
54#define QSPI_CMD_WREN 0x06 /* Write enable */
55#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
ba4dc8ab 56#define QSPI_CMD_BE_4K 0x20 /* 4K erase */
53e3db7f
PF		 57#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
58#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
59#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
60
a2358783
PF		 61/* Used for Micron, winbond and Macronix flashes */
62#define QSPI_CMD_WREAR 0xc5 /* EAR register write */
63#define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */
64
65/* Used for Spansion flashes only. */
66#define QSPI_CMD_BRRD 0x16 /* Bank register read */
67#define QSPI_CMD_BRWR 0x17 /* Bank register write */
68
febffe8d
YY		 69/* Used for Spansion S25FS-S family flash only. */
70#define QSPI_CMD_RDAR 0x65 /* Read any device register */
71#define QSPI_CMD_WRAR 0x71 /* Write any device register */
72
53e3db7f
PF		 73/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
74#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
75#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
76#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
6b57ff6f 77
5bc48308 78/* fsl_qspi_platdata flags */
29e6abd9 79#define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
6b57ff6f 80
5bc48308
HW		 81/* default SCK frequency, unit: HZ */
82#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
6b57ff6f 83
5bc48308
HW		 84/* QSPI max chipselect signals number */
85#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
86
87#ifdef CONFIG_DM_SPI
88/**
89 * struct fsl_qspi_platdata - platform data for Freescale QSPI
90 *
91 * @flags: Flags for QSPI QSPI_FLAG_...
92 * @speed_hz: Default SCK frequency
93 * @reg_base: Base address of QSPI registers
94 * @amba_base: Base address of QSPI memory mapping
95 * @amba_total_size: size of QSPI memory mapping
96 * @flash_num: Number of active slave devices
97 * @num_chipselect: Number of QSPI chipselect signals
98 */
99struct fsl_qspi_platdata {
100 u32 flags;
101 u32 speed_hz;
bf9bffa9
YY		 102 fdt_addr_t reg_base;
103 fdt_addr_t amba_base;
104 fdt_size_t amba_total_size;
5bc48308
HW		 105 u32 flash_num;
106 u32 num_chipselect;
107};
b93ab2ee 108#endif
5bc48308
HW		 109
110/**
111 * struct fsl_qspi_priv - private data for Freescale QSPI
112 *
113 * @flags: Flags for QSPI QSPI_FLAG_...
114 * @bus_clk: QSPI input clk frequency
115 * @speed_hz: Default SCK frequency
116 * @cur_seqid: current LUT table sequence id
117 * @sf_addr: flash access offset
118 * @amba_base: Base address of QSPI memory mapping of every CS
119 * @amba_total_size: size of QSPI memory mapping
120 * @cur_amba_base: Base address of QSPI memory mapping of current CS
121 * @flash_num: Number of active slave devices
122 * @num_chipselect: Number of QSPI chipselect signals
123 * @regs: Point to QSPI register structure for I/O access
124 */
125struct fsl_qspi_priv {
126 u32 flags;
127 u32 bus_clk;
128 u32 speed_hz;
129 u32 cur_seqid;
130 u32 sf_addr;
131 u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
132 u32 amba_total_size;
133 u32 cur_amba_base;
134 u32 flash_num;
135 u32 num_chipselect;
136 struct fsl_qspi_regs *regs;
6b57ff6f
AW		 137};
138
5bc48308 139#ifndef CONFIG_DM_SPI
6b57ff6f
AW		 140struct fsl_qspi {
141 struct spi_slave slave;
5bc48308 142 struct fsl_qspi_priv priv;
6b57ff6f 143};
5bc48308
HW		 144#endif
145
146static u32 qspi_read32(u32 flags, u32 *addr)
147{
148 return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
149 in_be32(addr) : in_le32(addr);
150}
151
152static void qspi_write32(u32 flags, u32 *addr, u32 val)
153{
154 flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
155 out_be32(addr, val) : out_le32(addr, val);
156}
6b57ff6f
AW		 157
158/* QSPI support swapping the flash read/write data
159 * in hardware for LS102xA, but not for VF610 */
160static inline u32 qspi_endian_xchg(u32 data)
161{
162#ifdef CONFIG_VF610
163 return swab32(data);
164#else
165 return data;
166#endif
167}
168
5bc48308 169static void qspi_set_lut(struct fsl_qspi_priv *priv)
6b57ff6f 170{
5bc48308 171 struct fsl_qspi_regs *regs = priv->regs;
6b57ff6f
AW		 172 u32 lut_base;
173
174 /* Unlock the LUT */
5bc48308
HW		 175 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
176 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
6b57ff6f
AW		 177
178 /* Write Enable */
179 lut_base = SEQID_WREN * 4;
5bc48308 180 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
6b57ff6f 181 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
5bc48308
HW		 182 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
183 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
184 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 185
186 /* Fast Read */
187 lut_base = SEQID_FAST_READ * 4;
a2358783 188#ifdef CONFIG_SPI_FLASH_BAR
5bc48308
HW		 189 qspi_write32(priv->flags, &regs->lut[lut_base],
190 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
191 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
a2358783
PF		 192 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
193#else
6b57ff6f 194 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
5bc48308
HW		 195 qspi_write32(priv->flags, &regs->lut[lut_base],
196 OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
197 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
198 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
6b57ff6f 199 else
5bc48308 200 qspi_write32(priv->flags, &regs->lut[lut_base],
53e3db7f
PF		 201 OPRND0(QSPI_CMD_FAST_READ_4B) |
202 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
203 OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
204 INSTR1(LUT_ADDR));
a2358783 205#endif
5bc48308
HW		 206 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
207 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
208 OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
209 INSTR1(LUT_READ));
210 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
211 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 212
213 /* Read Status */
214 lut_base = SEQID_RDSR * 4;
5bc48308 215 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
6b57ff6f
AW		 216 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
217 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
5bc48308
HW		 218 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
219 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
220 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 221
222 /* Erase a sector */
223 lut_base = SEQID_SE * 4;
a2358783 224#ifdef CONFIG_SPI_FLASH_BAR
5bc48308 225 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
a2358783
PF		 226 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
227 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
228#else
6b57ff6f 229 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
5bc48308
HW		 230 qspi_write32(priv->flags, &regs->lut[lut_base],
231 OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
232 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
233 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
6b57ff6f 234 else
5bc48308
HW		 235 qspi_write32(priv->flags, &regs->lut[lut_base],
236 OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
237 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
238 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
a2358783 239#endif
5bc48308
HW		 240 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
241 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
242 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 243
244 /* Erase the whole chip */
245 lut_base = SEQID_CHIP_ERASE * 4;
5bc48308
HW		 246 qspi_write32(priv->flags, &regs->lut[lut_base],
247 OPRND0(QSPI_CMD_CHIP_ERASE) |
248 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
249 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
250 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
251 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 252
253 /* Page Program */
254 lut_base = SEQID_PP * 4;
a2358783 255#ifdef CONFIG_SPI_FLASH_BAR
5bc48308 256 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
a2358783
PF		 257 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
258 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
259#else
6b57ff6f 260 if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
5bc48308
HW		 261 qspi_write32(priv->flags, &regs->lut[lut_base],
262 OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
263 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
264 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
6b57ff6f 265 else
5bc48308
HW		 266 qspi_write32(priv->flags, &regs->lut[lut_base],
267 OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
268 INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
269 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
a2358783 270#endif
b93ab2ee
PF		 271#ifdef CONFIG_MX6SX
272 /*
273 * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
274 * So, Use IDATSZ in IPCR to determine the size and here set 0.
275 */
5bc48308 276 qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
b93ab2ee
PF		 277 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
278#else
5bc48308
HW		 279 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
280 OPRND0(TX_BUFFER_SIZE) |
281 PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
b93ab2ee 282#endif
5bc48308
HW		 283 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
284 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f
AW		 285
286 /* READ ID */
287 lut_base = SEQID_RDID * 4;
5bc48308 288 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
6b57ff6f
AW		 289 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
290 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
5bc48308
HW		 291 qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
292 qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
293 qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
6b57ff6f 294
ba4dc8ab
PF		 295 /* SUB SECTOR 4K ERASE */
296 lut_base = SEQID_BE_4K * 4;
5bc48308 297 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
ba4dc8ab
PF		 298 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
299 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
300
a2358783
PF		 301#ifdef CONFIG_SPI_FLASH_BAR
302 /*
303 * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
304 * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
305 * initialization.
306 */
307 lut_base = SEQID_BRRD * 4;
5bc48308 308 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
a2358783
PF		 309 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
310 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
311
312 lut_base = SEQID_BRWR * 4;
5bc48308 313 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
a2358783
PF		 314 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
315 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
316
317 lut_base = SEQID_RDEAR * 4;
5bc48308 318 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
a2358783
PF		 319 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
320 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
321
322 lut_base = SEQID_WREAR * 4;
5bc48308 323 qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
a2358783
PF		 324 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
325 PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
326#endif
febffe8d
YY		 327
328 /*
329 * Read any device register.
330 * Used for Spansion S25FS-S family flash only.
331 */
332 lut_base = SEQID_RDAR * 4;
333 qspi_write32(priv->flags, &regs->lut[lut_base],
334 OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
335 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
336 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
337 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
338 OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
339 OPRND1(1) | PAD1(LUT_PAD1) |
340 INSTR1(LUT_READ));
341
342 /*
343 * Write any device register.
344 * Used for Spansion S25FS-S family flash only.
345 */
346 lut_base = SEQID_WRAR * 4;
347 qspi_write32(priv->flags, &regs->lut[lut_base],
348 OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
349 INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
350 PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
351 qspi_write32(priv->flags, &regs->lut[lut_base + 1],
352 OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
353
6b57ff6f 354 /* Lock the LUT */
5bc48308
HW		 355 qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
356 qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
6b57ff6f
AW		 357}
358
5f7f70c1
PF		 359#if defined(CONFIG_SYS_FSL_QSPI_AHB)
360/*
361 * If we have changed the content of the flash by writing or erasing,
362 * we need to invalidate the AHB buffer. If we do not do so, we may read out
363 * the wrong data. The spec tells us reset the AHB domain and Serial Flash
364 * domain at the same time.
365 */
5bc48308 366static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
5f7f70c1 367{
5bc48308 368 struct fsl_qspi_regs *regs = priv->regs;
5f7f70c1
PF		 369 u32 reg;
370
5bc48308 371 reg = qspi_read32(priv->flags, &regs->mcr);
5f7f70c1 372 reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
5bc48308 373 qspi_write32(priv->flags, &regs->mcr, reg);
5f7f70c1
PF		 374
375 /*
376 * The minimum delay : 1 AHB + 2 SFCK clocks.
377 * Delay 1 us is enough.
378 */
379 udelay(1);
380
381 reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
5bc48308 382 qspi_write32(priv->flags, &regs->mcr, reg);
5f7f70c1
PF		 383}
384
385/* Read out the data from the AHB buffer. */
5bc48308 386static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
5f7f70c1 387{
5bc48308 388 struct fsl_qspi_regs *regs = priv->regs;
5f7f70c1 389 u32 mcr_reg;
04e5c6d9 390 void *rx_addr = NULL;
5f7f70c1 391
5bc48308 392 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
5f7f70c1 393
5bc48308
HW		 394 qspi_write32(priv->flags, &regs->mcr,
395 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
5f7f70c1
PF		 396 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
397
04e5c6d9 398 rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
5f7f70c1 399 /* Read out the data directly from the AHB buffer. */
04e5c6d9 400 memcpy(rxbuf, rx_addr, len);
5f7f70c1 401
5bc48308 402 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
5f7f70c1
PF		 403}
404
5bc48308 405static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
5f7f70c1
PF		 406{
407 u32 reg, reg2;
5bc48308 408 struct fsl_qspi_regs *regs = priv->regs;
5f7f70c1 409
5bc48308 410 reg = qspi_read32(priv->flags, &regs->mcr);
5f7f70c1 411 /* Disable the module */
5bc48308 412 qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
5f7f70c1
PF		 413
414 /* Set the Sampling Register for DDR */
5bc48308 415 reg2 = qspi_read32(priv->flags, &regs->smpr);
5f7f70c1
PF		 416 reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
417 reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
5bc48308 418 qspi_write32(priv->flags, &regs->smpr, reg2);
5f7f70c1
PF		 419
420 /* Enable the module again (enable the DDR too) */
421 reg |= QSPI_MCR_DDR_EN_MASK;
422 /* Enable bit 29 for imx6sx */
29e6abd9 423 reg |= BIT(29);
5f7f70c1 424
5bc48308 425 qspi_write32(priv->flags, &regs->mcr, reg);
5f7f70c1
PF		 426}
427
428/*
429 * There are two different ways to read out the data from the flash:
430 * the "IP Command Read" and the "AHB Command Read".
431 *
432 * The IC guy suggests we use the "AHB Command Read" which is faster
433 * then the "IP Command Read". (What's more is that there is a bug in
434 * the "IP Command Read" in the Vybrid.)
435 *
436 * After we set up the registers for the "AHB Command Read", we can use
437 * the memcpy to read the data directly. A "missed" access to the buffer
438 * causes the controller to clear the buffer, and use the sequence pointed
439 * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
440 */
5bc48308 441static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
5f7f70c1 442{
5bc48308
HW		 443 struct fsl_qspi_regs *regs = priv->regs;
444
5f7f70c1 445 /* AHB configuration for access buffer 0/1/2 .*/
5bc48308
HW		 446 qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
447 qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
448 qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
449 qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
5f7f70c1
PF		 450 (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
451
452 /* We only use the buffer3 */
5bc48308
HW		 453 qspi_write32(priv->flags, &regs->buf0ind, 0);
454 qspi_write32(priv->flags, &regs->buf1ind, 0);
455 qspi_write32(priv->flags, &regs->buf2ind, 0);
5f7f70c1
PF		 456
457 /*
458 * Set the default lut sequence for AHB Read.
459 * Parallel mode is disabled.
460 */
5bc48308 461 qspi_write32(priv->flags, &regs->bfgencr,
5f7f70c1
PF		 462 SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
463
464 /*Enable DDR Mode*/
5bc48308 465 qspi_enable_ddr_mode(priv);
5f7f70c1
PF		 466}
467#endif
468
a2358783
PF		 469#ifdef CONFIG_SPI_FLASH_BAR
470/* Bank register read/write, EAR register read/write */
5bc48308 471static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
a2358783 472{
5bc48308 473 struct fsl_qspi_regs *regs = priv->regs;
a2358783
PF		 474 u32 reg, mcr_reg, data, seqid;
475
5bc48308
HW		 476 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
477 qspi_write32(priv->flags, &regs->mcr,
478 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
a2358783 479 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
5bc48308 480 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
a2358783 481
5bc48308 482 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
a2358783 483
5bc48308 484 if (priv->cur_seqid == QSPI_CMD_BRRD)
a2358783
PF		 485 seqid = SEQID_BRRD;
486 else
487 seqid = SEQID_RDEAR;
488
5bc48308
HW		 489 qspi_write32(priv->flags, &regs->ipcr,
490 (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
a2358783
PF		 491
492 /* Wait previous command complete */
5bc48308 493 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
a2358783
PF		 494 ;
495
496 while (1) {
4df24f2c
AS		 497 WATCHDOG_RESET();
498
5bc48308 499 reg = qspi_read32(priv->flags, &regs->rbsr);
a2358783 500 if (reg & QSPI_RBSR_RDBFL_MASK) {
5bc48308 501 data = qspi_read32(priv->flags, &regs->rbdr[0]);
a2358783
PF		 502 data = qspi_endian_xchg(data);
503 memcpy(rxbuf, &data, len);
5bc48308
HW		 504 qspi_write32(priv->flags, &regs->mcr,
505 qspi_read32(priv->flags, &regs->mcr) |
a2358783
PF		 506 QSPI_MCR_CLR_RXF_MASK);
507 break;
508 }
509 }
510
5bc48308 511 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
a2358783
PF		 512}
513#endif
514
5bc48308 515static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
6b57ff6f 516{
5bc48308 517 struct fsl_qspi_regs *regs = priv->regs;
5207014d
GQ		 518 u32 mcr_reg, rbsr_reg, data, size;
519 int i;
6b57ff6f 520
5bc48308
HW		 521 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
522 qspi_write32(priv->flags, &regs->mcr,
523 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
524 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
525 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
6b57ff6f 526
5bc48308 527 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
6b57ff6f 528
5bc48308
HW		 529 qspi_write32(priv->flags, &regs->ipcr,
530 (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
531 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 532 ;
533
534 i = 0;
5207014d 535 while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
4df24f2c
AS		 536 WATCHDOG_RESET();
537
5bc48308 538 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
6b57ff6f 539 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
5bc48308 540 data = qspi_read32(priv->flags, &regs->rbdr[i]);
6b57ff6f 541 data = qspi_endian_xchg(data);
5207014d
GQ		 542 size = (len < 4) ? len : 4;
543 memcpy(rxbuf, &data, size);
544 len -= size;
6b57ff6f 545 rxbuf++;
6b57ff6f
AW		 546 i++;
547 }
548 }
549
5bc48308 550 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
6b57ff6f
AW		 551}
552
5f7f70c1 553/* If not use AHB read, read data from ip interface */
5bc48308 554static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
6b57ff6f 555{
5bc48308 556 struct fsl_qspi_regs *regs = priv->regs;
6b57ff6f
AW		 557 u32 mcr_reg, data;
558 int i, size;
559 u32 to_or_from;
febffe8d
YY		 560 u32 seqid;
561
562 if (priv->cur_seqid == QSPI_CMD_RDAR)
563 seqid = SEQID_RDAR;
564 else
565 seqid = SEQID_FAST_READ;
6b57ff6f 566
5bc48308
HW		 567 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
568 qspi_write32(priv->flags, &regs->mcr,
569 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
570 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
571 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
6b57ff6f 572
5bc48308 573 to_or_from = priv->sf_addr + priv->cur_amba_base;
6b57ff6f
AW		 574
575 while (len > 0) {
beedbc2e
AS		 576 WATCHDOG_RESET();
577
5bc48308 578 qspi_write32(priv->flags, &regs->sfar, to_or_from);
6b57ff6f
AW		 579
580 size = (len > RX_BUFFER_SIZE) ?
581 RX_BUFFER_SIZE : len;
582
5bc48308 583 qspi_write32(priv->flags, &regs->ipcr,
febffe8d 584 (seqid << QSPI_IPCR_SEQID_SHIFT) |
5bc48308
HW		 585 size);
586 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 587 ;
588
589 to_or_from += size;
590 len -= size;
591
592 i = 0;
593 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
5bc48308 594 data = qspi_read32(priv->flags, &regs->rbdr[i]);
6b57ff6f 595 data = qspi_endian_xchg(data);
febffe8d
YY		 596 if (size < 4)
597 memcpy(rxbuf, &data, size);
598 else
599 memcpy(rxbuf, &data, 4);
6b57ff6f
AW		 600 rxbuf++;
601 size -= 4;
602 i++;
603 }
5bc48308
HW		 604 qspi_write32(priv->flags, &regs->mcr,
605 qspi_read32(priv->flags, &regs->mcr) |
606 QSPI_MCR_CLR_RXF_MASK);
6b57ff6f
AW		 607 }
608
5bc48308 609 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
6b57ff6f
AW		 610}
611
5bc48308 612static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
6b57ff6f 613{
5bc48308 614 struct fsl_qspi_regs *regs = priv->regs;
a2358783 615 u32 mcr_reg, data, reg, status_reg, seqid;
6b57ff6f
AW		 616 int i, size, tx_size;
617 u32 to_or_from = 0;
618
5bc48308
HW		 619 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
620 qspi_write32(priv->flags, &regs->mcr,
621 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
622 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
623 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
6b57ff6f
AW		 624
625 status_reg = 0;
626 while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
beedbc2e
AS		 627 WATCHDOG_RESET();
628
5bc48308
HW		 629 qspi_write32(priv->flags, &regs->ipcr,
630 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
631 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 632 ;
633
5bc48308
HW		 634 qspi_write32(priv->flags, &regs->ipcr,
635 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
636 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 637 ;
638
5bc48308 639 reg = qspi_read32(priv->flags, &regs->rbsr);
6b57ff6f 640 if (reg & QSPI_RBSR_RDBFL_MASK) {
5bc48308 641 status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
6b57ff6f
AW		 642 status_reg = qspi_endian_xchg(status_reg);
643 }
5bc48308
HW		 644 qspi_write32(priv->flags, &regs->mcr,
645 qspi_read32(priv->flags, &regs->mcr) |
646 QSPI_MCR_CLR_RXF_MASK);
6b57ff6f
AW		 647 }
648
a2358783
PF		 649 /* Default is page programming */
650 seqid = SEQID_PP;
febffe8d
YY		 651 if (priv->cur_seqid == QSPI_CMD_WRAR)
652 seqid = SEQID_WRAR;
a2358783 653#ifdef CONFIG_SPI_FLASH_BAR
5bc48308 654 if (priv->cur_seqid == QSPI_CMD_BRWR)
a2358783 655 seqid = SEQID_BRWR;
5bc48308 656 else if (priv->cur_seqid == QSPI_CMD_WREAR)
a2358783
PF		 657 seqid = SEQID_WREAR;
658#endif
659
5bc48308 660 to_or_from = priv->sf_addr + priv->cur_amba_base;
a2358783 661
5bc48308 662 qspi_write32(priv->flags, &regs->sfar, to_or_from);
6b57ff6f
AW		 663
664 tx_size = (len > TX_BUFFER_SIZE) ?
665 TX_BUFFER_SIZE : len;
666
10509987
SG		 667 size = tx_size / 16;
668 /*
669 * There must be atleast 128bit data
670 * available in TX FIFO for any pop operation
671 */
672 if (tx_size % 16)
673 size++;
674 for (i = 0; i < size * 4; i++) {
a2358783
PF		 675 memcpy(&data, txbuf, 4);
676 data = qspi_endian_xchg(data);
5bc48308 677 qspi_write32(priv->flags, &regs->tbdr, data);
a2358783 678 txbuf += 4;
6b57ff6f
AW		 679 }
680
5bc48308
HW		 681 qspi_write32(priv->flags, &regs->ipcr,
682 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
683 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 684 ;
685
5bc48308 686 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
6b57ff6f
AW		 687}
688
940d2b89 689static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
6b57ff6f 690{
5bc48308 691 struct fsl_qspi_regs *regs = priv->regs;
6b57ff6f
AW		 692 u32 mcr_reg, reg, data;
693
5bc48308
HW		 694 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
695 qspi_write32(priv->flags, &regs->mcr,
696 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
697 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
698 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
6b57ff6f 699
5bc48308 700 qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
6b57ff6f 701
5bc48308
HW		 702 qspi_write32(priv->flags, &regs->ipcr,
703 (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
704 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 705 ;
706
707 while (1) {
4df24f2c
AS		 708 WATCHDOG_RESET();
709
5bc48308 710 reg = qspi_read32(priv->flags, &regs->rbsr);
6b57ff6f 711 if (reg & QSPI_RBSR_RDBFL_MASK) {
5bc48308 712 data = qspi_read32(priv->flags, &regs->rbdr[0]);
6b57ff6f 713 data = qspi_endian_xchg(data);
940d2b89 714 memcpy(rxbuf, &data, len);
5bc48308
HW		 715 qspi_write32(priv->flags, &regs->mcr,
716 qspi_read32(priv->flags, &regs->mcr) |
717 QSPI_MCR_CLR_RXF_MASK);
6b57ff6f
AW		 718 break;
719 }
720 }
721
5bc48308 722 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
6b57ff6f
AW		 723}
724
5bc48308 725static void qspi_op_erase(struct fsl_qspi_priv *priv)
6b57ff6f 726{
5bc48308 727 struct fsl_qspi_regs *regs = priv->regs;
6b57ff6f
AW		 728 u32 mcr_reg;
729 u32 to_or_from = 0;
730
5bc48308
HW		 731 mcr_reg = qspi_read32(priv->flags, &regs->mcr);
732 qspi_write32(priv->flags, &regs->mcr,
733 QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
734 QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
735 qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
6b57ff6f 736
5bc48308
HW		 737 to_or_from = priv->sf_addr + priv->cur_amba_base;
738 qspi_write32(priv->flags, &regs->sfar, to_or_from);
6b57ff6f 739
5bc48308
HW		 740 qspi_write32(priv->flags, &regs->ipcr,
741 (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
742 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 743 ;
744
5bc48308
HW		 745 if (priv->cur_seqid == QSPI_CMD_SE) {
746 qspi_write32(priv->flags, &regs->ipcr,
ba4dc8ab 747 (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
5bc48308
HW		 748 } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
749 qspi_write32(priv->flags, &regs->ipcr,
ba4dc8ab
PF		 750 (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
751 }
5bc48308 752 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
6b57ff6f
AW		 753 ;
754
5bc48308 755 qspi_write32(priv->flags, &regs->mcr, mcr_reg);
6b57ff6f
AW		 756}
757
5bc48308 758int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
6b57ff6f
AW		 759 const void *dout, void *din, unsigned long flags)
760{
6b57ff6f 761 u32 bytes = DIV_ROUND_UP(bitlen, 8);
a2358783 762 static u32 wr_sfaddr;
6b57ff6f
AW		 763 u32 txbuf;
764
4df24f2c
AS		 765 WATCHDOG_RESET();
766
6b57ff6f 767 if (dout) {
a2358783 768 if (flags & SPI_XFER_BEGIN) {
5bc48308 769 priv->cur_seqid = *(u8 *)dout;
a2358783
PF		 770 memcpy(&txbuf, dout, 4);
771 }
6b57ff6f
AW		 772
773 if (flags == SPI_XFER_END) {
5bc48308
HW		 774 priv->sf_addr = wr_sfaddr;
775 qspi_op_write(priv, (u8 *)dout, bytes);
6b57ff6f
AW		 776 return 0;
777 }
778
febffe8d
YY		 779 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
780 priv->cur_seqid == QSPI_CMD_RDAR) {
5bc48308
HW		 781 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
782 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
783 (priv->cur_seqid == QSPI_CMD_BE_4K)) {
784 priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
785 qspi_op_erase(priv);
febffe8d
YY		 786 } else if (priv->cur_seqid == QSPI_CMD_PP ||
787 priv->cur_seqid == QSPI_CMD_WRAR) {
a2358783 788 wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
5bc48308
HW		 789 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
790 (priv->cur_seqid == QSPI_CMD_WREAR)) {
a2358783 791#ifdef CONFIG_SPI_FLASH_BAR
a2358783 792 wr_sfaddr = 0;
a2358783 793#endif
5bc48308 794 }
6b57ff6f
AW		 795 }
796
797 if (din) {
5bc48308 798 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
5f7f70c1 799#ifdef CONFIG_SYS_FSL_QSPI_AHB
5bc48308 800 qspi_ahb_read(priv, din, bytes);
5f7f70c1 801#else
5bc48308 802 qspi_op_read(priv, din, bytes);
5f7f70c1 803#endif
febffe8d
YY		 804 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
805 qspi_op_read(priv, din, bytes);
5bc48308
HW		 806 } else if (priv->cur_seqid == QSPI_CMD_RDID)
807 qspi_op_rdid(priv, din, bytes);
808 else if (priv->cur_seqid == QSPI_CMD_RDSR)
940d2b89 809 qspi_op_rdsr(priv, din, bytes);
a2358783 810#ifdef CONFIG_SPI_FLASH_BAR
5bc48308
HW		 811 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
812 (priv->cur_seqid == QSPI_CMD_RDEAR)) {
813 priv->sf_addr = 0;
814 qspi_op_rdbank(priv, din, bytes);
a2358783
PF		 815 }
816#endif
6b57ff6f
AW		 817 }
818
5f7f70c1 819#ifdef CONFIG_SYS_FSL_QSPI_AHB
5bc48308
HW		 820 if ((priv->cur_seqid == QSPI_CMD_SE) ||
821 (priv->cur_seqid == QSPI_CMD_PP) ||
822 (priv->cur_seqid == QSPI_CMD_BE_4K) ||
823 (priv->cur_seqid == QSPI_CMD_WREAR) ||
824 (priv->cur_seqid == QSPI_CMD_BRWR))
825 qspi_ahb_invalid(priv);
826#endif
827
828 return 0;
829}
830
831void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
832{
833 u32 mcr_val;
834
835 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
836 if (disable)
837 mcr_val |= QSPI_MCR_MDIS_MASK;
838 else
839 mcr_val &= ~QSPI_MCR_MDIS_MASK;
840 qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
841}
842
843void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
844{
845 u32 smpr_val;
846
847 smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
848 smpr_val &= ~clear_bits;
849 smpr_val |= set_bits;
850 qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
851}
852#ifndef CONFIG_DM_SPI
853static unsigned long spi_bases[] = {
854 QSPI0_BASE_ADDR,
855#ifdef CONFIG_MX6SX
856 QSPI1_BASE_ADDR,
857#endif
858};
859
860static unsigned long amba_bases[] = {
861 QSPI0_AMBA_BASE,
862#ifdef CONFIG_MX6SX
863 QSPI1_AMBA_BASE,
864#endif
865};
866
867static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
868{
869 return container_of(slave, struct fsl_qspi, slave);
870}
871
872struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
873 unsigned int max_hz, unsigned int mode)
874{
3c6b1767 875 u32 mcr_val;
5bc48308
HW		 876 struct fsl_qspi *qspi;
877 struct fsl_qspi_regs *regs;
878 u32 total_size;
879
880 if (bus >= ARRAY_SIZE(spi_bases))
881 return NULL;
882
883 if (cs >= FSL_QSPI_FLASH_NUM)
884 return NULL;
885
886 qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
887 if (!qspi)
888 return NULL;
889
890#ifdef CONFIG_SYS_FSL_QSPI_BE
891 qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
892#endif
893
894 regs = (struct fsl_qspi_regs *)spi_bases[bus];
895 qspi->priv.regs = regs;
896 /*
897 * According cs, use different amba_base to choose the
898 * corresponding flash devices.
899 *
900 * If not, only one flash device is used even if passing
901 * different cs using `sf probe`
902 */
903 qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
904
905 qspi->slave.max_write_size = TX_BUFFER_SIZE;
906
3c6b1767 907 mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
5bc48308 908 qspi_write32(qspi->priv.flags, &regs->mcr,
3c6b1767
YS		 909 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
910 (mcr_val & QSPI_MCR_END_CFD_MASK));
5bc48308
HW		 911
912 qspi_cfg_smpr(&qspi->priv,
913 ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
914 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
915
916 total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
917 /*
918 * Any read access to non-implemented addresses will provide
919 * undefined results.
920 *
921 * In case single die flash devices, TOP_ADDR_MEMA2 and
922 * TOP_ADDR_MEMB2 should be initialized/programmed to
923 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
924 * setting the size of these devices to 0. This would ensure
925 * that the complete memory map is assigned to only one flash device.
926 */
927 qspi_write32(qspi->priv.flags, &regs->sfa1ad,
928 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
929 qspi_write32(qspi->priv.flags, &regs->sfa2ad,
930 FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
931 qspi_write32(qspi->priv.flags, &regs->sfb1ad,
932 total_size | amba_bases[bus]);
933 qspi_write32(qspi->priv.flags, &regs->sfb2ad,
934 total_size | amba_bases[bus]);
935
936 qspi_set_lut(&qspi->priv);
937
938#ifdef CONFIG_SYS_FSL_QSPI_AHB
939 qspi_init_ahb_read(&qspi->priv);
5f7f70c1
PF		 940#endif
941
5bc48308
HW		 942 qspi_module_disable(&qspi->priv, 0);
943
944 return &qspi->slave;
945}
946
947void spi_free_slave(struct spi_slave *slave)
948{
949 struct fsl_qspi *qspi = to_qspi_spi(slave);
950
951 free(qspi);
952}
953
954int spi_claim_bus(struct spi_slave *slave)
955{
6b57ff6f
AW		 956 return 0;
957}
958
959void spi_release_bus(struct spi_slave *slave)
960{
961 /* Nothing to do */
962}
5bc48308
HW		 963
964int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
965 const void *dout, void *din, unsigned long flags)
966{
967 struct fsl_qspi *qspi = to_qspi_spi(slave);
968
969 return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
970}
971
972void spi_init(void)
973{
974 /* Nothing to do */
975}
976#else
977static int fsl_qspi_child_pre_probe(struct udevice *dev)
978{
bcbe3d15 979 struct spi_slave *slave = dev_get_parent_priv(dev);
5bc48308
HW		 980
981 slave->max_write_size = TX_BUFFER_SIZE;
982
983 return 0;
984}
985
986static int fsl_qspi_probe(struct udevice *bus)
987{
3c6b1767 988 u32 mcr_val;
4e147418 989 u32 amba_size_per_chip;
5bc48308
HW		 990 struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
991 struct fsl_qspi_priv *priv = dev_get_priv(bus);
992 struct dm_spi_bus *dm_spi_bus;
1c631da4 993 int i, ret;
5bc48308
HW		 994
995 dm_spi_bus = bus->uclass_priv;
996
997 dm_spi_bus->max_hz = plat->speed_hz;
998
c2a4cb17 999 priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
5bc48308
HW		 1000 priv->flags = plat->flags;
1001
1002 priv->speed_hz = plat->speed_hz;
bf9bffa9
YY		 1003 /*
1004 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
1005 * AMBA memory zone should be located on the 0~4GB space
1006 * even on a 64bits cpu.
1007 */
1008 priv->amba_base[0] = (u32)plat->amba_base;
1009 priv->amba_total_size = (u32)plat->amba_total_size;
5bc48308
HW		 1010 priv->flash_num = plat->flash_num;
1011 priv->num_chipselect = plat->num_chipselect;
1012
1c631da4
SG		 1013 /* make sure controller is not busy anywhere */
1014 ret = wait_for_bit(__func__, &priv->regs->sr,
1015 QSPI_SR_BUSY_MASK |
1016 QSPI_SR_AHB_ACC_MASK |
1017 QSPI_SR_IP_ACC_MASK,
1018 false, 100, false);
1019
1020 if (ret) {
1021 debug("ERROR : The controller is busy\n");
1022 return ret;
1023 }
1024
3c6b1767 1025 mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
5bc48308 1026 qspi_write32(priv->flags, &priv->regs->mcr,
3c6b1767
YS		 1027 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1028 (mcr_val & QSPI_MCR_END_CFD_MASK));
5bc48308
HW		 1029
1030 qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1031 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1032
4e147418
YY		 1033 /*
1034 * Assign AMBA memory zone for every chipselect
1035 * QuadSPI has two channels, every channel has two chipselects.
1036 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1037 * into two parts and assign to every channel. This indicate that every
1038 * channel only has one valid chipselect.
1039 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1040 * into four parts and assign to every chipselect.
1041 * Every channel will has two valid chipselects.
1042 */
1043 amba_size_per_chip = priv->amba_total_size >>
1044 (priv->num_chipselect >> 1);
1045 for (i = 1 ; i < priv->num_chipselect ; i++)
1046 priv->amba_base[i] =
1047 amba_size_per_chip + priv->amba_base[i - 1];
1048
5bc48308
HW		 1049 /*
1050 * Any read access to non-implemented addresses will provide
1051 * undefined results.
1052 *
1053 * In case single die flash devices, TOP_ADDR_MEMA2 and
1054 * TOP_ADDR_MEMB2 should be initialized/programmed to
1055 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1056 * setting the size of these devices to 0. This would ensure
1057 * that the complete memory map is assigned to only one flash device.
1058 */
38a5c57a
SG		 1059 qspi_write32(priv->flags, &priv->regs->sfa1ad,
1060 priv->amba_base[0] + amba_size_per_chip);
4e147418 1061 switch (priv->num_chipselect) {
38a5c57a
SG		 1062 case 1:
1063 break;
4e147418
YY		 1064 case 2:
1065 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1066 priv->amba_base[1]);
1067 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1068 priv->amba_base[1] + amba_size_per_chip);
1069 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1070 priv->amba_base[1] + amba_size_per_chip);
1071 break;
1072 case 4:
1073 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1074 priv->amba_base[2]);
1075 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1076 priv->amba_base[3]);
1077 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1078 priv->amba_base[3] + amba_size_per_chip);
1079 break;
1080 default:
1081 debug("Error: Unsupported chipselect number %u!\n",
1082 priv->num_chipselect);
1083 qspi_module_disable(priv, 1);
1084 return -EINVAL;
1085 }
5bc48308
HW		 1086
1087 qspi_set_lut(priv);
1088
1089#ifdef CONFIG_SYS_FSL_QSPI_AHB
1090 qspi_init_ahb_read(priv);
1091#endif
1092
1093 qspi_module_disable(priv, 0);
1094
1095 return 0;
1096}
1097
1098static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1099{
bf9bffa9 1100 struct fdt_resource res_regs, res_mem;
5bc48308
HW		 1101 struct fsl_qspi_platdata *plat = bus->platdata;
1102 const void *blob = gd->fdt_blob;
e160f7d4 1103 int node = dev_of_offset(bus);
5bc48308
HW		 1104 int ret, flash_num = 0, subnode;
1105
1106 if (fdtdec_get_bool(blob, node, "big-endian"))
1107 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1108
bf9bffa9
YY		 1109 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1110 "QuadSPI", &res_regs);
1111 if (ret) {
1112 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1113 return -ENOMEM;
1114 }
1115 ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1116 "QuadSPI-memory", &res_mem);
5bc48308 1117 if (ret) {
bf9bffa9 1118 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
5bc48308
HW		 1119 return -ENOMEM;
1120 }
1121
1122 /* Count flash numbers */
df87e6b1 1123 fdt_for_each_subnode(subnode, blob, node)
5bc48308
HW		 1124 ++flash_num;
1125
1126 if (flash_num == 0) {
1127 debug("Error: Missing flashes!\n");
1128 return -ENODEV;
1129 }
1130
1131 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1132 FSL_QSPI_DEFAULT_SCK_FREQ);
1133 plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1134 FSL_QSPI_MAX_CHIPSELECT_NUM);
1135
bf9bffa9
YY		 1136 plat->reg_base = res_regs.start;
1137 plat->amba_base = res_mem.start;
1138 plat->amba_total_size = res_mem.end - res_mem.start + 1;
5bc48308
HW		 1139 plat->flash_num = flash_num;
1140
bf9bffa9 1141 debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
5bc48308 1142 __func__,
bf9bffa9
YY		 1143 (u64)plat->reg_base,
1144 (u64)plat->amba_base,
1145 (u64)plat->amba_total_size,
5bc48308
HW		 1146 plat->speed_hz,
1147 plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1148 );
1149
1150 return 0;
1151}
1152
1153static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1154 const void *dout, void *din, unsigned long flags)
1155{
1156 struct fsl_qspi_priv *priv;
1157 struct udevice *bus;
1158
1159 bus = dev->parent;
1160 priv = dev_get_priv(bus);
1161
1162 return qspi_xfer(priv, bitlen, dout, din, flags);
1163}
1164
1165static int fsl_qspi_claim_bus(struct udevice *dev)
1166{
1167 struct fsl_qspi_priv *priv;
1168 struct udevice *bus;
1169 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1c631da4 1170 int ret;
5bc48308
HW		 1171
1172 bus = dev->parent;
1173 priv = dev_get_priv(bus);
1174
1c631da4
SG		 1175 /* make sure controller is not busy anywhere */
1176 ret = wait_for_bit(__func__, &priv->regs->sr,
1177 QSPI_SR_BUSY_MASK |
1178 QSPI_SR_AHB_ACC_MASK |
1179 QSPI_SR_IP_ACC_MASK,
1180 false, 100, false);
1181
1182 if (ret) {
1183 debug("ERROR : The controller is busy\n");
1184 return ret;
1185 }
1186
4e147418 1187 priv->cur_amba_base = priv->amba_base[slave_plat->cs];
5bc48308
HW		 1188
1189 qspi_module_disable(priv, 0);
1190
1191 return 0;
1192}
1193
1194static int fsl_qspi_release_bus(struct udevice *dev)
1195{
1196 struct fsl_qspi_priv *priv;
1197 struct udevice *bus;
1198
1199 bus = dev->parent;
1200 priv = dev_get_priv(bus);
1201
1202 qspi_module_disable(priv, 1);
1203
1204 return 0;
1205}
1206
1207static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1208{
1209 /* Nothing to do */
1210 return 0;
1211}
1212
1213static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1214{
1215 /* Nothing to do */
1216 return 0;
1217}
1218
1219static const struct dm_spi_ops fsl_qspi_ops = {
1220 .claim_bus = fsl_qspi_claim_bus,
1221 .release_bus = fsl_qspi_release_bus,
1222 .xfer = fsl_qspi_xfer,
1223 .set_speed = fsl_qspi_set_speed,
1224 .set_mode = fsl_qspi_set_mode,
1225};
1226
1227static const struct udevice_id fsl_qspi_ids[] = {
1228 { .compatible = "fsl,vf610-qspi" },
1229 { .compatible = "fsl,imx6sx-qspi" },
1230 { }
1231};
1232
1233U_BOOT_DRIVER(fsl_qspi) = {
1234 .name = "fsl_qspi",
1235 .id = UCLASS_SPI,
1236 .of_match = fsl_qspi_ids,
1237 .ops = &fsl_qspi_ops,
1238 .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1239 .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1240 .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1241 .probe = fsl_qspi_probe,
1242 .child_pre_probe = fsl_qspi_child_pre_probe,
1243};
1244#endif
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