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6b57ff6f | 1 | /* |
5bc48308 | 2 | * Copyright 2013-2015 Freescale Semiconductor, Inc. |
6b57ff6f AW |
3 | * |
4 | * Freescale Quad Serial Peripheral Interface (QSPI) driver | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
10 | #include <malloc.h> | |
11 | #include <spi.h> | |
12 | #include <asm/io.h> | |
13 | #include <linux/sizes.h> | |
5bc48308 HW |
14 | #include <dm.h> |
15 | #include <errno.h> | |
beedbc2e | 16 | #include <watchdog.h> |
1c631da4 | 17 | #include <wait_bit.h> |
6b57ff6f AW |
18 | #include "fsl_qspi.h" |
19 | ||
5bc48308 HW |
20 | DECLARE_GLOBAL_DATA_PTR; |
21 | ||
6b57ff6f | 22 | #define RX_BUFFER_SIZE 0x80 |
afe8e1b0 PF |
23 | #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ |
24 | defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) | |
b93ab2ee PF |
25 | #define TX_BUFFER_SIZE 0x200 |
26 | #else | |
6b57ff6f | 27 | #define TX_BUFFER_SIZE 0x40 |
b93ab2ee | 28 | #endif |
6b57ff6f | 29 | |
8770413f | 30 | #define OFFSET_BITS_MASK GENMASK(23, 0) |
6b57ff6f AW |
31 | |
32 | #define FLASH_STATUS_WEL 0x02 | |
33 | ||
34 | /* SEQID */ | |
35 | #define SEQID_WREN 1 | |
36 | #define SEQID_FAST_READ 2 | |
37 | #define SEQID_RDSR 3 | |
38 | #define SEQID_SE 4 | |
39 | #define SEQID_CHIP_ERASE 5 | |
40 | #define SEQID_PP 6 | |
41 | #define SEQID_RDID 7 | |
ba4dc8ab | 42 | #define SEQID_BE_4K 8 |
a2358783 PF |
43 | #ifdef CONFIG_SPI_FLASH_BAR |
44 | #define SEQID_BRRD 9 | |
45 | #define SEQID_BRWR 10 | |
46 | #define SEQID_RDEAR 11 | |
47 | #define SEQID_WREAR 12 | |
48 | #endif | |
febffe8d YY |
49 | #define SEQID_WRAR 13 |
50 | #define SEQID_RDAR 14 | |
6b57ff6f | 51 | |
53e3db7f PF |
52 | /* QSPI CMD */ |
53 | #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ | |
54 | #define QSPI_CMD_RDSR 0x05 /* Read status register */ | |
55 | #define QSPI_CMD_WREN 0x06 /* Write enable */ | |
56 | #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ | |
ba4dc8ab | 57 | #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ |
53e3db7f PF |
58 | #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
59 | #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ | |
60 | #define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */ | |
61 | ||
a2358783 PF |
62 | /* Used for Micron, winbond and Macronix flashes */ |
63 | #define QSPI_CMD_WREAR 0xc5 /* EAR register write */ | |
64 | #define QSPI_CMD_RDEAR 0xc8 /* EAR reigster read */ | |
65 | ||
66 | /* Used for Spansion flashes only. */ | |
67 | #define QSPI_CMD_BRRD 0x16 /* Bank register read */ | |
68 | #define QSPI_CMD_BRWR 0x17 /* Bank register write */ | |
69 | ||
febffe8d YY |
70 | /* Used for Spansion S25FS-S family flash only. */ |
71 | #define QSPI_CMD_RDAR 0x65 /* Read any device register */ | |
72 | #define QSPI_CMD_WRAR 0x71 /* Write any device register */ | |
73 | ||
53e3db7f PF |
74 | /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ |
75 | #define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ | |
76 | #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ | |
77 | #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */ | |
6b57ff6f | 78 | |
5bc48308 | 79 | /* fsl_qspi_platdata flags */ |
29e6abd9 | 80 | #define QSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) |
6b57ff6f | 81 | |
5bc48308 HW |
82 | /* default SCK frequency, unit: HZ */ |
83 | #define FSL_QSPI_DEFAULT_SCK_FREQ 50000000 | |
6b57ff6f | 84 | |
5bc48308 HW |
85 | /* QSPI max chipselect signals number */ |
86 | #define FSL_QSPI_MAX_CHIPSELECT_NUM 4 | |
87 | ||
88 | #ifdef CONFIG_DM_SPI | |
89 | /** | |
90 | * struct fsl_qspi_platdata - platform data for Freescale QSPI | |
91 | * | |
92 | * @flags: Flags for QSPI QSPI_FLAG_... | |
93 | * @speed_hz: Default SCK frequency | |
94 | * @reg_base: Base address of QSPI registers | |
95 | * @amba_base: Base address of QSPI memory mapping | |
96 | * @amba_total_size: size of QSPI memory mapping | |
97 | * @flash_num: Number of active slave devices | |
98 | * @num_chipselect: Number of QSPI chipselect signals | |
99 | */ | |
100 | struct fsl_qspi_platdata { | |
101 | u32 flags; | |
102 | u32 speed_hz; | |
bf9bffa9 YY |
103 | fdt_addr_t reg_base; |
104 | fdt_addr_t amba_base; | |
105 | fdt_size_t amba_total_size; | |
5bc48308 HW |
106 | u32 flash_num; |
107 | u32 num_chipselect; | |
108 | }; | |
b93ab2ee | 109 | #endif |
5bc48308 HW |
110 | |
111 | /** | |
112 | * struct fsl_qspi_priv - private data for Freescale QSPI | |
113 | * | |
114 | * @flags: Flags for QSPI QSPI_FLAG_... | |
115 | * @bus_clk: QSPI input clk frequency | |
116 | * @speed_hz: Default SCK frequency | |
117 | * @cur_seqid: current LUT table sequence id | |
118 | * @sf_addr: flash access offset | |
119 | * @amba_base: Base address of QSPI memory mapping of every CS | |
120 | * @amba_total_size: size of QSPI memory mapping | |
121 | * @cur_amba_base: Base address of QSPI memory mapping of current CS | |
122 | * @flash_num: Number of active slave devices | |
123 | * @num_chipselect: Number of QSPI chipselect signals | |
124 | * @regs: Point to QSPI register structure for I/O access | |
125 | */ | |
126 | struct fsl_qspi_priv { | |
127 | u32 flags; | |
128 | u32 bus_clk; | |
129 | u32 speed_hz; | |
130 | u32 cur_seqid; | |
131 | u32 sf_addr; | |
132 | u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM]; | |
133 | u32 amba_total_size; | |
134 | u32 cur_amba_base; | |
135 | u32 flash_num; | |
136 | u32 num_chipselect; | |
137 | struct fsl_qspi_regs *regs; | |
6b57ff6f AW |
138 | }; |
139 | ||
5bc48308 | 140 | #ifndef CONFIG_DM_SPI |
6b57ff6f AW |
141 | struct fsl_qspi { |
142 | struct spi_slave slave; | |
5bc48308 | 143 | struct fsl_qspi_priv priv; |
6b57ff6f | 144 | }; |
5bc48308 HW |
145 | #endif |
146 | ||
147 | static u32 qspi_read32(u32 flags, u32 *addr) | |
148 | { | |
149 | return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? | |
150 | in_be32(addr) : in_le32(addr); | |
151 | } | |
152 | ||
153 | static void qspi_write32(u32 flags, u32 *addr, u32 val) | |
154 | { | |
155 | flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? | |
156 | out_be32(addr, val) : out_le32(addr, val); | |
157 | } | |
6b57ff6f AW |
158 | |
159 | /* QSPI support swapping the flash read/write data | |
160 | * in hardware for LS102xA, but not for VF610 */ | |
161 | static inline u32 qspi_endian_xchg(u32 data) | |
162 | { | |
163 | #ifdef CONFIG_VF610 | |
164 | return swab32(data); | |
165 | #else | |
166 | return data; | |
167 | #endif | |
168 | } | |
169 | ||
5bc48308 | 170 | static void qspi_set_lut(struct fsl_qspi_priv *priv) |
6b57ff6f | 171 | { |
5bc48308 | 172 | struct fsl_qspi_regs *regs = priv->regs; |
6b57ff6f AW |
173 | u32 lut_base; |
174 | ||
175 | /* Unlock the LUT */ | |
5bc48308 HW |
176 | qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); |
177 | qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_UNLOCK); | |
6b57ff6f AW |
178 | |
179 | /* Write Enable */ | |
180 | lut_base = SEQID_WREN * 4; | |
5bc48308 | 181 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) | |
6b57ff6f | 182 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); |
5bc48308 HW |
183 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
184 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
185 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
186 | |
187 | /* Fast Read */ | |
188 | lut_base = SEQID_FAST_READ * 4; | |
a2358783 | 189 | #ifdef CONFIG_SPI_FLASH_BAR |
5bc48308 HW |
190 | qspi_write32(priv->flags, ®s->lut[lut_base], |
191 | OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | | |
192 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
a2358783 PF |
193 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); |
194 | #else | |
6b57ff6f | 195 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
5bc48308 HW |
196 | qspi_write32(priv->flags, ®s->lut[lut_base], |
197 | OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) | | |
198 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
199 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
6b57ff6f | 200 | else |
5bc48308 | 201 | qspi_write32(priv->flags, ®s->lut[lut_base], |
53e3db7f PF |
202 | OPRND0(QSPI_CMD_FAST_READ_4B) | |
203 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | | |
204 | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | | |
205 | INSTR1(LUT_ADDR)); | |
a2358783 | 206 | #endif |
5bc48308 HW |
207 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], |
208 | OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | | |
209 | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) | | |
210 | INSTR1(LUT_READ)); | |
211 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
212 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
213 | |
214 | /* Read Status */ | |
215 | lut_base = SEQID_RDSR * 4; | |
5bc48308 | 216 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) | |
6b57ff6f AW |
217 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
218 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); | |
5bc48308 HW |
219 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
220 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
221 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
222 | |
223 | /* Erase a sector */ | |
224 | lut_base = SEQID_SE * 4; | |
a2358783 | 225 | #ifdef CONFIG_SPI_FLASH_BAR |
5bc48308 | 226 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_SE) | |
a2358783 PF |
227 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
228 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
229 | #else | |
6b57ff6f | 230 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
5bc48308 HW |
231 | qspi_write32(priv->flags, ®s->lut[lut_base], |
232 | OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) | | |
233 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
234 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
6b57ff6f | 235 | else |
5bc48308 HW |
236 | qspi_write32(priv->flags, ®s->lut[lut_base], |
237 | OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) | | |
238 | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | | |
239 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
a2358783 | 240 | #endif |
5bc48308 HW |
241 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
242 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
243 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
244 | |
245 | /* Erase the whole chip */ | |
246 | lut_base = SEQID_CHIP_ERASE * 4; | |
5bc48308 HW |
247 | qspi_write32(priv->flags, ®s->lut[lut_base], |
248 | OPRND0(QSPI_CMD_CHIP_ERASE) | | |
249 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); | |
250 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); | |
251 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
252 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
253 | |
254 | /* Page Program */ | |
255 | lut_base = SEQID_PP * 4; | |
a2358783 | 256 | #ifdef CONFIG_SPI_FLASH_BAR |
5bc48308 | 257 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_PP) | |
a2358783 PF |
258 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
259 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
260 | #else | |
6b57ff6f | 261 | if (FSL_QSPI_FLASH_SIZE <= SZ_16M) |
5bc48308 HW |
262 | qspi_write32(priv->flags, ®s->lut[lut_base], |
263 | OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) | | |
264 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
265 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
6b57ff6f | 266 | else |
5bc48308 HW |
267 | qspi_write32(priv->flags, ®s->lut[lut_base], |
268 | OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) | | |
269 | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | | |
270 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
a2358783 | 271 | #endif |
afe8e1b0 PF |
272 | #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \ |
273 | defined(CONFIG_MX6ULL) || defined(CONFIG_MX7D) | |
b93ab2ee PF |
274 | /* |
275 | * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly. | |
276 | * So, Use IDATSZ in IPCR to determine the size and here set 0. | |
277 | */ | |
5bc48308 | 278 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(0) | |
b93ab2ee PF |
279 | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); |
280 | #else | |
5bc48308 HW |
281 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], |
282 | OPRND0(TX_BUFFER_SIZE) | | |
283 | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); | |
b93ab2ee | 284 | #endif |
5bc48308 HW |
285 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); |
286 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f AW |
287 | |
288 | /* READ ID */ | |
289 | lut_base = SEQID_RDID * 4; | |
5bc48308 | 290 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) | |
6b57ff6f AW |
291 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) | |
292 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); | |
5bc48308 HW |
293 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); |
294 | qspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); | |
295 | qspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); | |
6b57ff6f | 296 | |
ba4dc8ab PF |
297 | /* SUB SECTOR 4K ERASE */ |
298 | lut_base = SEQID_BE_4K * 4; | |
5bc48308 | 299 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) | |
ba4dc8ab PF |
300 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | |
301 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
302 | ||
a2358783 PF |
303 | #ifdef CONFIG_SPI_FLASH_BAR |
304 | /* | |
305 | * BRRD BRWR RDEAR WREAR are all supported, because it is hard to | |
306 | * dynamically check whether to set BRRD BRWR or RDEAR WREAR during | |
307 | * initialization. | |
308 | */ | |
309 | lut_base = SEQID_BRRD * 4; | |
5bc48308 | 310 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRRD) | |
a2358783 PF |
311 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
312 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); | |
313 | ||
314 | lut_base = SEQID_BRWR * 4; | |
5bc48308 | 315 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_BRWR) | |
a2358783 PF |
316 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
317 | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); | |
318 | ||
319 | lut_base = SEQID_RDEAR * 4; | |
5bc48308 | 320 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) | |
a2358783 PF |
321 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
322 | PAD1(LUT_PAD1) | INSTR1(LUT_READ)); | |
323 | ||
324 | lut_base = SEQID_WREAR * 4; | |
5bc48308 | 325 | qspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(QSPI_CMD_WREAR) | |
a2358783 PF |
326 | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | |
327 | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); | |
328 | #endif | |
febffe8d YY |
329 | |
330 | /* | |
331 | * Read any device register. | |
332 | * Used for Spansion S25FS-S family flash only. | |
333 | */ | |
334 | lut_base = SEQID_RDAR * 4; | |
335 | qspi_write32(priv->flags, ®s->lut[lut_base], | |
336 | OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) | | |
337 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
338 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
339 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], | |
340 | OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) | | |
341 | OPRND1(1) | PAD1(LUT_PAD1) | | |
342 | INSTR1(LUT_READ)); | |
343 | ||
344 | /* | |
345 | * Write any device register. | |
346 | * Used for Spansion S25FS-S family flash only. | |
347 | */ | |
348 | lut_base = SEQID_WRAR * 4; | |
349 | qspi_write32(priv->flags, ®s->lut[lut_base], | |
350 | OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) | | |
351 | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | | |
352 | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); | |
353 | qspi_write32(priv->flags, ®s->lut[lut_base + 1], | |
354 | OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); | |
355 | ||
6b57ff6f | 356 | /* Lock the LUT */ |
5bc48308 HW |
357 | qspi_write32(priv->flags, ®s->lutkey, LUT_KEY_VALUE); |
358 | qspi_write32(priv->flags, ®s->lckcr, QSPI_LCKCR_LOCK); | |
6b57ff6f AW |
359 | } |
360 | ||
5f7f70c1 PF |
361 | #if defined(CONFIG_SYS_FSL_QSPI_AHB) |
362 | /* | |
363 | * If we have changed the content of the flash by writing or erasing, | |
364 | * we need to invalidate the AHB buffer. If we do not do so, we may read out | |
365 | * the wrong data. The spec tells us reset the AHB domain and Serial Flash | |
366 | * domain at the same time. | |
367 | */ | |
5bc48308 | 368 | static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv) |
5f7f70c1 | 369 | { |
5bc48308 | 370 | struct fsl_qspi_regs *regs = priv->regs; |
5f7f70c1 PF |
371 | u32 reg; |
372 | ||
5bc48308 | 373 | reg = qspi_read32(priv->flags, ®s->mcr); |
5f7f70c1 | 374 | reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK; |
5bc48308 | 375 | qspi_write32(priv->flags, ®s->mcr, reg); |
5f7f70c1 PF |
376 | |
377 | /* | |
378 | * The minimum delay : 1 AHB + 2 SFCK clocks. | |
379 | * Delay 1 us is enough. | |
380 | */ | |
381 | udelay(1); | |
382 | ||
383 | reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK); | |
5bc48308 | 384 | qspi_write32(priv->flags, ®s->mcr, reg); |
5f7f70c1 PF |
385 | } |
386 | ||
387 | /* Read out the data from the AHB buffer. */ | |
5bc48308 | 388 | static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) |
5f7f70c1 | 389 | { |
5bc48308 | 390 | struct fsl_qspi_regs *regs = priv->regs; |
5f7f70c1 | 391 | u32 mcr_reg; |
04e5c6d9 | 392 | void *rx_addr = NULL; |
5f7f70c1 | 393 | |
5bc48308 | 394 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
5f7f70c1 | 395 | |
5bc48308 HW |
396 | qspi_write32(priv->flags, ®s->mcr, |
397 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
5f7f70c1 PF |
398 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
399 | ||
04e5c6d9 | 400 | rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); |
5f7f70c1 | 401 | /* Read out the data directly from the AHB buffer. */ |
04e5c6d9 | 402 | memcpy(rxbuf, rx_addr, len); |
5f7f70c1 | 403 | |
5bc48308 | 404 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
5f7f70c1 PF |
405 | } |
406 | ||
5bc48308 | 407 | static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) |
5f7f70c1 PF |
408 | { |
409 | u32 reg, reg2; | |
5bc48308 | 410 | struct fsl_qspi_regs *regs = priv->regs; |
5f7f70c1 | 411 | |
5bc48308 | 412 | reg = qspi_read32(priv->flags, ®s->mcr); |
5f7f70c1 | 413 | /* Disable the module */ |
5bc48308 | 414 | qspi_write32(priv->flags, ®s->mcr, reg | QSPI_MCR_MDIS_MASK); |
5f7f70c1 PF |
415 | |
416 | /* Set the Sampling Register for DDR */ | |
5bc48308 | 417 | reg2 = qspi_read32(priv->flags, ®s->smpr); |
5f7f70c1 PF |
418 | reg2 &= ~QSPI_SMPR_DDRSMP_MASK; |
419 | reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT); | |
5bc48308 | 420 | qspi_write32(priv->flags, ®s->smpr, reg2); |
5f7f70c1 PF |
421 | |
422 | /* Enable the module again (enable the DDR too) */ | |
423 | reg |= QSPI_MCR_DDR_EN_MASK; | |
424 | /* Enable bit 29 for imx6sx */ | |
29e6abd9 | 425 | reg |= BIT(29); |
5f7f70c1 | 426 | |
5bc48308 | 427 | qspi_write32(priv->flags, ®s->mcr, reg); |
5f7f70c1 PF |
428 | } |
429 | ||
430 | /* | |
431 | * There are two different ways to read out the data from the flash: | |
432 | * the "IP Command Read" and the "AHB Command Read". | |
433 | * | |
434 | * The IC guy suggests we use the "AHB Command Read" which is faster | |
435 | * then the "IP Command Read". (What's more is that there is a bug in | |
436 | * the "IP Command Read" in the Vybrid.) | |
437 | * | |
438 | * After we set up the registers for the "AHB Command Read", we can use | |
439 | * the memcpy to read the data directly. A "missed" access to the buffer | |
440 | * causes the controller to clear the buffer, and use the sequence pointed | |
441 | * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash. | |
442 | */ | |
5bc48308 | 443 | static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) |
5f7f70c1 | 444 | { |
5bc48308 HW |
445 | struct fsl_qspi_regs *regs = priv->regs; |
446 | ||
5f7f70c1 | 447 | /* AHB configuration for access buffer 0/1/2 .*/ |
5bc48308 HW |
448 | qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); |
449 | qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); | |
450 | qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); | |
451 | qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | | |
5f7f70c1 PF |
452 | (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); |
453 | ||
454 | /* We only use the buffer3 */ | |
5bc48308 HW |
455 | qspi_write32(priv->flags, ®s->buf0ind, 0); |
456 | qspi_write32(priv->flags, ®s->buf1ind, 0); | |
457 | qspi_write32(priv->flags, ®s->buf2ind, 0); | |
5f7f70c1 PF |
458 | |
459 | /* | |
460 | * Set the default lut sequence for AHB Read. | |
461 | * Parallel mode is disabled. | |
462 | */ | |
5bc48308 | 463 | qspi_write32(priv->flags, ®s->bfgencr, |
5f7f70c1 PF |
464 | SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); |
465 | ||
466 | /*Enable DDR Mode*/ | |
5bc48308 | 467 | qspi_enable_ddr_mode(priv); |
5f7f70c1 PF |
468 | } |
469 | #endif | |
470 | ||
a2358783 PF |
471 | #ifdef CONFIG_SPI_FLASH_BAR |
472 | /* Bank register read/write, EAR register read/write */ | |
5bc48308 | 473 | static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len) |
a2358783 | 474 | { |
5bc48308 | 475 | struct fsl_qspi_regs *regs = priv->regs; |
a2358783 PF |
476 | u32 reg, mcr_reg, data, seqid; |
477 | ||
5bc48308 HW |
478 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
479 | qspi_write32(priv->flags, ®s->mcr, | |
480 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
a2358783 | 481 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); |
5bc48308 | 482 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); |
a2358783 | 483 | |
5bc48308 | 484 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
a2358783 | 485 | |
5bc48308 | 486 | if (priv->cur_seqid == QSPI_CMD_BRRD) |
a2358783 PF |
487 | seqid = SEQID_BRRD; |
488 | else | |
489 | seqid = SEQID_RDEAR; | |
490 | ||
5bc48308 HW |
491 | qspi_write32(priv->flags, ®s->ipcr, |
492 | (seqid << QSPI_IPCR_SEQID_SHIFT) | len); | |
a2358783 PF |
493 | |
494 | /* Wait previous command complete */ | |
5bc48308 | 495 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
a2358783 PF |
496 | ; |
497 | ||
498 | while (1) { | |
4df24f2c AS |
499 | WATCHDOG_RESET(); |
500 | ||
5bc48308 | 501 | reg = qspi_read32(priv->flags, ®s->rbsr); |
a2358783 | 502 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
5bc48308 | 503 | data = qspi_read32(priv->flags, ®s->rbdr[0]); |
a2358783 PF |
504 | data = qspi_endian_xchg(data); |
505 | memcpy(rxbuf, &data, len); | |
5bc48308 HW |
506 | qspi_write32(priv->flags, ®s->mcr, |
507 | qspi_read32(priv->flags, ®s->mcr) | | |
a2358783 PF |
508 | QSPI_MCR_CLR_RXF_MASK); |
509 | break; | |
510 | } | |
511 | } | |
512 | ||
5bc48308 | 513 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
a2358783 PF |
514 | } |
515 | #endif | |
516 | ||
5bc48308 | 517 | static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) |
6b57ff6f | 518 | { |
5bc48308 | 519 | struct fsl_qspi_regs *regs = priv->regs; |
5207014d GQ |
520 | u32 mcr_reg, rbsr_reg, data, size; |
521 | int i; | |
6b57ff6f | 522 | |
5bc48308 HW |
523 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
524 | qspi_write32(priv->flags, ®s->mcr, | |
525 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
526 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); | |
527 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); | |
6b57ff6f | 528 | |
5bc48308 | 529 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
6b57ff6f | 530 | |
5bc48308 HW |
531 | qspi_write32(priv->flags, ®s->ipcr, |
532 | (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0); | |
533 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
534 | ; |
535 | ||
536 | i = 0; | |
5207014d | 537 | while ((RX_BUFFER_SIZE >= len) && (len > 0)) { |
4df24f2c AS |
538 | WATCHDOG_RESET(); |
539 | ||
5bc48308 | 540 | rbsr_reg = qspi_read32(priv->flags, ®s->rbsr); |
6b57ff6f | 541 | if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) { |
5bc48308 | 542 | data = qspi_read32(priv->flags, ®s->rbdr[i]); |
6b57ff6f | 543 | data = qspi_endian_xchg(data); |
5207014d GQ |
544 | size = (len < 4) ? len : 4; |
545 | memcpy(rxbuf, &data, size); | |
546 | len -= size; | |
6b57ff6f | 547 | rxbuf++; |
6b57ff6f AW |
548 | i++; |
549 | } | |
550 | } | |
551 | ||
5bc48308 | 552 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
6b57ff6f AW |
553 | } |
554 | ||
5f7f70c1 | 555 | /* If not use AHB read, read data from ip interface */ |
5bc48308 | 556 | static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len) |
6b57ff6f | 557 | { |
5bc48308 | 558 | struct fsl_qspi_regs *regs = priv->regs; |
6b57ff6f AW |
559 | u32 mcr_reg, data; |
560 | int i, size; | |
561 | u32 to_or_from; | |
febffe8d YY |
562 | u32 seqid; |
563 | ||
564 | if (priv->cur_seqid == QSPI_CMD_RDAR) | |
565 | seqid = SEQID_RDAR; | |
566 | else | |
567 | seqid = SEQID_FAST_READ; | |
6b57ff6f | 568 | |
5bc48308 HW |
569 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
570 | qspi_write32(priv->flags, ®s->mcr, | |
571 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
572 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); | |
573 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); | |
6b57ff6f | 574 | |
5bc48308 | 575 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
6b57ff6f AW |
576 | |
577 | while (len > 0) { | |
beedbc2e AS |
578 | WATCHDOG_RESET(); |
579 | ||
5bc48308 | 580 | qspi_write32(priv->flags, ®s->sfar, to_or_from); |
6b57ff6f AW |
581 | |
582 | size = (len > RX_BUFFER_SIZE) ? | |
583 | RX_BUFFER_SIZE : len; | |
584 | ||
5bc48308 | 585 | qspi_write32(priv->flags, ®s->ipcr, |
febffe8d | 586 | (seqid << QSPI_IPCR_SEQID_SHIFT) | |
5bc48308 HW |
587 | size); |
588 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
589 | ; |
590 | ||
591 | to_or_from += size; | |
592 | len -= size; | |
593 | ||
594 | i = 0; | |
595 | while ((RX_BUFFER_SIZE >= size) && (size > 0)) { | |
5bc48308 | 596 | data = qspi_read32(priv->flags, ®s->rbdr[i]); |
6b57ff6f | 597 | data = qspi_endian_xchg(data); |
febffe8d YY |
598 | if (size < 4) |
599 | memcpy(rxbuf, &data, size); | |
600 | else | |
601 | memcpy(rxbuf, &data, 4); | |
6b57ff6f AW |
602 | rxbuf++; |
603 | size -= 4; | |
604 | i++; | |
605 | } | |
5bc48308 HW |
606 | qspi_write32(priv->flags, ®s->mcr, |
607 | qspi_read32(priv->flags, ®s->mcr) | | |
608 | QSPI_MCR_CLR_RXF_MASK); | |
6b57ff6f AW |
609 | } |
610 | ||
5bc48308 | 611 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
6b57ff6f AW |
612 | } |
613 | ||
5bc48308 | 614 | static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) |
6b57ff6f | 615 | { |
5bc48308 | 616 | struct fsl_qspi_regs *regs = priv->regs; |
a2358783 | 617 | u32 mcr_reg, data, reg, status_reg, seqid; |
6b57ff6f AW |
618 | int i, size, tx_size; |
619 | u32 to_or_from = 0; | |
620 | ||
5bc48308 HW |
621 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
622 | qspi_write32(priv->flags, ®s->mcr, | |
623 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
624 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); | |
625 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); | |
6b57ff6f AW |
626 | |
627 | status_reg = 0; | |
628 | while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) { | |
beedbc2e AS |
629 | WATCHDOG_RESET(); |
630 | ||
5bc48308 HW |
631 | qspi_write32(priv->flags, ®s->ipcr, |
632 | (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); | |
633 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
634 | ; |
635 | ||
5bc48308 HW |
636 | qspi_write32(priv->flags, ®s->ipcr, |
637 | (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1); | |
638 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
639 | ; |
640 | ||
5bc48308 | 641 | reg = qspi_read32(priv->flags, ®s->rbsr); |
6b57ff6f | 642 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
5bc48308 | 643 | status_reg = qspi_read32(priv->flags, ®s->rbdr[0]); |
6b57ff6f AW |
644 | status_reg = qspi_endian_xchg(status_reg); |
645 | } | |
5bc48308 HW |
646 | qspi_write32(priv->flags, ®s->mcr, |
647 | qspi_read32(priv->flags, ®s->mcr) | | |
648 | QSPI_MCR_CLR_RXF_MASK); | |
6b57ff6f AW |
649 | } |
650 | ||
a2358783 PF |
651 | /* Default is page programming */ |
652 | seqid = SEQID_PP; | |
febffe8d YY |
653 | if (priv->cur_seqid == QSPI_CMD_WRAR) |
654 | seqid = SEQID_WRAR; | |
a2358783 | 655 | #ifdef CONFIG_SPI_FLASH_BAR |
5bc48308 | 656 | if (priv->cur_seqid == QSPI_CMD_BRWR) |
a2358783 | 657 | seqid = SEQID_BRWR; |
5bc48308 | 658 | else if (priv->cur_seqid == QSPI_CMD_WREAR) |
a2358783 PF |
659 | seqid = SEQID_WREAR; |
660 | #endif | |
661 | ||
5bc48308 | 662 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
a2358783 | 663 | |
5bc48308 | 664 | qspi_write32(priv->flags, ®s->sfar, to_or_from); |
6b57ff6f AW |
665 | |
666 | tx_size = (len > TX_BUFFER_SIZE) ? | |
667 | TX_BUFFER_SIZE : len; | |
668 | ||
10509987 SG |
669 | size = tx_size / 16; |
670 | /* | |
671 | * There must be atleast 128bit data | |
672 | * available in TX FIFO for any pop operation | |
673 | */ | |
674 | if (tx_size % 16) | |
675 | size++; | |
676 | for (i = 0; i < size * 4; i++) { | |
a2358783 PF |
677 | memcpy(&data, txbuf, 4); |
678 | data = qspi_endian_xchg(data); | |
5bc48308 | 679 | qspi_write32(priv->flags, ®s->tbdr, data); |
a2358783 | 680 | txbuf += 4; |
6b57ff6f AW |
681 | } |
682 | ||
5bc48308 HW |
683 | qspi_write32(priv->flags, ®s->ipcr, |
684 | (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size); | |
685 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
686 | ; |
687 | ||
5bc48308 | 688 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
6b57ff6f AW |
689 | } |
690 | ||
940d2b89 | 691 | static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) |
6b57ff6f | 692 | { |
5bc48308 | 693 | struct fsl_qspi_regs *regs = priv->regs; |
6b57ff6f AW |
694 | u32 mcr_reg, reg, data; |
695 | ||
5bc48308 HW |
696 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
697 | qspi_write32(priv->flags, ®s->mcr, | |
698 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
699 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); | |
700 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); | |
6b57ff6f | 701 | |
5bc48308 | 702 | qspi_write32(priv->flags, ®s->sfar, priv->cur_amba_base); |
6b57ff6f | 703 | |
5bc48308 HW |
704 | qspi_write32(priv->flags, ®s->ipcr, |
705 | (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); | |
706 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
707 | ; |
708 | ||
709 | while (1) { | |
4df24f2c AS |
710 | WATCHDOG_RESET(); |
711 | ||
5bc48308 | 712 | reg = qspi_read32(priv->flags, ®s->rbsr); |
6b57ff6f | 713 | if (reg & QSPI_RBSR_RDBFL_MASK) { |
5bc48308 | 714 | data = qspi_read32(priv->flags, ®s->rbdr[0]); |
6b57ff6f | 715 | data = qspi_endian_xchg(data); |
940d2b89 | 716 | memcpy(rxbuf, &data, len); |
5bc48308 HW |
717 | qspi_write32(priv->flags, ®s->mcr, |
718 | qspi_read32(priv->flags, ®s->mcr) | | |
719 | QSPI_MCR_CLR_RXF_MASK); | |
6b57ff6f AW |
720 | break; |
721 | } | |
722 | } | |
723 | ||
5bc48308 | 724 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
6b57ff6f AW |
725 | } |
726 | ||
5bc48308 | 727 | static void qspi_op_erase(struct fsl_qspi_priv *priv) |
6b57ff6f | 728 | { |
5bc48308 | 729 | struct fsl_qspi_regs *regs = priv->regs; |
6b57ff6f AW |
730 | u32 mcr_reg; |
731 | u32 to_or_from = 0; | |
732 | ||
5bc48308 HW |
733 | mcr_reg = qspi_read32(priv->flags, ®s->mcr); |
734 | qspi_write32(priv->flags, ®s->mcr, | |
735 | QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | | |
736 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); | |
737 | qspi_write32(priv->flags, ®s->rbct, QSPI_RBCT_RXBRD_USEIPS); | |
6b57ff6f | 738 | |
5bc48308 HW |
739 | to_or_from = priv->sf_addr + priv->cur_amba_base; |
740 | qspi_write32(priv->flags, ®s->sfar, to_or_from); | |
6b57ff6f | 741 | |
5bc48308 HW |
742 | qspi_write32(priv->flags, ®s->ipcr, |
743 | (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0); | |
744 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) | |
6b57ff6f AW |
745 | ; |
746 | ||
5bc48308 HW |
747 | if (priv->cur_seqid == QSPI_CMD_SE) { |
748 | qspi_write32(priv->flags, ®s->ipcr, | |
ba4dc8ab | 749 | (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0); |
5bc48308 HW |
750 | } else if (priv->cur_seqid == QSPI_CMD_BE_4K) { |
751 | qspi_write32(priv->flags, ®s->ipcr, | |
ba4dc8ab PF |
752 | (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0); |
753 | } | |
5bc48308 | 754 | while (qspi_read32(priv->flags, ®s->sr) & QSPI_SR_BUSY_MASK) |
6b57ff6f AW |
755 | ; |
756 | ||
5bc48308 | 757 | qspi_write32(priv->flags, ®s->mcr, mcr_reg); |
6b57ff6f AW |
758 | } |
759 | ||
5bc48308 | 760 | int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, |
6b57ff6f AW |
761 | const void *dout, void *din, unsigned long flags) |
762 | { | |
6b57ff6f | 763 | u32 bytes = DIV_ROUND_UP(bitlen, 8); |
a2358783 | 764 | static u32 wr_sfaddr; |
6b57ff6f AW |
765 | u32 txbuf; |
766 | ||
4df24f2c AS |
767 | WATCHDOG_RESET(); |
768 | ||
6b57ff6f | 769 | if (dout) { |
a2358783 | 770 | if (flags & SPI_XFER_BEGIN) { |
5bc48308 | 771 | priv->cur_seqid = *(u8 *)dout; |
a2358783 PF |
772 | memcpy(&txbuf, dout, 4); |
773 | } | |
6b57ff6f AW |
774 | |
775 | if (flags == SPI_XFER_END) { | |
5bc48308 HW |
776 | priv->sf_addr = wr_sfaddr; |
777 | qspi_op_write(priv, (u8 *)dout, bytes); | |
6b57ff6f AW |
778 | return 0; |
779 | } | |
780 | ||
febffe8d YY |
781 | if (priv->cur_seqid == QSPI_CMD_FAST_READ || |
782 | priv->cur_seqid == QSPI_CMD_RDAR) { | |
5bc48308 HW |
783 | priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; |
784 | } else if ((priv->cur_seqid == QSPI_CMD_SE) || | |
785 | (priv->cur_seqid == QSPI_CMD_BE_4K)) { | |
786 | priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK; | |
787 | qspi_op_erase(priv); | |
febffe8d YY |
788 | } else if (priv->cur_seqid == QSPI_CMD_PP || |
789 | priv->cur_seqid == QSPI_CMD_WRAR) { | |
a2358783 | 790 | wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK; |
5bc48308 HW |
791 | } else if ((priv->cur_seqid == QSPI_CMD_BRWR) || |
792 | (priv->cur_seqid == QSPI_CMD_WREAR)) { | |
a2358783 | 793 | #ifdef CONFIG_SPI_FLASH_BAR |
a2358783 | 794 | wr_sfaddr = 0; |
a2358783 | 795 | #endif |
5bc48308 | 796 | } |
6b57ff6f AW |
797 | } |
798 | ||
799 | if (din) { | |
5bc48308 | 800 | if (priv->cur_seqid == QSPI_CMD_FAST_READ) { |
5f7f70c1 | 801 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
5bc48308 | 802 | qspi_ahb_read(priv, din, bytes); |
5f7f70c1 | 803 | #else |
5bc48308 | 804 | qspi_op_read(priv, din, bytes); |
5f7f70c1 | 805 | #endif |
febffe8d YY |
806 | } else if (priv->cur_seqid == QSPI_CMD_RDAR) { |
807 | qspi_op_read(priv, din, bytes); | |
5bc48308 HW |
808 | } else if (priv->cur_seqid == QSPI_CMD_RDID) |
809 | qspi_op_rdid(priv, din, bytes); | |
810 | else if (priv->cur_seqid == QSPI_CMD_RDSR) | |
940d2b89 | 811 | qspi_op_rdsr(priv, din, bytes); |
a2358783 | 812 | #ifdef CONFIG_SPI_FLASH_BAR |
5bc48308 HW |
813 | else if ((priv->cur_seqid == QSPI_CMD_BRRD) || |
814 | (priv->cur_seqid == QSPI_CMD_RDEAR)) { | |
815 | priv->sf_addr = 0; | |
816 | qspi_op_rdbank(priv, din, bytes); | |
a2358783 PF |
817 | } |
818 | #endif | |
6b57ff6f AW |
819 | } |
820 | ||
5f7f70c1 | 821 | #ifdef CONFIG_SYS_FSL_QSPI_AHB |
5bc48308 HW |
822 | if ((priv->cur_seqid == QSPI_CMD_SE) || |
823 | (priv->cur_seqid == QSPI_CMD_PP) || | |
824 | (priv->cur_seqid == QSPI_CMD_BE_4K) || | |
825 | (priv->cur_seqid == QSPI_CMD_WREAR) || | |
826 | (priv->cur_seqid == QSPI_CMD_BRWR)) | |
827 | qspi_ahb_invalid(priv); | |
828 | #endif | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
833 | void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable) | |
834 | { | |
835 | u32 mcr_val; | |
836 | ||
837 | mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); | |
838 | if (disable) | |
839 | mcr_val |= QSPI_MCR_MDIS_MASK; | |
840 | else | |
841 | mcr_val &= ~QSPI_MCR_MDIS_MASK; | |
842 | qspi_write32(priv->flags, &priv->regs->mcr, mcr_val); | |
843 | } | |
844 | ||
845 | void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) | |
846 | { | |
847 | u32 smpr_val; | |
848 | ||
849 | smpr_val = qspi_read32(priv->flags, &priv->regs->smpr); | |
850 | smpr_val &= ~clear_bits; | |
851 | smpr_val |= set_bits; | |
852 | qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); | |
853 | } | |
854 | #ifndef CONFIG_DM_SPI | |
855 | static unsigned long spi_bases[] = { | |
856 | QSPI0_BASE_ADDR, | |
857 | #ifdef CONFIG_MX6SX | |
858 | QSPI1_BASE_ADDR, | |
859 | #endif | |
860 | }; | |
861 | ||
862 | static unsigned long amba_bases[] = { | |
863 | QSPI0_AMBA_BASE, | |
864 | #ifdef CONFIG_MX6SX | |
865 | QSPI1_AMBA_BASE, | |
866 | #endif | |
867 | }; | |
868 | ||
869 | static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) | |
870 | { | |
871 | return container_of(slave, struct fsl_qspi, slave); | |
872 | } | |
873 | ||
874 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | |
875 | unsigned int max_hz, unsigned int mode) | |
876 | { | |
3c6b1767 | 877 | u32 mcr_val; |
5bc48308 HW |
878 | struct fsl_qspi *qspi; |
879 | struct fsl_qspi_regs *regs; | |
880 | u32 total_size; | |
881 | ||
882 | if (bus >= ARRAY_SIZE(spi_bases)) | |
883 | return NULL; | |
884 | ||
885 | if (cs >= FSL_QSPI_FLASH_NUM) | |
886 | return NULL; | |
887 | ||
888 | qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); | |
889 | if (!qspi) | |
890 | return NULL; | |
891 | ||
892 | #ifdef CONFIG_SYS_FSL_QSPI_BE | |
893 | qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; | |
894 | #endif | |
895 | ||
896 | regs = (struct fsl_qspi_regs *)spi_bases[bus]; | |
897 | qspi->priv.regs = regs; | |
898 | /* | |
899 | * According cs, use different amba_base to choose the | |
900 | * corresponding flash devices. | |
901 | * | |
902 | * If not, only one flash device is used even if passing | |
903 | * different cs using `sf probe` | |
904 | */ | |
905 | qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; | |
906 | ||
907 | qspi->slave.max_write_size = TX_BUFFER_SIZE; | |
908 | ||
3c6b1767 | 909 | mcr_val = qspi_read32(qspi->priv.flags, ®s->mcr); |
afe8e1b0 PF |
910 | |
911 | /* Set endianness to LE for i.mx */ | |
912 | if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) | |
913 | mcr_val = QSPI_MCR_END_CFD_LE; | |
914 | ||
5bc48308 | 915 | qspi_write32(qspi->priv.flags, ®s->mcr, |
3c6b1767 YS |
916 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | |
917 | (mcr_val & QSPI_MCR_END_CFD_MASK)); | |
5bc48308 HW |
918 | |
919 | qspi_cfg_smpr(&qspi->priv, | |
920 | ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | | |
921 | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); | |
922 | ||
923 | total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; | |
924 | /* | |
925 | * Any read access to non-implemented addresses will provide | |
926 | * undefined results. | |
927 | * | |
928 | * In case single die flash devices, TOP_ADDR_MEMA2 and | |
929 | * TOP_ADDR_MEMB2 should be initialized/programmed to | |
930 | * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, | |
931 | * setting the size of these devices to 0. This would ensure | |
932 | * that the complete memory map is assigned to only one flash device. | |
933 | */ | |
934 | qspi_write32(qspi->priv.flags, ®s->sfa1ad, | |
935 | FSL_QSPI_FLASH_SIZE | amba_bases[bus]); | |
936 | qspi_write32(qspi->priv.flags, ®s->sfa2ad, | |
937 | FSL_QSPI_FLASH_SIZE | amba_bases[bus]); | |
938 | qspi_write32(qspi->priv.flags, ®s->sfb1ad, | |
939 | total_size | amba_bases[bus]); | |
940 | qspi_write32(qspi->priv.flags, ®s->sfb2ad, | |
941 | total_size | amba_bases[bus]); | |
942 | ||
943 | qspi_set_lut(&qspi->priv); | |
944 | ||
945 | #ifdef CONFIG_SYS_FSL_QSPI_AHB | |
946 | qspi_init_ahb_read(&qspi->priv); | |
5f7f70c1 PF |
947 | #endif |
948 | ||
5bc48308 HW |
949 | qspi_module_disable(&qspi->priv, 0); |
950 | ||
951 | return &qspi->slave; | |
952 | } | |
953 | ||
954 | void spi_free_slave(struct spi_slave *slave) | |
955 | { | |
956 | struct fsl_qspi *qspi = to_qspi_spi(slave); | |
957 | ||
958 | free(qspi); | |
959 | } | |
960 | ||
961 | int spi_claim_bus(struct spi_slave *slave) | |
962 | { | |
6b57ff6f AW |
963 | return 0; |
964 | } | |
965 | ||
966 | void spi_release_bus(struct spi_slave *slave) | |
967 | { | |
968 | /* Nothing to do */ | |
969 | } | |
5bc48308 HW |
970 | |
971 | int spi_xfer(struct spi_slave *slave, unsigned int bitlen, | |
972 | const void *dout, void *din, unsigned long flags) | |
973 | { | |
974 | struct fsl_qspi *qspi = to_qspi_spi(slave); | |
975 | ||
976 | return qspi_xfer(&qspi->priv, bitlen, dout, din, flags); | |
977 | } | |
978 | ||
979 | void spi_init(void) | |
980 | { | |
981 | /* Nothing to do */ | |
982 | } | |
983 | #else | |
984 | static int fsl_qspi_child_pre_probe(struct udevice *dev) | |
985 | { | |
bcbe3d15 | 986 | struct spi_slave *slave = dev_get_parent_priv(dev); |
5bc48308 HW |
987 | |
988 | slave->max_write_size = TX_BUFFER_SIZE; | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | static int fsl_qspi_probe(struct udevice *bus) | |
994 | { | |
3c6b1767 | 995 | u32 mcr_val; |
4e147418 | 996 | u32 amba_size_per_chip; |
5bc48308 HW |
997 | struct fsl_qspi_platdata *plat = dev_get_platdata(bus); |
998 | struct fsl_qspi_priv *priv = dev_get_priv(bus); | |
999 | struct dm_spi_bus *dm_spi_bus; | |
1c631da4 | 1000 | int i, ret; |
5bc48308 HW |
1001 | |
1002 | dm_spi_bus = bus->uclass_priv; | |
1003 | ||
1004 | dm_spi_bus->max_hz = plat->speed_hz; | |
1005 | ||
c2a4cb17 | 1006 | priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base; |
5bc48308 HW |
1007 | priv->flags = plat->flags; |
1008 | ||
1009 | priv->speed_hz = plat->speed_hz; | |
bf9bffa9 YY |
1010 | /* |
1011 | * QSPI SFADR width is 32bits, the max dest addr is 4GB-1. | |
1012 | * AMBA memory zone should be located on the 0~4GB space | |
1013 | * even on a 64bits cpu. | |
1014 | */ | |
1015 | priv->amba_base[0] = (u32)plat->amba_base; | |
1016 | priv->amba_total_size = (u32)plat->amba_total_size; | |
5bc48308 HW |
1017 | priv->flash_num = plat->flash_num; |
1018 | priv->num_chipselect = plat->num_chipselect; | |
1019 | ||
1c631da4 | 1020 | /* make sure controller is not busy anywhere */ |
48263504 ÁFR |
1021 | ret = wait_for_bit_le32(&priv->regs->sr, |
1022 | QSPI_SR_BUSY_MASK | | |
1023 | QSPI_SR_AHB_ACC_MASK | | |
1024 | QSPI_SR_IP_ACC_MASK, | |
1025 | false, 100, false); | |
1c631da4 SG |
1026 | |
1027 | if (ret) { | |
1028 | debug("ERROR : The controller is busy\n"); | |
1029 | return ret; | |
1030 | } | |
1031 | ||
3c6b1767 | 1032 | mcr_val = qspi_read32(priv->flags, &priv->regs->mcr); |
afe8e1b0 PF |
1033 | |
1034 | /* Set endianness to LE for i.mx */ | |
1035 | if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) | |
1036 | mcr_val = QSPI_MCR_END_CFD_LE; | |
1037 | ||
5bc48308 | 1038 | qspi_write32(priv->flags, &priv->regs->mcr, |
3c6b1767 YS |
1039 | QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | |
1040 | (mcr_val & QSPI_MCR_END_CFD_MASK)); | |
5bc48308 HW |
1041 | |
1042 | qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | | |
1043 | QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); | |
1044 | ||
4e147418 YY |
1045 | /* |
1046 | * Assign AMBA memory zone for every chipselect | |
1047 | * QuadSPI has two channels, every channel has two chipselects. | |
1048 | * If the property 'num-cs' in dts is 2, the AMBA memory will be divided | |
1049 | * into two parts and assign to every channel. This indicate that every | |
1050 | * channel only has one valid chipselect. | |
1051 | * If the property 'num-cs' in dts is 4, the AMBA memory will be divided | |
1052 | * into four parts and assign to every chipselect. | |
1053 | * Every channel will has two valid chipselects. | |
1054 | */ | |
1055 | amba_size_per_chip = priv->amba_total_size >> | |
1056 | (priv->num_chipselect >> 1); | |
1057 | for (i = 1 ; i < priv->num_chipselect ; i++) | |
1058 | priv->amba_base[i] = | |
1059 | amba_size_per_chip + priv->amba_base[i - 1]; | |
1060 | ||
5bc48308 HW |
1061 | /* |
1062 | * Any read access to non-implemented addresses will provide | |
1063 | * undefined results. | |
1064 | * | |
1065 | * In case single die flash devices, TOP_ADDR_MEMA2 and | |
1066 | * TOP_ADDR_MEMB2 should be initialized/programmed to | |
1067 | * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, | |
1068 | * setting the size of these devices to 0. This would ensure | |
1069 | * that the complete memory map is assigned to only one flash device. | |
1070 | */ | |
38a5c57a SG |
1071 | qspi_write32(priv->flags, &priv->regs->sfa1ad, |
1072 | priv->amba_base[0] + amba_size_per_chip); | |
4e147418 | 1073 | switch (priv->num_chipselect) { |
38a5c57a SG |
1074 | case 1: |
1075 | break; | |
4e147418 YY |
1076 | case 2: |
1077 | qspi_write32(priv->flags, &priv->regs->sfa2ad, | |
1078 | priv->amba_base[1]); | |
1079 | qspi_write32(priv->flags, &priv->regs->sfb1ad, | |
1080 | priv->amba_base[1] + amba_size_per_chip); | |
1081 | qspi_write32(priv->flags, &priv->regs->sfb2ad, | |
1082 | priv->amba_base[1] + amba_size_per_chip); | |
1083 | break; | |
1084 | case 4: | |
1085 | qspi_write32(priv->flags, &priv->regs->sfa2ad, | |
1086 | priv->amba_base[2]); | |
1087 | qspi_write32(priv->flags, &priv->regs->sfb1ad, | |
1088 | priv->amba_base[3]); | |
1089 | qspi_write32(priv->flags, &priv->regs->sfb2ad, | |
1090 | priv->amba_base[3] + amba_size_per_chip); | |
1091 | break; | |
1092 | default: | |
1093 | debug("Error: Unsupported chipselect number %u!\n", | |
1094 | priv->num_chipselect); | |
1095 | qspi_module_disable(priv, 1); | |
1096 | return -EINVAL; | |
1097 | } | |
5bc48308 HW |
1098 | |
1099 | qspi_set_lut(priv); | |
1100 | ||
1101 | #ifdef CONFIG_SYS_FSL_QSPI_AHB | |
1102 | qspi_init_ahb_read(priv); | |
1103 | #endif | |
1104 | ||
1105 | qspi_module_disable(priv, 0); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | static int fsl_qspi_ofdata_to_platdata(struct udevice *bus) | |
1111 | { | |
bf9bffa9 | 1112 | struct fdt_resource res_regs, res_mem; |
5bc48308 HW |
1113 | struct fsl_qspi_platdata *plat = bus->platdata; |
1114 | const void *blob = gd->fdt_blob; | |
e160f7d4 | 1115 | int node = dev_of_offset(bus); |
5bc48308 HW |
1116 | int ret, flash_num = 0, subnode; |
1117 | ||
1118 | if (fdtdec_get_bool(blob, node, "big-endian")) | |
1119 | plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; | |
1120 | ||
bf9bffa9 YY |
1121 | ret = fdt_get_named_resource(blob, node, "reg", "reg-names", |
1122 | "QuadSPI", &res_regs); | |
1123 | if (ret) { | |
1124 | debug("Error: can't get regs base addresses(ret = %d)!\n", ret); | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | ret = fdt_get_named_resource(blob, node, "reg", "reg-names", | |
1128 | "QuadSPI-memory", &res_mem); | |
5bc48308 | 1129 | if (ret) { |
bf9bffa9 | 1130 | debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); |
5bc48308 HW |
1131 | return -ENOMEM; |
1132 | } | |
1133 | ||
1134 | /* Count flash numbers */ | |
df87e6b1 | 1135 | fdt_for_each_subnode(subnode, blob, node) |
5bc48308 HW |
1136 | ++flash_num; |
1137 | ||
1138 | if (flash_num == 0) { | |
1139 | debug("Error: Missing flashes!\n"); | |
1140 | return -ENODEV; | |
1141 | } | |
1142 | ||
1143 | plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", | |
1144 | FSL_QSPI_DEFAULT_SCK_FREQ); | |
1145 | plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", | |
1146 | FSL_QSPI_MAX_CHIPSELECT_NUM); | |
1147 | ||
bf9bffa9 YY |
1148 | plat->reg_base = res_regs.start; |
1149 | plat->amba_base = res_mem.start; | |
1150 | plat->amba_total_size = res_mem.end - res_mem.start + 1; | |
5bc48308 HW |
1151 | plat->flash_num = flash_num; |
1152 | ||
bf9bffa9 | 1153 | debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n", |
5bc48308 | 1154 | __func__, |
bf9bffa9 YY |
1155 | (u64)plat->reg_base, |
1156 | (u64)plat->amba_base, | |
1157 | (u64)plat->amba_total_size, | |
5bc48308 HW |
1158 | plat->speed_hz, |
1159 | plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" | |
1160 | ); | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, | |
1166 | const void *dout, void *din, unsigned long flags) | |
1167 | { | |
1168 | struct fsl_qspi_priv *priv; | |
1169 | struct udevice *bus; | |
1170 | ||
1171 | bus = dev->parent; | |
1172 | priv = dev_get_priv(bus); | |
1173 | ||
1174 | return qspi_xfer(priv, bitlen, dout, din, flags); | |
1175 | } | |
1176 | ||
1177 | static int fsl_qspi_claim_bus(struct udevice *dev) | |
1178 | { | |
1179 | struct fsl_qspi_priv *priv; | |
1180 | struct udevice *bus; | |
1181 | struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); | |
1c631da4 | 1182 | int ret; |
5bc48308 HW |
1183 | |
1184 | bus = dev->parent; | |
1185 | priv = dev_get_priv(bus); | |
1186 | ||
1c631da4 | 1187 | /* make sure controller is not busy anywhere */ |
48263504 ÁFR |
1188 | ret = wait_for_bit_le32(&priv->regs->sr, |
1189 | QSPI_SR_BUSY_MASK | | |
1190 | QSPI_SR_AHB_ACC_MASK | | |
1191 | QSPI_SR_IP_ACC_MASK, | |
1192 | false, 100, false); | |
1c631da4 SG |
1193 | |
1194 | if (ret) { | |
1195 | debug("ERROR : The controller is busy\n"); | |
1196 | return ret; | |
1197 | } | |
1198 | ||
4e147418 | 1199 | priv->cur_amba_base = priv->amba_base[slave_plat->cs]; |
5bc48308 HW |
1200 | |
1201 | qspi_module_disable(priv, 0); | |
1202 | ||
1203 | return 0; | |
1204 | } | |
1205 | ||
1206 | static int fsl_qspi_release_bus(struct udevice *dev) | |
1207 | { | |
1208 | struct fsl_qspi_priv *priv; | |
1209 | struct udevice *bus; | |
1210 | ||
1211 | bus = dev->parent; | |
1212 | priv = dev_get_priv(bus); | |
1213 | ||
1214 | qspi_module_disable(priv, 1); | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static int fsl_qspi_set_speed(struct udevice *bus, uint speed) | |
1220 | { | |
1221 | /* Nothing to do */ | |
1222 | return 0; | |
1223 | } | |
1224 | ||
1225 | static int fsl_qspi_set_mode(struct udevice *bus, uint mode) | |
1226 | { | |
1227 | /* Nothing to do */ | |
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | static const struct dm_spi_ops fsl_qspi_ops = { | |
1232 | .claim_bus = fsl_qspi_claim_bus, | |
1233 | .release_bus = fsl_qspi_release_bus, | |
1234 | .xfer = fsl_qspi_xfer, | |
1235 | .set_speed = fsl_qspi_set_speed, | |
1236 | .set_mode = fsl_qspi_set_mode, | |
1237 | }; | |
1238 | ||
1239 | static const struct udevice_id fsl_qspi_ids[] = { | |
1240 | { .compatible = "fsl,vf610-qspi" }, | |
1241 | { .compatible = "fsl,imx6sx-qspi" }, | |
afe8e1b0 PF |
1242 | { .compatible = "fsl,imx6ul-qspi" }, |
1243 | { .compatible = "fsl,imx7d-qspi" }, | |
5bc48308 HW |
1244 | { } |
1245 | }; | |
1246 | ||
1247 | U_BOOT_DRIVER(fsl_qspi) = { | |
1248 | .name = "fsl_qspi", | |
1249 | .id = UCLASS_SPI, | |
1250 | .of_match = fsl_qspi_ids, | |
1251 | .ops = &fsl_qspi_ops, | |
1252 | .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata, | |
1253 | .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata), | |
1254 | .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv), | |
1255 | .probe = fsl_qspi_probe, | |
1256 | .child_pre_probe = fsl_qspi_child_pre_probe, | |
1257 | }; | |
1258 | #endif |