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1853030e SG |
1 | /* |
2 | * Copyright (c) 2011-12 The Chromium OS Authors. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
1853030e SG |
5 | * |
6 | * This file is derived from the flashrom project. | |
7 | */ | |
9eb4339b | 8 | |
1853030e | 9 | #include <common.h> |
ba457562 | 10 | #include <dm.h> |
5093badb | 11 | #include <errno.h> |
1853030e | 12 | #include <malloc.h> |
f2b85ab5 | 13 | #include <pch.h> |
1853030e SG |
14 | #include <pci.h> |
15 | #include <pci_ids.h> | |
f2b85ab5 | 16 | #include <spi.h> |
1853030e SG |
17 | #include <asm/io.h> |
18 | ||
19 | #include "ich.h" | |
20 | ||
1f9eb59d BM |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
fffe25db SG |
23 | #ifdef DEBUG_TRACE |
24 | #define debug_trace(fmt, args...) debug(fmt, ##args) | |
25 | #else | |
26 | #define debug_trace(x, args...) | |
27 | #endif | |
28 | ||
ba457562 | 29 | static u8 ich_readb(struct ich_spi_priv *priv, int reg) |
1853030e | 30 | { |
ba457562 | 31 | u8 value = readb(priv->base + reg); |
1853030e | 32 | |
fffe25db | 33 | debug_trace("read %2.2x from %4.4x\n", value, reg); |
1853030e SG |
34 | |
35 | return value; | |
36 | } | |
37 | ||
ba457562 | 38 | static u16 ich_readw(struct ich_spi_priv *priv, int reg) |
1853030e | 39 | { |
ba457562 | 40 | u16 value = readw(priv->base + reg); |
1853030e | 41 | |
fffe25db | 42 | debug_trace("read %4.4x from %4.4x\n", value, reg); |
1853030e SG |
43 | |
44 | return value; | |
45 | } | |
46 | ||
ba457562 | 47 | static u32 ich_readl(struct ich_spi_priv *priv, int reg) |
1853030e | 48 | { |
ba457562 | 49 | u32 value = readl(priv->base + reg); |
1853030e | 50 | |
fffe25db | 51 | debug_trace("read %8.8x from %4.4x\n", value, reg); |
1853030e SG |
52 | |
53 | return value; | |
54 | } | |
55 | ||
ba457562 | 56 | static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg) |
1853030e | 57 | { |
ba457562 | 58 | writeb(value, priv->base + reg); |
fffe25db | 59 | debug_trace("wrote %2.2x to %4.4x\n", value, reg); |
1853030e SG |
60 | } |
61 | ||
ba457562 | 62 | static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg) |
1853030e | 63 | { |
ba457562 | 64 | writew(value, priv->base + reg); |
fffe25db | 65 | debug_trace("wrote %4.4x to %4.4x\n", value, reg); |
1853030e SG |
66 | } |
67 | ||
ba457562 | 68 | static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg) |
1853030e | 69 | { |
ba457562 | 70 | writel(value, priv->base + reg); |
fffe25db | 71 | debug_trace("wrote %8.8x to %4.4x\n", value, reg); |
1853030e SG |
72 | } |
73 | ||
ba457562 SG |
74 | static void write_reg(struct ich_spi_priv *priv, const void *value, |
75 | int dest_reg, uint32_t size) | |
1853030e | 76 | { |
ba457562 | 77 | memcpy_toio(priv->base + dest_reg, value, size); |
1853030e SG |
78 | } |
79 | ||
ba457562 SG |
80 | static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value, |
81 | uint32_t size) | |
1853030e | 82 | { |
ba457562 | 83 | memcpy_fromio(value, priv->base + src_reg, size); |
1853030e SG |
84 | } |
85 | ||
ba457562 | 86 | static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr) |
1853030e SG |
87 | { |
88 | const uint32_t bbar_mask = 0x00ffff00; | |
89 | uint32_t ichspi_bbar; | |
90 | ||
91 | minaddr &= bbar_mask; | |
ba457562 | 92 | ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask; |
1853030e | 93 | ichspi_bbar |= minaddr; |
ba457562 | 94 | ich_writel(ctlr, ichspi_bbar, ctlr->bbar); |
1853030e SG |
95 | } |
96 | ||
1853030e | 97 | /* @return 1 if the SPI flash supports the 33MHz speed */ |
f2b85ab5 | 98 | static int ich9_can_do_33mhz(struct udevice *dev) |
1853030e SG |
99 | { |
100 | u32 fdod, speed; | |
101 | ||
102 | /* Observe SPI Descriptor Component Section 0 */ | |
f2b85ab5 | 103 | dm_pci_write_config32(dev->parent, 0xb0, 0x1000); |
1853030e SG |
104 | |
105 | /* Extract the Write/Erase SPI Frequency from descriptor */ | |
f2b85ab5 | 106 | dm_pci_read_config32(dev->parent, 0xb4, &fdod); |
1853030e SG |
107 | |
108 | /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ | |
109 | speed = (fdod >> 21) & 7; | |
110 | ||
111 | return speed == 1; | |
112 | } | |
113 | ||
f2b85ab5 SG |
114 | static int ich_init_controller(struct udevice *dev, |
115 | struct ich_spi_platdata *plat, | |
ba457562 | 116 | struct ich_spi_priv *ctlr) |
1853030e | 117 | { |
f2b85ab5 SG |
118 | ulong sbase_addr; |
119 | void *sbase; | |
5093badb SG |
120 | |
121 | /* SBASE is similar */ | |
3e389d8b | 122 | pch_get_spi_base(dev->parent, &sbase_addr); |
f2b85ab5 SG |
123 | sbase = (void *)sbase_addr; |
124 | debug("%s: sbase=%p\n", __func__, sbase); | |
5093badb | 125 | |
6e670b5c | 126 | if (plat->ich_version == ICHV_7) { |
f2b85ab5 | 127 | struct ich7_spi_regs *ich7_spi = sbase; |
1853030e | 128 | |
ba457562 | 129 | ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu); |
1853030e | 130 | ctlr->menubytes = sizeof(ich7_spi->opmenu); |
ba457562 SG |
131 | ctlr->optype = offsetof(struct ich7_spi_regs, optype); |
132 | ctlr->addr = offsetof(struct ich7_spi_regs, spia); | |
133 | ctlr->data = offsetof(struct ich7_spi_regs, spid); | |
1853030e | 134 | ctlr->databytes = sizeof(ich7_spi->spid); |
ba457562 SG |
135 | ctlr->status = offsetof(struct ich7_spi_regs, spis); |
136 | ctlr->control = offsetof(struct ich7_spi_regs, spic); | |
137 | ctlr->bbar = offsetof(struct ich7_spi_regs, bbar); | |
138 | ctlr->preop = offsetof(struct ich7_spi_regs, preop); | |
1853030e | 139 | ctlr->base = ich7_spi; |
6e670b5c | 140 | } else if (plat->ich_version == ICHV_9) { |
f2b85ab5 | 141 | struct ich9_spi_regs *ich9_spi = sbase; |
1853030e | 142 | |
ba457562 | 143 | ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu); |
1853030e | 144 | ctlr->menubytes = sizeof(ich9_spi->opmenu); |
ba457562 SG |
145 | ctlr->optype = offsetof(struct ich9_spi_regs, optype); |
146 | ctlr->addr = offsetof(struct ich9_spi_regs, faddr); | |
147 | ctlr->data = offsetof(struct ich9_spi_regs, fdata); | |
1853030e | 148 | ctlr->databytes = sizeof(ich9_spi->fdata); |
ba457562 SG |
149 | ctlr->status = offsetof(struct ich9_spi_regs, ssfs); |
150 | ctlr->control = offsetof(struct ich9_spi_regs, ssfc); | |
151 | ctlr->speed = ctlr->control + 2; | |
152 | ctlr->bbar = offsetof(struct ich9_spi_regs, bbar); | |
153 | ctlr->preop = offsetof(struct ich9_spi_regs, preop); | |
50787928 | 154 | ctlr->bcr = offsetof(struct ich9_spi_regs, bcr); |
1853030e SG |
155 | ctlr->pr = &ich9_spi->pr[0]; |
156 | ctlr->base = ich9_spi; | |
157 | } else { | |
ba457562 SG |
158 | debug("ICH SPI: Unrecognised ICH version %d\n", |
159 | plat->ich_version); | |
160 | return -EINVAL; | |
1853030e | 161 | } |
1853030e SG |
162 | |
163 | /* Work out the maximum speed we can support */ | |
164 | ctlr->max_speed = 20000000; | |
6e670b5c | 165 | if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev)) |
1853030e | 166 | ctlr->max_speed = 33000000; |
f2b85ab5 | 167 | debug("ICH SPI: Version ID %d detected at %p, speed %ld\n", |
ba457562 | 168 | plat->ich_version, ctlr->base, ctlr->max_speed); |
1853030e SG |
169 | |
170 | ich_set_bbar(ctlr, 0); | |
171 | ||
172 | return 0; | |
173 | } | |
174 | ||
1853030e SG |
175 | static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) |
176 | { | |
177 | trans->out += bytes; | |
178 | trans->bytesout -= bytes; | |
179 | } | |
180 | ||
181 | static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) | |
182 | { | |
183 | trans->in += bytes; | |
184 | trans->bytesin -= bytes; | |
185 | } | |
186 | ||
3e791416 BM |
187 | static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase) |
188 | { | |
189 | int lock = 0; | |
190 | ||
191 | if (plat->ich_version == ICHV_7) { | |
192 | struct ich7_spi_regs *ich7_spi = sbase; | |
193 | ||
194 | lock = readw(&ich7_spi->spis) & SPIS_LOCK; | |
195 | } else if (plat->ich_version == ICHV_9) { | |
196 | struct ich9_spi_regs *ich9_spi = sbase; | |
197 | ||
198 | lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; | |
199 | } | |
200 | ||
201 | return lock != 0; | |
202 | } | |
203 | ||
1853030e SG |
204 | static void spi_setup_type(struct spi_trans *trans, int data_bytes) |
205 | { | |
206 | trans->type = 0xFF; | |
207 | ||
9eb4339b | 208 | /* Try to guess spi type from read/write sizes */ |
1853030e SG |
209 | if (trans->bytesin == 0) { |
210 | if (trans->bytesout + data_bytes > 4) | |
211 | /* | |
212 | * If bytesin = 0 and bytesout > 4, we presume this is | |
213 | * a write data operation, which is accompanied by an | |
214 | * address. | |
215 | */ | |
216 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; | |
217 | else | |
218 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; | |
219 | return; | |
220 | } | |
221 | ||
222 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ | |
223 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; | |
224 | return; | |
225 | } | |
226 | ||
227 | if (trans->bytesout == 4) /* and bytesin is > 0 */ | |
228 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; | |
229 | ||
230 | /* Fast read command is called with 5 bytes instead of 4 */ | |
231 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { | |
232 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; | |
233 | --trans->bytesout; | |
234 | } | |
235 | } | |
236 | ||
3e791416 BM |
237 | static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans, |
238 | bool lock) | |
1853030e SG |
239 | { |
240 | uint16_t optypes; | |
ba457562 | 241 | uint8_t opmenu[ctlr->menubytes]; |
1853030e SG |
242 | |
243 | trans->opcode = trans->out[0]; | |
244 | spi_use_out(trans, 1); | |
3e791416 | 245 | if (!lock) { |
1853030e | 246 | /* The lock is off, so just use index 0. */ |
ba457562 SG |
247 | ich_writeb(ctlr, trans->opcode, ctlr->opmenu); |
248 | optypes = ich_readw(ctlr, ctlr->optype); | |
1853030e | 249 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
ba457562 | 250 | ich_writew(ctlr, optypes, ctlr->optype); |
1853030e SG |
251 | return 0; |
252 | } else { | |
253 | /* The lock is on. See if what we need is on the menu. */ | |
254 | uint8_t optype; | |
255 | uint16_t opcode_index; | |
256 | ||
257 | /* Write Enable is handled as atomic prefix */ | |
258 | if (trans->opcode == SPI_OPCODE_WREN) | |
259 | return 0; | |
260 | ||
ba457562 SG |
261 | read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu)); |
262 | for (opcode_index = 0; opcode_index < ctlr->menubytes; | |
1853030e SG |
263 | opcode_index++) { |
264 | if (opmenu[opcode_index] == trans->opcode) | |
265 | break; | |
266 | } | |
267 | ||
ba457562 | 268 | if (opcode_index == ctlr->menubytes) { |
1853030e SG |
269 | printf("ICH SPI: Opcode %x not found\n", |
270 | trans->opcode); | |
ba457562 | 271 | return -EINVAL; |
1853030e SG |
272 | } |
273 | ||
ba457562 | 274 | optypes = ich_readw(ctlr, ctlr->optype); |
1853030e SG |
275 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
276 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && | |
277 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && | |
278 | trans->bytesout >= 3) { | |
279 | /* We guessed wrong earlier. Fix it up. */ | |
280 | trans->type = optype; | |
281 | } | |
282 | if (optype != trans->type) { | |
283 | printf("ICH SPI: Transaction doesn't fit type %d\n", | |
284 | optype); | |
ba457562 | 285 | return -ENOSPC; |
1853030e SG |
286 | } |
287 | return opcode_index; | |
288 | } | |
289 | } | |
290 | ||
291 | static int spi_setup_offset(struct spi_trans *trans) | |
292 | { | |
9eb4339b | 293 | /* Separate the SPI address and data */ |
1853030e SG |
294 | switch (trans->type) { |
295 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: | |
296 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: | |
297 | return 0; | |
298 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: | |
299 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: | |
300 | trans->offset = ((uint32_t)trans->out[0] << 16) | | |
301 | ((uint32_t)trans->out[1] << 8) | | |
302 | ((uint32_t)trans->out[2] << 0); | |
303 | spi_use_out(trans, 3); | |
304 | return 1; | |
305 | default: | |
306 | printf("Unrecognized SPI transaction type %#x\n", trans->type); | |
ba457562 | 307 | return -EPROTO; |
1853030e SG |
308 | } |
309 | } | |
310 | ||
311 | /* | |
312 | * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set | |
472d5460 | 313 | * below is true) or 0. In case the wait was for the bit(s) to set - write |
1853030e SG |
314 | * those bits back, which would cause resetting them. |
315 | * | |
316 | * Return the last read status value on success or -1 on failure. | |
317 | */ | |
ba457562 SG |
318 | static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask, |
319 | int wait_til_set) | |
1853030e SG |
320 | { |
321 | int timeout = 600000; /* This will result in 6s */ | |
322 | u16 status = 0; | |
323 | ||
324 | while (timeout--) { | |
ba457562 | 325 | status = ich_readw(ctlr, ctlr->status); |
1853030e | 326 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
ba457562 SG |
327 | if (wait_til_set) { |
328 | ich_writew(ctlr, status & bitmask, | |
329 | ctlr->status); | |
330 | } | |
1853030e SG |
331 | return status; |
332 | } | |
333 | udelay(10); | |
334 | } | |
335 | ||
336 | printf("ICH SPI: SCIP timeout, read %x, expected %x\n", | |
337 | status, bitmask); | |
ba457562 | 338 | return -ETIMEDOUT; |
1853030e SG |
339 | } |
340 | ||
b42711f9 BM |
341 | void ich_spi_config_opcode(struct udevice *dev) |
342 | { | |
343 | struct ich_spi_priv *ctlr = dev_get_priv(dev); | |
344 | ||
345 | /* | |
346 | * PREOP, OPTYPE, OPMENU1/OPMENU2 registers can be locked down | |
347 | * to prevent accidental or intentional writes. Before they get | |
348 | * locked down, these registers should be initialized properly. | |
349 | */ | |
350 | ich_writew(ctlr, SPI_OPPREFIX, ctlr->preop); | |
351 | ich_writew(ctlr, SPI_OPTYPE, ctlr->optype); | |
352 | ich_writel(ctlr, SPI_OPMENU_LOWER, ctlr->opmenu); | |
353 | ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32)); | |
354 | } | |
355 | ||
ba457562 SG |
356 | static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen, |
357 | const void *dout, void *din, unsigned long flags) | |
1853030e | 358 | { |
ba457562 | 359 | struct udevice *bus = dev_get_parent(dev); |
e1e332c8 | 360 | struct ich_spi_platdata *plat = dev_get_platdata(bus); |
ba457562 | 361 | struct ich_spi_priv *ctlr = dev_get_priv(bus); |
1853030e SG |
362 | uint16_t control; |
363 | int16_t opcode_index; | |
364 | int with_address; | |
365 | int status; | |
366 | int bytes = bitlen / 8; | |
ba457562 | 367 | struct spi_trans *trans = &ctlr->trans; |
1853030e SG |
368 | unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); |
369 | int using_cmd = 0; | |
3e791416 | 370 | bool lock = spi_lock_status(plat, ctlr->base); |
ba457562 | 371 | int ret; |
1853030e | 372 | |
5d4a757c | 373 | /* We don't support writing partial bytes */ |
1853030e SG |
374 | if (bitlen % 8) { |
375 | debug("ICH SPI: Accessing partial bytes not supported\n"); | |
ba457562 | 376 | return -EPROTONOSUPPORT; |
1853030e SG |
377 | } |
378 | ||
379 | /* An empty end transaction can be ignored */ | |
380 | if (type == SPI_XFER_END && !dout && !din) | |
381 | return 0; | |
382 | ||
383 | if (type & SPI_XFER_BEGIN) | |
384 | memset(trans, '\0', sizeof(*trans)); | |
385 | ||
386 | /* Dp we need to come back later to finish it? */ | |
387 | if (dout && type == SPI_XFER_BEGIN) { | |
388 | if (bytes > ICH_MAX_CMD_LEN) { | |
389 | debug("ICH SPI: Command length limit exceeded\n"); | |
ba457562 | 390 | return -ENOSPC; |
1853030e SG |
391 | } |
392 | memcpy(trans->cmd, dout, bytes); | |
393 | trans->cmd_len = bytes; | |
fffe25db | 394 | debug_trace("ICH SPI: Saved %d bytes\n", bytes); |
1853030e SG |
395 | return 0; |
396 | } | |
397 | ||
398 | /* | |
399 | * We process a 'middle' spi_xfer() call, which has no | |
400 | * SPI_XFER_BEGIN/END, as an independent transaction as if it had | |
401 | * an end. We therefore repeat the command. This is because ICH | |
402 | * seems to have no support for this, or because interest (in digging | |
403 | * out the details and creating a special case in the code) is low. | |
404 | */ | |
405 | if (trans->cmd_len) { | |
406 | trans->out = trans->cmd; | |
407 | trans->bytesout = trans->cmd_len; | |
408 | using_cmd = 1; | |
fffe25db | 409 | debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len); |
1853030e SG |
410 | } else { |
411 | trans->out = dout; | |
412 | trans->bytesout = dout ? bytes : 0; | |
413 | } | |
414 | ||
415 | trans->in = din; | |
416 | trans->bytesin = din ? bytes : 0; | |
417 | ||
9eb4339b | 418 | /* There has to always at least be an opcode */ |
1853030e SG |
419 | if (!trans->bytesout) { |
420 | debug("ICH SPI: No opcode for transfer\n"); | |
ba457562 | 421 | return -EPROTO; |
1853030e SG |
422 | } |
423 | ||
ba457562 SG |
424 | ret = ich_status_poll(ctlr, SPIS_SCIP, 0); |
425 | if (ret < 0) | |
426 | return ret; | |
1853030e | 427 | |
6e670b5c | 428 | if (plat->ich_version == ICHV_7) |
e1e332c8 SG |
429 | ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); |
430 | else | |
431 | ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status); | |
1853030e SG |
432 | |
433 | spi_setup_type(trans, using_cmd ? bytes : 0); | |
3e791416 | 434 | opcode_index = spi_setup_opcode(ctlr, trans, lock); |
1853030e | 435 | if (opcode_index < 0) |
ba457562 | 436 | return -EINVAL; |
1853030e SG |
437 | with_address = spi_setup_offset(trans); |
438 | if (with_address < 0) | |
ba457562 | 439 | return -EINVAL; |
1853030e SG |
440 | |
441 | if (trans->opcode == SPI_OPCODE_WREN) { | |
442 | /* | |
443 | * Treat Write Enable as Atomic Pre-Op if possible | |
444 | * in order to prevent the Management Engine from | |
445 | * issuing a transaction between WREN and DATA. | |
446 | */ | |
3e791416 | 447 | if (!lock) |
ba457562 | 448 | ich_writew(ctlr, trans->opcode, ctlr->preop); |
1853030e SG |
449 | return 0; |
450 | } | |
451 | ||
ba457562 | 452 | if (ctlr->speed && ctlr->max_speed >= 33000000) { |
1853030e SG |
453 | int byte; |
454 | ||
ba457562 SG |
455 | byte = ich_readb(ctlr, ctlr->speed); |
456 | if (ctlr->cur_speed >= 33000000) | |
1853030e SG |
457 | byte |= SSFC_SCF_33MHZ; |
458 | else | |
459 | byte &= ~SSFC_SCF_33MHZ; | |
ba457562 | 460 | ich_writeb(ctlr, byte, ctlr->speed); |
1853030e SG |
461 | } |
462 | ||
463 | /* See if we have used up the command data */ | |
464 | if (using_cmd && dout && bytes) { | |
465 | trans->out = dout; | |
466 | trans->bytesout = bytes; | |
fffe25db | 467 | debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes); |
1853030e SG |
468 | } |
469 | ||
470 | /* Preset control fields */ | |
1853030e SG |
471 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
472 | ||
473 | /* Issue atomic preop cycle if needed */ | |
ba457562 | 474 | if (ich_readw(ctlr, ctlr->preop)) |
1853030e SG |
475 | control |= SPIC_ACS; |
476 | ||
477 | if (!trans->bytesout && !trans->bytesin) { | |
478 | /* SPI addresses are 24 bit only */ | |
ba457562 SG |
479 | if (with_address) { |
480 | ich_writel(ctlr, trans->offset & 0x00FFFFFF, | |
481 | ctlr->addr); | |
482 | } | |
1853030e SG |
483 | /* |
484 | * This is a 'no data' command (like Write Enable), its | |
485 | * bitesout size was 1, decremented to zero while executing | |
486 | * spi_setup_opcode() above. Tell the chip to send the | |
487 | * command. | |
488 | */ | |
ba457562 | 489 | ich_writew(ctlr, control, ctlr->control); |
1853030e SG |
490 | |
491 | /* wait for the result */ | |
ba457562 SG |
492 | status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); |
493 | if (status < 0) | |
494 | return status; | |
1853030e SG |
495 | |
496 | if (status & SPIS_FCERR) { | |
497 | debug("ICH SPI: Command transaction error\n"); | |
ba457562 | 498 | return -EIO; |
1853030e SG |
499 | } |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | /* | |
505 | * Check if this is a write command atempting to transfer more bytes | |
506 | * than the controller can handle. Iterations for writes are not | |
507 | * supported here because each SPI write command needs to be preceded | |
508 | * and followed by other SPI commands, and this sequence is controlled | |
509 | * by the SPI chip driver. | |
510 | */ | |
ba457562 | 511 | if (trans->bytesout > ctlr->databytes) { |
1853030e | 512 | debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); |
ba457562 | 513 | return -EPROTO; |
1853030e SG |
514 | } |
515 | ||
516 | /* | |
517 | * Read or write up to databytes bytes at a time until everything has | |
518 | * been sent. | |
519 | */ | |
520 | while (trans->bytesout || trans->bytesin) { | |
521 | uint32_t data_length; | |
1853030e SG |
522 | |
523 | /* SPI addresses are 24 bit only */ | |
ba457562 | 524 | ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr); |
1853030e SG |
525 | |
526 | if (trans->bytesout) | |
ba457562 | 527 | data_length = min(trans->bytesout, ctlr->databytes); |
1853030e | 528 | else |
ba457562 | 529 | data_length = min(trans->bytesin, ctlr->databytes); |
1853030e SG |
530 | |
531 | /* Program data into FDATA0 to N */ | |
532 | if (trans->bytesout) { | |
ba457562 | 533 | write_reg(ctlr, trans->out, ctlr->data, data_length); |
1853030e SG |
534 | spi_use_out(trans, data_length); |
535 | if (with_address) | |
536 | trans->offset += data_length; | |
537 | } | |
538 | ||
539 | /* Add proper control fields' values */ | |
ba457562 | 540 | control &= ~((ctlr->databytes - 1) << 8); |
1853030e SG |
541 | control |= SPIC_DS; |
542 | control |= (data_length - 1) << 8; | |
543 | ||
544 | /* write it */ | |
ba457562 | 545 | ich_writew(ctlr, control, ctlr->control); |
1853030e | 546 | |
9eb4339b | 547 | /* Wait for Cycle Done Status or Flash Cycle Error */ |
ba457562 SG |
548 | status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1); |
549 | if (status < 0) | |
550 | return status; | |
1853030e SG |
551 | |
552 | if (status & SPIS_FCERR) { | |
5d4a757c | 553 | debug("ICH SPI: Data transaction error %x\n", status); |
ba457562 | 554 | return -EIO; |
1853030e SG |
555 | } |
556 | ||
557 | if (trans->bytesin) { | |
ba457562 | 558 | read_reg(ctlr, ctlr->data, trans->in, data_length); |
1853030e SG |
559 | spi_use_in(trans, data_length); |
560 | if (with_address) | |
561 | trans->offset += data_length; | |
562 | } | |
563 | } | |
564 | ||
565 | /* Clear atomic preop now that xfer is done */ | |
d2ca80c3 BM |
566 | if (!lock) |
567 | ich_writew(ctlr, 0, ctlr->preop); | |
1853030e SG |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
f2b85ab5 | 572 | static int ich_spi_probe(struct udevice *dev) |
ba457562 | 573 | { |
f2b85ab5 SG |
574 | struct ich_spi_platdata *plat = dev_get_platdata(dev); |
575 | struct ich_spi_priv *priv = dev_get_priv(dev); | |
ba457562 SG |
576 | uint8_t bios_cntl; |
577 | int ret; | |
578 | ||
f2b85ab5 | 579 | ret = ich_init_controller(dev, plat, priv); |
ba457562 SG |
580 | if (ret) |
581 | return ret; | |
f2b85ab5 SG |
582 | /* Disable the BIOS write protect so write commands are allowed */ |
583 | ret = pch_set_spi_protect(dev->parent, false); | |
584 | if (ret == -ENOSYS) { | |
50787928 | 585 | bios_cntl = ich_readb(priv, priv->bcr); |
69fd4c38 | 586 | bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */ |
ba457562 | 587 | bios_cntl |= 1; /* Write Protect Disable (WPD) */ |
50787928 | 588 | ich_writeb(priv, bios_cntl, priv->bcr); |
f2b85ab5 SG |
589 | } else if (ret) { |
590 | debug("%s: Failed to disable write-protect: err=%d\n", | |
591 | __func__, ret); | |
592 | return ret; | |
ba457562 SG |
593 | } |
594 | ||
595 | priv->cur_speed = priv->max_speed; | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
4759dffe SR |
600 | static int ich_spi_remove(struct udevice *bus) |
601 | { | |
4759dffe SR |
602 | /* |
603 | * Configure SPI controller so that the Linux MTD driver can fully | |
604 | * access the SPI NOR chip | |
605 | */ | |
b42711f9 | 606 | ich_spi_config_opcode(bus); |
4759dffe SR |
607 | |
608 | return 0; | |
609 | } | |
610 | ||
ba457562 SG |
611 | static int ich_spi_set_speed(struct udevice *bus, uint speed) |
612 | { | |
613 | struct ich_spi_priv *priv = dev_get_priv(bus); | |
614 | ||
615 | priv->cur_speed = speed; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static int ich_spi_set_mode(struct udevice *bus, uint mode) | |
621 | { | |
622 | debug("%s: mode=%d\n", __func__, mode); | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static int ich_spi_child_pre_probe(struct udevice *dev) | |
628 | { | |
629 | struct udevice *bus = dev_get_parent(dev); | |
630 | struct ich_spi_platdata *plat = dev_get_platdata(bus); | |
631 | struct ich_spi_priv *priv = dev_get_priv(bus); | |
bcbe3d15 | 632 | struct spi_slave *slave = dev_get_parent_priv(dev); |
ba457562 SG |
633 | |
634 | /* | |
635 | * Yes this controller can only write a small number of bytes at | |
636 | * once! The limit is typically 64 bytes. | |
637 | */ | |
638 | slave->max_write_size = priv->databytes; | |
639 | /* | |
640 | * ICH 7 SPI controller only supports array read command | |
641 | * and byte program command for SST flash | |
642 | */ | |
08fe9c29 JT |
643 | if (plat->ich_version == ICHV_7) |
644 | slave->mode = SPI_RX_SLOW | SPI_TX_BYTE; | |
ba457562 SG |
645 | |
646 | return 0; | |
647 | } | |
648 | ||
1f9eb59d BM |
649 | static int ich_spi_ofdata_to_platdata(struct udevice *dev) |
650 | { | |
651 | struct ich_spi_platdata *plat = dev_get_platdata(dev); | |
e160f7d4 | 652 | int node = dev_of_offset(dev); |
1f9eb59d BM |
653 | int ret; |
654 | ||
e160f7d4 | 655 | ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi"); |
1f9eb59d | 656 | if (ret == 0) { |
6e670b5c | 657 | plat->ich_version = ICHV_7; |
1f9eb59d | 658 | } else { |
e160f7d4 | 659 | ret = fdt_node_check_compatible(gd->fdt_blob, node, |
1f9eb59d BM |
660 | "intel,ich9-spi"); |
661 | if (ret == 0) | |
6e670b5c | 662 | plat->ich_version = ICHV_9; |
1f9eb59d BM |
663 | } |
664 | ||
665 | return ret; | |
666 | } | |
667 | ||
ba457562 SG |
668 | static const struct dm_spi_ops ich_spi_ops = { |
669 | .xfer = ich_spi_xfer, | |
670 | .set_speed = ich_spi_set_speed, | |
671 | .set_mode = ich_spi_set_mode, | |
672 | /* | |
673 | * cs_info is not needed, since we require all chip selects to be | |
674 | * in the device tree explicitly | |
675 | */ | |
676 | }; | |
677 | ||
678 | static const struct udevice_id ich_spi_ids[] = { | |
1f9eb59d BM |
679 | { .compatible = "intel,ich7-spi" }, |
680 | { .compatible = "intel,ich9-spi" }, | |
ba457562 SG |
681 | { } |
682 | }; | |
683 | ||
684 | U_BOOT_DRIVER(ich_spi) = { | |
685 | .name = "ich_spi", | |
686 | .id = UCLASS_SPI, | |
687 | .of_match = ich_spi_ids, | |
688 | .ops = &ich_spi_ops, | |
1f9eb59d | 689 | .ofdata_to_platdata = ich_spi_ofdata_to_platdata, |
ba457562 SG |
690 | .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata), |
691 | .priv_auto_alloc_size = sizeof(struct ich_spi_priv), | |
692 | .child_pre_probe = ich_spi_child_pre_probe, | |
693 | .probe = ich_spi_probe, | |
4759dffe SR |
694 | .remove = ich_spi_remove, |
695 | .flags = DM_FLAG_OS_PREPARE, | |
ba457562 | 696 | }; |